GB2167630A - "Insidedness" test for point near a polygon on a visual display - Google Patents

Abstract

A device in a visual display preferably constructed as an integrated circuit, comprises a set of circuit nodes (1), preferably arranged in a regular array, each node (1) being connected to (typically eight) adjacent nodes by respective switches (2) which either close or open when a signal is applied to a node to which the switch is connected. Such signals are supplied to nodes representing the boundary of a polygon for display. A test signal is applied to a circuit node and flow of current between through node and other nodes on the polygon indicates whether the first node is inside or outside the polygon. <IMAGE>

Description

SPECIFICATION Device for use in visual display and visual display incorporating such device The present invention relates to a device for use in visual display, and to a visual display incorporating such a device. The device may be in the form of a hardware or firmware large scale integrated circuit and may be used in displays of the raster or pixel represented objects, or vector represented objects, for panel-filling, scan conversion, image processing, and the like.

Any object may be conceptually thought of as comprising a periphery or surface, which is continuous and of negligible thickness, and an inner body. From the point of view of drawing on a flat screen of a display, this is equally true for 2- and 3dimensional objects. Such drawings are usually represented on visual displays considered as a white line of edges plus an opaque inner area.

For such an edge-defined object representation, it is necessary to know which is the inside and which the outside. In the case of a display representing a three dimensional scene, objects area to be displayed at varying distances from the viewer with overlying parts or nearer objects masking more distant objects. This visibility from the point of view of the observer is crucial in such three dimensional pictures.

Software approaches to this problem fall into two general classes, namely edge processing and scan conversion or panel filling. The former approach exhaustively tests whether edges cross each other and their depth with respect to the observer so as to determine their visibility. This method is more applicable to vector representation. The other approach is more suitable for raster representation and bit-mapped graphics. In this case, the edges and the inner body are represented as pixels (either on or off or a grey level or colour level) or voxels (three dimensional equivalent of pixels). Each pixel at any depth has a unique address or set of coordinates (x,y, z).If inner pixels were opaque and edge pixels white or coloured differently, the display of the most anterior with respect to the observer at any (x,y) or overwriting from the most posterior would produce a three dimensional picture. The problem thus effectively becomes that of determining automatically the "insideness" of an edge-defined structure. Such scan conversion or panel-filling has been solved in several ways with software where the periphery is continuous and integerised into an x, y grid where each step touches each other. Software methods for handling this problem include searching systematically or randomly outwardly from a pregiven or calculated central point, maze-like wall following, counting boundary crossings (Jordan curvetheorem) with special checking of concave and convex vertices, etc.All such methods lack clearly appropriate stopping rules and are relatively slow because of the large amount of checking which is involved.

According to the invention, there is provided a device for use in visual display, comprising a set of circuit nodes, each of which is connected to each circuit node of a subset of the set of circuit nodes by a respective switch means selectively operable to permit or prevent the flow of current, and means for applying a potential difference between and for detecting the flow of current between selected pairs of the circuit nodes.

Preferably each switch means is arranged to be actuated and de-actuated in response to the application of first and second potentials or polarities, respectively, to either or one of the circuit nodes to which it is connected. Actuation and de-actuation of the switch means may correspond to permitting and preventing, respectively, or to preventing and permitting, respectively, the flow of current.

The circuit nodes and switch means may be arranged as an array, for instance a two dimensional array of rectangular type in which each circuit node is connected to four or eight adjacent nodes by respective swtiches. Preferably, the array has a boundary defined by a boundary subset of the set of circuit nodes. One of each of the selected pairs of the circuit nodes may be a member of the boundary subset. Alternatively, the boundary circuit nodes may be connected via respective switch means to a common connection which constitutes one of every selected pair. As a further alternative, the selected pair may comprise any pair of the circuit nodes.

The device is preferably an integrated circuit, for instance a MOS or CMOS integrated circuit, in which the switch means comprise transmission gates, for instance controlled by stored gate charge.

According to another aspect of the invention, there is provided a visual display apparatus including a device according to the invention.

It is thus possible to provide a hardware or firmware "insideness checker" which may allow the "insideness" of a display pattern to be checked more quickly than is possible with software solutions, for instance of the types described above.

Such a device is automatic in that it need not "know" which is inside before it commences checking. When constructed as an integrated circuit, the device is relatively cheap as it may be constructed by means of technology of the type used to provide integrated circuit random access memory. Further, only one passage through the data is necessary in order to check the insideness of one closed polygon, and thus the entire defect.

In general, such a device will be used with bitmapped graphics to a VDU screen capable of representing M, x M2 pixels. The VDU will generally contain a continuous or integerised stepped stream of periphery coordinates (xy), with no gaps greater than or equal to pixel size, at a plane of depth z that is a closed polygon with each polygon separated by a "new polygon flag".Appropriate hardware or software means will generally be provided for any required (xyz) transformation before display, such as rotation, reflection, zoom, translation, interpolation, or closure The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram of part of a device constituting a preferred embodiment of the invention; Figure 2 is a block diagram of the device of Figure 1; and Figure 3 is a block diagram showing part of a display or VDU including a device as shown in Figures 1 and 2.

Figure 1 is a circuit diagram of a "corner" portion of the device comprising a plurality of circuit nodes 1. The circuit nodes are arranged, either notionally or physically, in the form of a two-dimensional rectangular array on an integrated circuit to form a set of nodes. Each node is connected to each circuit node of a subset of the set of circuit nodes by respective switch means 2. The subset for each circuit node comprises those circuit nodes which are rectangularly or diagonally adjacent the node. Thus, each subset comprises eight such circuit nodes connected to the "central" circuit node by eight switch means, respectively.The switch means are in the form of transmission gates provided with control means (not shown) for switching all the switch means at that node between their conducting and non-conducting states in response to the application at an adjacent circuit node of first and second potentials or potential polarities, respectively. In the embodiment shown, the switch means will normally be conducting, or will be set to the conducting state when the device is initialised. When the appropriate potential or polarity is supplied via decoding means (described hereinafter) to a circuit node, the eight switches connected to that node are set to their non-conducting state. The switches remain in this state unless or until a second (different) potential or polarity is supplied to an adjacent circuit node.Thus, if the first potential or polarity is applied to two adjacent circuits nodes, the inter-connecting switch means remains in its non-conducting state ie it is not reset by the second application of the first potential or polarity.

The circuit nodes at the periphery or boundary of the array form a subset and each such circuit node is connected via a respective switch means 3 to a reference line 4. In the embodiment shown, the reference line 4 constitutes an input or output of the device.

Figure 2 shows the array 10 of circuit nodes and switches together with x, y test address decoders 11 and 12, respectively, and x, y control address decoders 13 and 14. Each of the decoders 11 to 14 has, for instance, an eight bit input bus 15 to 18, respectively and an output bus 19 to 22, respectively, comprising 27 individual addressing lines for the rows and columns of circuit nodes. In order to control the switches directed to a particular circuit node such that they are in the non-conducting state, the address of that circuit node in terms of eight bit x, y coordinates is supplied on the buses 17 and 18 to the control decoders 13 and 14.This process is repeated so as to enter at least the edge of a shape to be displayed into the device so that the edge will be effectively represented by a subset of the set of circuit nodes in which the adjacent switches of each actuated node are non-conducting, and having essentially the same shape as the image produced on the screen of the VDU.

When it is desired to test whether a particular pixel is inside or outside the boundary, the address of the corresponding circuit node is supplied on the buses 15 and 16 to the test decoders 11 and 12. A measuring voltage is supplied by the decoders 11 and 12 to the corresponding circuit node and the reference line 4 supplies a current if that circuit node is outside the boundary, whereas no current is supplied is that circuit node is inside the boundary.

Figure 3 shows part of a display or VDU including the device 30 shown in Figures 1 and 2. Display data are supplied from a CPU, logic circuit, frame store or the like on a line 31 to a circuit 32 for processing the data into the appropriate form (eg rotation, interpolation). Thus, the currently addressed z value of the data is supplied on line 33 to the CPU, logic circuit or screen controller for providing a pixel display or, if required, is stored with its x, y values. The x, y coordinates are supplied to a clipper circuit 34 whose outputs are connected to the data buses 17 and 18 for controlling the switch means of the addressed circuit node within the device 30. The x, y data are also supplied to a minimax circuit 35 whose outputs are connected to the buses 15 and 16.The clipper circuit 34 is used to determine when the x, y data represents a circuit node or pixel which is off the screen and controls actuation of switches connected to circuit nodes in the boundary subset so as to complete an edge which overspills the screen. The minimax circuit 35 supplies addresses to the buses 15 and 16 and may, for instance, comprise a scan controller constituted by a pleurality of cascaded binary counters, a clock, etc. The reference line 4 is connected to a current sensor 36 whose output is connected to the CPU, logic circuit, screen controller, frame store or the like. The buses 15 and 16 also constitute an output to the CPU, logic circuit, screem controller, frame store or the like for identifying the circuit node, and hence the corresponding pixel, which is being tested for its insideness.

In a typical application of the device and display, the switch means are initialised so that they are conducting and the display screen will be initialised so as to be blank. Transformed data for continuously touching pixel coordinates are then supplied to the device so as to open the switches connected to the corresponding circuit nodes, with the clipper circuit 34 determining when the coordinates go off the edge of the array so as to open the switches connected to the boundary circuit nodes in order to close the polygon if necessary.

The minimum and maximum values of x, y are also stored. The polygon is closed if necessary The periphery of the polygon or image is displayed, for instance as a white line, on the screen at the same time if the z value of the corresponding pixels indicate that the image is closer to the observer than that currently on the screen at that x, y location.

On reaching a "new polygon flag", the circuit nodes are scanned from (maxx)-1 to (min x)+1 for (max y)-1 to (min y)+1 by applying a voltage with respect to the reference line 4 to each of the circuit nodes in turn and detecting by the sensor 36 whether a current flows. If there is no flow of current for that particular circuit node and corresponding pixel position, then that pixel is inside the polygon whereas flow of current indicates that it is outside. As each pixel is determined to be inside or outside the polygon, its "colour" or opaqueness (transparent ie blank, usually representing outside) is displayed on the screen according to whether its calculated value z is nearer the observer than that currently displayed on the screen at that x, y.The values x, y, z corresponding to the pixels may be stored if required as each circuit node is tested. Thus, the speed of this operation will be determined by the area of the polygon and hence by the total volume of the displayed image.

The device is preferably constructed in the form of an integrated circuit and the structure has some similarities to that of a random access memory. A single device may be used for displays having a resolution, and hence number of pixels, within the capacity of the available integration technology so as to provide a single device for use with a screen.

Alternatively, it is possible for several such devices to be interconnected so as to provide the necessary resolution over a screen if this cannot be achieved with the current level of integration or packing density of devices on to a single chip.

It is thus possible to provide a device which may be used for graphic processing, particularly in a raster/pixel type of display. The device may be used for automatic or requested panel-fill in any colour, scan conversion, hidden line and hidden surface removal for CAD, CAM, sectional reconstructions, animations, and the like.

The device shown in the drawings may be modified so as to permit extra information to be obtained, for instance whether a polygon contains another polygon. In this case, instead of using the peripheral reference line 4 as one terminal for testing whether current flows, additional address decoding and the like may be provided so as to permit two circuit nodes to be used for testing the conductivity therebetween. Similarly, the device may be used for polygons which are topologically equivalent to a circle but which contain "holes", which are defined as "outside" the surrounded by "inside" or "inside" surrounded by "outside" depending on choice of circuit nodes for testing.

Claims (12)

1. A device for use in visual display, comprising a set of circuit modes, each of which is connected to each circuit mode of a subset of the set of circuit modes by a respective switch means selectively operable to permit or prevent the flow of current, and means for applying a potential difference between and for detecting the flow of current between selected pairs of the circuit modes.

2. A device as claimed in claim 1, in which each switch means is arranged to be actuated and deactuated in response to the application of first and second potentials or polarities, respectively, to either or one of the circuit modes to which it is connected.

3. A device as claimed in claim 1 or 2, in which the circuit modes and switch means are arranged as an array.

4. A device as claimed in claim 3, in which the array is a two-dimensional array.

5. A device as claimed in claim 4, in which the array is of rectangular type and each circuit mode is connected to for or eight adjacent circuit modes by respective switches.

6. A device as claimed in anyone of claims 3 to 5, in which the array has a boundary defined by a boundary subset of the set of circuit modes.

7. A device as claimed in claim 6, in which one of each of the selected pairs of the circuit modes is a member of the boundary subset.

8. A device as claimed in claim 6, in which the boundary circuit modes are connected via respective switch means to a common connection which constitutes one of every selected pair of the circuit modes.

9. A device as claimed in any one of the preceding claims in the form of an integrated circuit.

10. A device as claimed in claim 9 in the form of a MOS or CMOS integrated circuit, in which the switch means comprise transmission gates.

11. A device substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

12. A visual display apparatus including a device as claimed in any one of the preceding claims.