GB2167230A - Semiconductor processing - Google Patents
Semiconductor processing Download PDFInfo
- Publication number
- GB2167230A GB2167230A GB08506073A GB8506073A GB2167230A GB 2167230 A GB2167230 A GB 2167230A GB 08506073 A GB08506073 A GB 08506073A GB 8506073 A GB8506073 A GB 8506073A GB 2167230 A GB2167230 A GB 2167230A
- Authority
- GB
- United Kingdom
- Prior art keywords
- galnasp
- layer
- diffusion
- inp
- capsule
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 239000011701 zinc Substances 0.000 claims abstract description 26
- 239000002775 capsule Substances 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 229910052725 zinc Inorganic materials 0.000 claims abstract description 18
- 239000002019 doping agent Substances 0.000 claims abstract description 17
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 9
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 5
- 229910052793 cadmium Inorganic materials 0.000 claims abstract description 4
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract 6
- 238000000034 method Methods 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000004943 liquid phase epitaxy Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000000203 mixture Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 30
- 235000012431 wafers Nutrition 0.000 description 16
- 239000008187 granular material Substances 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2258—Diffusion into or out of AIIIBV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Lasers (AREA)
Abstract
Diffusion of a volatile dopant, for example zinc or cadmium, into a surface region of an InP based material (5), in particular GaInAsP, to which electrical contact (8) is to be made is carried out, for example, in a closed capsule with an overpressure of Zn, As and P, with the surface region in intimate contact with a surface of a GaAs wafer (9 - Fig. 2) which surface is doped with the volatile dopant. This has the effect that the InP based material sees a high concentration of the volatile dopant at all times as well as altering the surface alloy composition so that it is higher in GaAs following diffusion, resulting in a higher electrical doping density. <IMAGE>
Description
SPECIFICATION
Semiconductor processing
This invention relates to semiconductor processing and in particular to the contacting of
InP based lasers and other devices.
According to one aspect of the present invention there is provided a method of processing a surface region of InP based material to which electrical contact is to be made, including the step of diffusing a volatile dopant into said surface region whilst said surface region is in intimate contact with a surface of a semiconductor body, which surface is doped with said dopant.
According to another aspect of the present invention there is provided a method of manufacturing a semiconductor laser including the steps of forming consecutive layers of n-type
InP, undoped GalnAsP, p-type InP and p-type
GalnAsP by liquid phase epitaxy on an n-type
InP substrate, providing a silicon dioxide layer on the p-type GalnAsP layer, etching channels in the silicon dioxide layer whereby to expose portions of the p-type GalnAsP layer, and diffusing a volatile dopant into the exposed portions of the p-type GalnAsP layer whilst the exposed portions are in intimate contact with a surface of a GaAs wafer, which surface is doped with said dopant.
Embodiments of the invention will now be described with reference to the accompanying drawings, in which:
Figure 1 shows a section through a semiconductor laser, and
Figure 2 shows schematically zinc diffusion in a capsule and according to the present invention.
The laser structure illustrated in Fig. 1 comprises a n-type InP substrate 1 upon which are grown by liquid phase epitaxy an n-type
InP layer 2, an undoped GalnAsP active layer 3, a p-type InP layer 4, and a p-type GalnAsP contacting layer 5. A silicon dioxide layer 6 is deposited on layer 5 and a window 7 opened therein. A metallisation layer 8 is provided on layer 6 and extends into window 7 to electrically contact layer 5. Alternatively the layer 5 may be omitted so that the metallisation layer 8 is to contact layer 4 directly. Thus the metallisation layer 8 is required to electrically contact a p-type GalnAsP layer or a p-type
InP layer that, is it is required to contact an ptype InP based layer.Now, InP is difficult to contact and in order to achieve a low resistance ohmic contact to the InP based layer following metallisation it has previously been proposed to perform a shallow Zn diffusion to produce a highly doped p+ surface region of the InP based layer.
The Zn diffusion is conventionally carried out by disposing the wafers in which the lasers are being formed in a closed capsule containing a quantity of Zn and As in order to produce an overpressure of Zn and As and diffuse Zn into the InP based layer. The slices are stacked up on an InP base in the capsule.
The closed capsule is then placed in a furnace at 550 C. If the capsule is left in the furnace for seven minutes the subsequently measured threshold current (It) is good, with a usually reasonable forward voltage (VF). If the time in the furnace is increased to fifteen minutes the threshold current is increased, this being undesirable, whilst the forward voltage is usually good. However, with longer diffusion times there is the danger that diffusion into the undoped active layer will occur.We have measured the temperature within the capsule, by means of a thermocouple inserted into its neck, and found that after seven minutes in a 5500C furnace the interior capsule temperature is actually of the order of 535 C, and after fifteen minutes the interior capsule temperature is actually of the order of 545 C.
Now, if an InP wafer is covered by a GaAs wafer with a gap therebetween of the order of O to 100#m and is heated at 5500C in hydrogen then both Ga and As are transported from the GaAs wafer to the surface of the
InP wafer.
Use of a cover slice of GaAs has previously been made to protect InP wafers prior to liquid phase epitaxial growth as in the manufacture of IRW (Inverted Rib Waveguide) lasers. In the manufacture of IRW lasers a channel is first etched in an InP substrate and the epitaxial layers equivalent to the layers 2 to 4 or 5 grown thereon by liquid phase epitaxy.
The epitaxy process takes place at some 600-700 C and the covering of an InP wafer by another InP wafer results in mass transport of InP and undesirable smoothing of the etched channel. To prevent this, GaAs cover slices are provided for the etched InP wafers, no such mass transport of InP occurs and the etched channel retains its shape for the epitaxy process.
The GalnAsP layer 5 may be regarded as (GaAs),(lnP),. GaAs has a forward voltage of less than 1.4 volts with an excess of less than 0.1 volts, whereas InP has a forward voltage of 2 to 3 volts with an excess of 1 to 2 volts. If, therefore, the exposed surface of the GalnAsP layer 5 could be treated to produce a surface layer with the structure (GaAs),(lnP), where A7X then the contact resistance will be reduced and the forward VF reduced.
We have found that this can be achieved by carrying out the zinc diffusion in a closed capsule with amounts of Zn and As therein to create an overpressure thereof as is conventional but with the InP laser wafers in intimate contact (spaced apart by 0 to 100,umì with heavily Zn doped GaAs wafers, as illustrated schematically in Fig. 2. Since there is at least one InP surface inside the capsule, this surface will emit phosphorus and thus the over pressure will be of Zn, As and P whilst the diffusion is carried out. The GaAs wafer 9 has a surface doping of Zn on its uppermost face at approximately the 1 % level. A laser wafer 10 with channels 11 etched in its oxide 12 is disposed channel-side down on the GaAs wafer 9.This arrangement is disposed together with Zn and As granules 13 and 14 in a capsule 15 which is sealed. The sealed capsule is placed in a 55000 furnace for seven minutes. The resultant laser devices have a low forward voltage and a low threshold current. Placing the laser wafer in intimate contact with the heavily zinc doped GaAs ensures that the InP based material sees a high zinc concentration at all times and the composition of the (GaAs)(lnP) alloy on the surface exposed by the channels etched in the oxide will be beneficially altered by being higher in the
GaAs fraction after the diffusion, which results in a higher electrical doping density. Whereas the Zn granules provide Zn vapour in the capsule for diffusion the heavily Zn doped GaAs also acts as a diffusion source.
It is not necessary that the technique be carried out in a closed capsule. It may be carried out in an open tube with an ambient gas, such as argon or hydrogen flowing through it. In this case the granules of As and
Zn would not be included. In fact the As and
Zn granules may be omitted from a closed capsule technique since they are not considered to be essential.
Whereas the p-dopant has so far been described as zinc, other volatile p or n dopants may be employed, in particular cadmium as another p-dopant.
Claims (16)
1. A method of processing a surface region of InP based material to which electrical contact is to be made, including the step of diffusing a volatile dopant into said surface region whilst said surface region is in intimate contact with a surface of a semiconductor body, which surface is doped with said dopant.
2. A method as claimed in claim 1, wherein said dopant comprises zinc or cadmium.
3. A method as claimed in claim 1 or claim 2, which diffusion is carried out with said surface region and semiconductor body in a closed capsule.
4. A method as claimed in claim 1 or claim 2, which diffusion is carried out with said surface region and semiconductor body in an open tube with an ambient gas flowing through it.
5. A method as claimed in any one of the preceding claims, wherein the semiconductor body is of GaAs.
6. A method as claimed in claim 3, wherein the semiconductor body is of GaAs, the InP based material is GalnAsP and the diffusion is carried out with an overpressure of
P in the capsule.
7. A method as claimed in claim 6, wherein the overpressure is of Zn, As and P.
8. A method as claimed in claim 7, wherein the capsule is disposed in at furnace at 55000 for seven minutes to perform said diffusion process.
9. A method of manufacturing a semiconductor laser including the steps of forming consecutive layers of n-type InP, undoped
GalnAsP, p-type InP and p-type GalnAsP by liquid phase epitaxy on an n-type InP substrate, providing a silicon dioxide layer on the p-type GalnAsP layer, etching channels in the silicon dioxide layer whereby to expose portions of the p-type GalnAsP layer, and diffusing a volatile dopant into the exposed portions of the p-type GalnAsP layer whilst the exposed portions are in intimate contact with a surface of a GaAs wafer, which surface is doped with said dopant.
10. A method as claimed in claim 9, wherein said dopant comprises zinc or cadmium.
11. A method as claimed in claim 9 or claim 10, wherein the diffusion is carried out with the GaAs wafer disposed in a closed capsule together with the partly manufactured semiconductor laser, there being an overpressure of P in the capsule.
12. A method as claimed in claim 11, wherein the overpressure is of Zn, As and P.
13. A method as claimed in claim 12, wherein the capsule is disposed in a furnace at 55000 for seven minutes to perform the diffusion process.
14. A method as claimed in any one of claims 9 to 13 including the step of metallising the surface of the GalnAsP layer into which the volatile dopant was diffused.
15. A method of processing a surface region of an InP based material substantially as herein described with reference to and as illustrated in the accompanying drawings.
16. A method of manufacturing a semiconductor laser substantially as herein described with reference to and as illustrated in the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB848428888A GB8428888D0 (en) | 1984-11-15 | 1984-11-15 | Semiconductor processing |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8506073D0 GB8506073D0 (en) | 1985-04-11 |
| GB2167230A true GB2167230A (en) | 1986-05-21 |
| GB2167230B GB2167230B (en) | 1988-09-14 |
Family
ID=10569780
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB848428888A Pending GB8428888D0 (en) | 1984-11-15 | 1984-11-15 | Semiconductor processing |
| GB08506073A Expired GB2167230B (en) | 1984-11-15 | 1985-03-08 | Semiconductor processing |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB848428888A Pending GB8428888D0 (en) | 1984-11-15 | 1984-11-15 | Semiconductor processing |
Country Status (1)
| Country | Link |
|---|---|
| GB (2) | GB8428888D0 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0194499A2 (en) * | 1985-03-15 | 1986-09-17 | International Business Machines Corporation | Process for diffusing impurities into a semiconductor body |
| WO1987004006A1 (en) * | 1985-12-18 | 1987-07-02 | Allied Corporation | Proximity diffusion method for group iii-v semiconductors |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1101909A (en) * | 1967-01-13 | 1968-02-07 | Standard Telephones Cables Ltd | Method for producing gallium arsenide devices |
-
1984
- 1984-11-15 GB GB848428888A patent/GB8428888D0/en active Pending
-
1985
- 1985-03-08 GB GB08506073A patent/GB2167230B/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1101909A (en) * | 1967-01-13 | 1968-02-07 | Standard Telephones Cables Ltd | Method for producing gallium arsenide devices |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0194499A2 (en) * | 1985-03-15 | 1986-09-17 | International Business Machines Corporation | Process for diffusing impurities into a semiconductor body |
| EP0194499A3 (en) * | 1985-03-15 | 1989-12-13 | International Business Machines Corporation | Process for diffusing impurities into a semiconductor body |
| WO1987004006A1 (en) * | 1985-12-18 | 1987-07-02 | Allied Corporation | Proximity diffusion method for group iii-v semiconductors |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2167230B (en) | 1988-09-14 |
| GB8428888D0 (en) | 1984-12-27 |
| GB8506073D0 (en) | 1985-04-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |