GB2167219A - Data decoder - Google Patents

Abstract

A data decoder, for processing data encoded in accordance with Information Theory for reduced average bit count but variable word length, comprises a 32K 8-bit memory (30) with output bit serialisation connected to an 8-bit shift register (48) into which data bits are clocked serially. On each clock cycle, the shift register contents are compared with data codes by comparators (58). Code identification is notified to a computer for decoding and subsequent shift register reset prior to operation repetition. The computer also indicates an initial start address to the memory (30) and controls clock operation. For coded data including interspersed uncoded data, the decoder includes a comparator (58d) arranged to detect a recognition code and the computer is arranged to effect output of and read the appropriate number of uncoded data bits. <IMAGE>

Description

SPECIFICATION Data decoder This invention relates to a data decoder, and more particularly but not exclusively to a decoder for dealing with variable word length data encoded for reduced redundancy in accordance with Information Theory.

Information Theory provides a means for reducing data to more manageable proportions.

There is provided a discussion of this in inter alia "Key papers in the Development of Information Theory", Ed. D Slepian, IEEE, 1974.

Examples of this include data encoding using Shannon or Huffman coding. The approach involves the principle that information has a value in accordance with its unexpectedness, ie the value is an inverse function of the information occurrence probability. The length of a message is clearly largely controlled by the number of characters required to indicate the more probable items of information. Data reduction is accordingly possible if more probable items of information are coded in fewer characters or bits than less probable items.

In Shannon coding, the approach is to arrange information items in descending order of occurrence frequency. The most frequently occurring item is assigned the fewest number of bits, ie the shortest code. The second is assigned a slightly longer code, and so on with code length increasing as occurrence frequency decreases. Use of these codes results in appreciable data reduction when the occurrence probability of information items varies significantly.

Use of data reduced by coding is unfortunately difficult for conventional computers, which are arranged to process data words of fixed bit length. Complex computer programmes are required to deal with variable bitlength data, and this reduces speed of data analysis negating the benefit of data reduction.

Furthermore, in the case of microprocessors, the operating speed is far too low for reduced data analysis at any acceptable rate.

It is an object of the present invention to provide a data decoder for processing data coded in accordance with Information Theory.

The present invention provides a data decoder including: a bit-serial memory to contain coded data; a serial to parallel converter arranged to receive successive data bits from the memory; means for comparing serial to parallel converted data with each of a plurality of stored data codes, such comparing means being operative after output of each data bit from the memory; means for identifying successive data codes after matching with respective coded data; means for interpreting identified data codes; and means for controlling operation of the memory, serial to parallel converter and comparing means.

The invention provides the advantage that a stream of data codes of varying length can be compared with stored codes, identified and decoded without the need for computer software adapted to process varying word length data. This can provide a processing speed advantage of two orders of magnitude or better, and renders data reduction by Information Theory viable for digital electronic purposes.

Comparison of coded data with stored codes may be carried out by a computer. In a preferred embodiment however, one or more comparators are employed. A plurality of comparators may be arranged in parallel for simultaneous comparison of converted data with respective stored codes. Alternatively, one comparator may be used with a code store, and be arranged to compare each stored code in turn with converted data.

The means for identifying data codes nay comprise lines from the comparing means to a computer, the computer also being arranged for decoding data codes.

The means for controlling operation of the memory, serial to parallel converter and comparing means may include a clock. The clock is arranged for remote initiation under computer control, and each clock pulse triggers bit output from the memory together with operation of the serial to parallel converter and comparing means. The controlling means may also include means for stopping the clock in response to a code match by the comparing means, and for resetting the converter for a subsequent match.

The invention may also be arranged for processing coded data interspersed with uncoded data preceded by a recognition code. The length of each uncoded data item may be indicated by part of the recognition code or a word or words following it. The computer previously referred to may be arranged to read appropriate numbers of data bits from the serial to parallel converter in response to identification of the recognition code. To facilitate this, the controlling means may be arranged to receive the data item bit count from the computer, and to operate the clock until the appropriate number of bits has been output by the memory and read by the computer from the serial to parallel converter.

The invention preferably includes a computer as previously referred to and programned to: receive signals indicating memory start addresses; indicate start addresses to the memory; initiate operation of the controlling means in both code and data read modes; read data output from the memory; interpret both coded and uncoded data; and co-operate with any device interfacing therewith.

In order that the invention might be more fully understood, an embodiment thereof will now be described by way of example only with reference to the accompanying drawings, in which: Figure 1 is a schematic block diagram of a decoder of the invention; Figure 2 is a more detailed circuit diagram of a decoder of the invention with the omission of an interfacing computer, a display and control panel shown in Figure 1; and Figure 3 is a code identifier circuit providing an alternative to the comparator arrangement in Figure 2.

Referring to Figure 1, there is schematically shown a data decoder 10 of the invention connected to a computer 12 arranged for the display of decoded data. The computer 12 is operator controlled via a control panel 14, and displays decoded information on a visual display unit (VDU) 16.

The decoder 10 comprises a bit memory 18 to provide bit serial data to a serial to parallel converter 20. A code identifier 22 receives the data, and indicates both code identities to the computer 12 and when appropriate code detection to a controller 24. The controller 24 controls output from the bit memory 18 in response to instructions from the computer 12 and code detection signals from the code identifier 22.

Data contained in the memory 18 is largely in the form of Shannon coded information, but also includes a small proportion ( 1%) of uncoded data or instructions for the computer 12. Each such uncoded item is prefaced by a respective code instructing the computer to read data.

The Figure 1 arrangement operates as follows. An operator uses the control panel 14 to furnish the computer 12 with a start point from which information in the memory 18 is to be taken. Bit-serial information is fed from the memory 18 to the converter 20 for conversion into fixed bit-length words. Each word changes on each operation cycle by receiving a new least significant bit (Isb), losing its most significant bit (msb) and increasing by unity the bit significance of all other bits. Successive words are compared with codes stored in the identifier 22, which instructs the computer 12 as to which code has been identified.

Shannon codes corresponding to reduced information are interpreted by the computer 12 using a look-up table (not shown). The code designated as a computer instruction or data preface instructs the computer 12 to read subsequent data bits from the converter 20.

The data is then employed by the computer in accordance with its stored programme, and might indicate for example graphics information for the VDU 16.

After code recognition, or when appropriate data receipt, the computer 12 resets the word contained in the converter 20 to zero.

On the subsequent clock cycle a bit is output from the memory 18 to the converter 20 and thence to the identifier 22. The code identification procedure then proceeds once more.

The codes implemented by the identifier 22 may be fixed, or alternatively programmable from the computer via a link indicated by chain line 26.

Referring now also to Figure 2, there is shown a more detailed circuit diagram of a data decoder 10 in accordance with the invention, except that the computer 12, VDU 16 and panel 14 are not shown. The bit memory 18 comprises a conventional memory 30 storing 32K 8-bit words or bytes, an 8 to 1 mul tipiexer 32 and an 18-bit counter 34. Counter output bits Ao to A2 are fed to the multiplexer 32 and bits A3 to A,7 to the memory 30 via 3-bit and 15-bit buses 36 and 38 respectively. An 8-bit bus 40 connects memory 30 to multiplexer 32. The computer 12 furnishes the counter 34 with a start point (start address minus one) via an 18-bit bus 44 and a "set start point" instruction via a line 46. The serial to parallel converter 20 is implemented by an 8-bit shift register 48 connected to multiplexer 32 by a line 50.The register 48 has an 8-bit output bus 52 with branches 54 and 56. Branch 54 is connected to the computer 12, and branch 56 to the code identifier 22 implemented as four comparators 58a to 58d arranged in parallel. Comparators 58a to 58c contain respective Shannon codes, and comparator 58d is a code indicating that uncoded data follows. Four lines 60a to 60d are connected from respective comparators 58a to 58d both to the computer 12 and to the controller 24.

The controller 24 is implemented as follows.

It comprises a four input OR gate 62 connected to lines 60 and to an AND gate 64 driving a two input OR gate 66. The OR gate 66 has a second input from a second AND gate 68 having one polarity reversing input 70. A one-bit CODE/DATA line 72 is connected from the computer 12 to AND gate 64 and input 70. The output of OR gate 66 is connected to a clock 74, which stops on receipt of a rising pulse edge. The clock 74 starts on receipt of a falling pulse edge from the computer 12 via a line 76, and such a pulse also resets shift register 48 via a line 78. A 3-bit data bus 80 is connected from the computer 12 to a 3-bit comparator 82.

The clock 74 is connected via a line 84 to a 3-bit counter 86 incremented by pulse rising edges. The counter 86 provides a 3-bit output via a bus 88 to the comparator 82, and is resettable by the computer 12 via a line 90 connected to line 76. The comparator 82 provides a second input to AND gate 68 via a line 92. It will have been appreciated that the controller 24 incorporates gates 62 to 68, clock 74, counter 86, comparator 82 and associated connections. The clock 74 supplies clock signals to the rising edge-triggered coun ter 34 via a line 94. The line 94 and clock signals are connected via lines 96 and 98 to the falling edge triggered shift register 48 and comparators 58. Line 96 is connected to all four comparators 58, whose operation is enabled upon receipt of a falling edge clock pulse.Their operation is disabled by a pulse rising edge from line 78 via a connection 100, ie in response to a reset signal from the computer 12.

The Figure 2 arrangement operates as follows. The computer 12 is controlled via the panel 14 to furnish a "set start point" pulse and start point to counter 34 via line 46 and bus 44 respectively. The start point is one less than the required start address. Simultaneously, the computer 12 places a start pulse on lines 78 and 76 to reset the shift register 48 to zero and start the falling edgetriggered clock 74. The rising edge of the first clock pulse on line 94 starts the counter 34, which thereafter continues under clock control. The computer 12 holds CODE/DATA line 76 high to provide for a code search. The high signal on line 72 ensures that gate 70 has a 0 output. Gate 64 will also have a 0 output until any one of the comparators 58 indicates a code match, which provides a 1 input to OR gate 62.OR gate 66 accordingly has a 0 output in the absence of a code match, and clock 74 does not receive a stop signal until a match is detected.

On the rising edge of the first clock pulse, the counter 34 increments the start point by 1 and furnishes the multiplexer 32 and memory 30 with the resulting start address. Counter output bits A3 to A,7 address a corresponding 8-bit word in memory 30 for output to multiplexer 32. Bits Ao to A2 indicate to multiplexer 32 which bit of the memory output word is to be presented to shift register 48.

Subsequent clock pulses increment the count and supply successive bits of the memory output word to shift register 48, the output word changing at 8-bit intervals. This interval does not necessarily apply to the change from first to second memory output word, since the start address may occur part way through a word. The multiplexer/8-bit memory arrangement is a convenient way of implementing a bit-serial memory with commercially available components.

The falling edge of the first clock pulse on lines 98 and 96 clocks the first memory word bit on line 50 into shift register 48 and enables all comparators 58. Designating this first bit as b, the shift register output is 0000000b for comparison with their stored codes by all four comparators 58. If no match occurs, each of lines 60 and OR gate 62 inputs receive 0.

OR gate 66 is now in receipt of two Os effecting a 0 output to clock 74, which therefore continues operation producing a second clock pulse. This cycle of operations repeats until one of the comparators' stored codes matches the contents of shift register 48. The comparator output changes from 0 to 1, and the computer 12 receives 0001, 0010, 0100 or 1000 on lines 60 according which of comparators 58 has matched. This indicates either a Shannon code (comparators 58a to 58c) or that data follows (comparator 58d). In the former case, the computer 12 carries out a decoding operation employing its internally programmed look-up table, and outputs corresponding data (a pixel address) to the VDU 16. At the same time, OR gate 62 has received a 1 input and CODE/DATA line 72 is high. AND gate 64 output therefore goes high, and as also that of OR gate 66. This stops clock 74.The computer 12 then pulses lines 76, 78 and 90 high to seek the next code.

Shift register 48 and counter 86 become reset to zero, comparators 58 are disabled, and clock 74 restarts. In the case of comparator 58d providing a match, the computer 12 sets CODE/DATA line 72 low and presents the appropriate bit count to comparator 82 via line 80. It then pulses lines 76, 78, 90 and 100 high to start clock 74, reset both counter 86 and shift register 48 and disable comparators 58. Clock pulses continue until the contents of counter 86 match the input bit count, when comparator 82 presents a high input to gate 68. Shift register 48 now contains a number of bits equal to the number of clock pulses.

By virtue of inverting input 70 being low and line 92 high, gate 68 output goes high and so also OR gate 66 output. Clock 74 accordingly stops, at which point the computer 12 reads the appropriate number of data bits via bus 54. The data bits are used to indicate colour, intensity or labelling on the VDU display in the region of the last pixel address decoded from the immediately preceding Shannon code if any, or overall display conditions if none. The recognition code may be expressed by the five most significant bits of an 8-bit word, the three least significant bits being arbitrary for recognition purposes but indicating the required bit count. This would require comparator 58d to be of 5 bits. Alternatively, the bit count may be indicated by a word or words following the code.

Having read the data, the computer pulses lines 76, 78 and 90 high to reset and start, and the cycle of operations begins once more.

The computer may be an appropriately programmed microprocessor with a programmable peripheral interface. The programming requirements are minor and well understood in the art. It is merely necessary to provide for: data read from bus 54, control panel 14 and lines 60; outputs to bus 80 and lines 72 and 76; internal look-up tables to interpret Shannon code identities and generate graphics information; and interface with VDU 16.

It is possible to provide for code identifica tion entirely within a computer instead of by means of external decoding in accordance with the invention. However, computers are generally ill-suited to dealing with variable bitlength data, and require appreciable programming to do so. This makes them slow, and in the case of microprocessors quite unacceptably slow. Employing a computer with internal code identification but external bit-memory and serial to parallel converter is about 10 times faster than the same computer programmed to carry out the whole operation.

External comparison speeds operation still further. Whereas the above example of the invention contains four comparators 58, it will be apparent that much larger numbers of comparators can be employed to deal with larger numbers of codes.

Referring now to Figure 3, there is shown a comparator device indicated generally by 110 providing an alternative to the comparators 58a to 58d of Figure 2. The comparator device 110 includes a comparator 112 connected via bus branch 56 (see Figure 2) to the shift register 48 (not shown). The comparator 112 has a = (not equal) output 114 to indicate code detection or otherwise as appropriate. A 1024 by 8 bit memory 116 supplies comparison codes to the comparator 112 from data outputs Do to D7. Address inputs Ao to A7 of the memory 116 are connected via a bus 120 to the count outputs QO to Q7 of an eight-bit counter 118. The bus 120 has a branch 122 providing a code identity output.

Address inputs A8 and A9 of the memory 116 are connected to a table select input 124. The counter 118 has reset and clock inputs 126 and 128, the latter being connected to a clock 130. The counter 118 also has a TCU or "not terminal count up" output 132 connected to an AND gate 134, this gate having a second input connected to the comparator = output 114 by a line 136. The output of AND gate 134 provides an enable signal for starting clock 130.

The comparator device 110 operates as follows. The memory 116 holds four tables each holding 255 codes together with a dummy code at address 0. The dummy code is chosen so that it is guaranteed never to match the code contents of shift register 48. One of the four code tables is selected by input of an appropriate two bit code to memory address inputs A8 and Ag. After each fresh bit is cycled into the shift register 48, the counter reset input 126 is pulsed momentarily high by means not shown. The counter 118 then se lects the dumny code at memory address 0 for output to the comparator 112 via data outputs Do to D7. This code necessarily does not match the contents of shift register 48, and comparator = output 114 goes high.

Moreover, the counter TCU output 132 is also high, since the counter 118 has not reached its terminal count. AND gate 134 accordingly receives two logic 1 inputs, and provides a logic 1 output to start clock 130. Successive clock pulses operate the counter 118 to count through successive memory addresses, which presents each stored code in the selected table in turn to the comparator 112. When a match is obtained between the contents of comparator 112 and shift register 48, TCU output 132 goes low changing the state of AND gate 134 and stopping clock 130. The matching code identity is given by the memory address on bus branch 122. If no match is obtained despite the counter 118 having reached its maximum or terminal eight bit count, TCU output goes low, which also switches off clock 130 via AND gate 134.

Code table selection via memory address inputs A8 and A9 provides for the other three stored tables to be compared in turn with the contents of shift register 48.

Use of the Figure 3 comparator device 110 instead of parallel comparators 58 in Figure 2 results in reduced speed, since the memory 116 must cycle through one or more code tables for each new bit entering shift register 48. This would require minor modifications to the Figure 2 clocking arrangements, eg the clock 74 in Figure 2 would operate very much slower than clock 130 to enable the code search to be performed for each new bit.

Other modifications would also be required to provide for reading out uncoded data as in Figure 2.

Such modifications comprise straightforward digital electronic circuitry and will not be described.

Claims (9)

1. A data decoder including: a bit-serial memory to contain coded data; a serial to parallel converter arranged to receive successive data bits from the memory; means for comparing serial to parallel converted data with each of a plurality of stored data codes, such means being operative after output of each data bit from the memory; means for identifying successive data codes after matching with respective coded data; means for interpreting identified data codes; means for controlling operation of the memory, serial to parallel converter and comparing means.

2. A data decoder according to Claim 1 wherein the comparing means includes a plurality of comparators arranged for comparison of converted data with their respective stored codes.

3. A data decoder according to Claim 1 or 2 wherein the controlling means includes a clock arranged to trigger bit output from the memory and operation of the serial to parallel converter and comparing means, operation of the clock being interruptable by means re sponsive to code identification.

4. A data decoder according to Claim 3 including means for resetting the serial to parallel converter in response to code identification and means for restarting the clock thereafter.

5. A data decoder according to any preceding claim including means for reading uncoded data interspersed with coded data.

6. A data decoder according to Claim 5 wherein the means for reading uncoded data includes a circuit responsive to an uncoded data bit count and operative to effect read-out of a corresponding number of uncoded data bits from the serial to parallel converter.

7. A data decoder according to Claim 6 wherein the means for reading encoded data includes a counter and comparator arranged to control operation of the bit-serial memory and effect uncoded data output in response to identification of an appropriate code by the said means therefor.

8. A data decoder according to Claim 1 wherein the means for comparing serial to parallel converted data with stored data codes includes a single comparator, a data code memory and means for supplying successive data codes from the memory to the comparator.

9. A data decoder substantially as herein described with reference to Figures 1 and 2 or Figures 1 and 2 as modified in accordance with Figure 3.