GB2166014A

GB2166014A - Automatic gain control

Info

Publication number: GB2166014A
Application number: GB08426927A
Authority: GB
Inventors: Philip Hall
Original assignee: General Electric Co PLC
Current assignee: General Electric Co PLC
Priority date: 1984-10-24
Filing date: 1984-10-24
Publication date: 1986-04-23
Also published as: GB2166014B; GB8426927D0

Abstract

The gain of an amplifier 2 is controlled by the contents of a counter 6 which is arranged to be clocked by clock signals either up or down depending on whether an average output of the amplifier as determined at 3 is above or below a set level or range of levels (A1-A2 on Fig. 3). Two clocks 9A and 9B which operate at different speeds can be used to enable different clocking up and down speeds. <IMAGE>

Description

SPECIFICATION Automatic gain control In a conventional automatic gain control circuit the gain of an amplifier is varied according to changes in the average amplitude of its output. This maintains the average value constant. In such conventional circuits the speed of adjustment of gain is dictated by fixed characteristics of the circuit in particular by circuits incorporating fixed capacitors and resistors; and by the nature of the input signal.

This invention stemmed from the realisation that it would be a considerable advantage to be able to select the speed of adjustment of gain independently of fixed characteristics of the circuit and independently of the nature of the input signal. Furthermore it may be desirable to control the speed of adjustment of gain during operation so that it is faster at some times than at other times.

This invention provides an automatic gain control circuit in which the gain of an amplifier is controlled by the contents of a counter which is arranged to be clocked by clock signals either up or down depending on whether an output derived from the amplifier is above or below a set level or range of levels.

Thus by employing the invention the speed of adjustment of gain is directed entirely by the frequency of the clock signals which can be chosen and varied at will and which can be made entirely independent of the input signal or can be made to follow any desired function of the input signal. Furthermore the invention enables the fixed capacitors, previously referred to, to be eliminated. This is considered to be a significant advantage since the capacitors are relatively large components and cannot be incorporated as part of an integrated circuit.

Means is preferably included for setting upper and lower limits to a range of levels within which it is desired that the output from the amplifier be maintained. Clocking of the counter is inhibited when the output lies within the defined range. In this way continuous adjustment of the gain up and down is avoided.

In some circumstances it is preferable to arrange for the counter to be clocked in one direction faster than in the other direction and this can easily be achieved for example by including two sources of clock signals operating at different frequencies and by selecting which of these is fed to the counter depending on whether the output from the amplifier is above or below the desired level or range of levels.

One way in which the invention may be performed will now be described by way of example with reference to the accompanying drawings in which: Figure 1 is a block diagram of an automatic gain control circuit constructed in accordance with the invention; Figure 2 represents an input signal fed to the circuit of Fig. 1; and Figure 3 illustrates the output of an averaging device included in the circuit of Fig. 1 without any automatic gain control being applied, and indicates the amplitude values Al A2 between which it is desired to maintain the average output of the amplifier.

Referring to the drawings an audio signal, e.g., derived from an aerial or a microphone, and shown in Fig. 2 is applied to an input 1 of a variable gain amplifier 2.

The amplitude of the output of the amplifier 2 is averaged over a fixed period of time by an averaging system 3. This preferably calculates the RMS amplitude but other types of average would be possible. Where the output of the amplifier is uni-directional the averaging circuit 3 could be formed by a simple low pass filter. It will be appreciated that such a filter does not produce a true mathematical average value. In the context of this specification the term "average" is to be interpreted as referring to a general indication of the level of the signal which is not significantly affected by transient variations of the signal.

The output of the circuit 3 is passed to a circuit 4 which produces a binary value 0 at 4A if the input to circuit 4 is within a range of amplitude values between the lower and upper limits Al and A2 as shown on Fig. 3; and a value 1 if it is outside this range of values A1-A2. If the input to circuit 4 is higher than A2 a value 1 is produced at output 4B and if it is below the value Al a value O is produced at 4B.

The circuit 4 comprises two Schmitt triggers 4C and 4D. Trigger 4C is set for voltages above A2 and reset for voltages below A2.

The output of the trigger 4C is passed to line 4B. The outputs of triggers 4C and 4D are passed to an exlcusive OR gate 4E followed by an inverter 4F.

If the inputs of a circuit 4 is within the range A1-A2 the output 0 on line 4A blocks an AND gate 5 thereby stopping the clocking of a counter 6. If it is outside the range A1-A2 the output 1 at 4A allows the counter to be clocked in a direction up or down depending on the binary value on line 4B. It is clocked down if the RMS signal is above the range and vice versa.

The output of the counter is passed to an indicator 7 which indicates the RMS value at the output of the circuit 3 and to a digital to analogue convertor 8 which controls the gain of the amplifier 2. The gain of the amplifier 2 is thus adjusted so as to maintain the RMS value within the range A1-A2. The ouput of the amplifier 2 will normally be taken to further circuitry (not shown).

The speed of adjustment of the gain of the amplifier 2 is dictated by the speed of the clock 9 and it is an advantage of the system that that speed can be selected relatively easily depending for example on the type of signal to be processed. Furthermore a different speed can be selected when clocking up from clocking down so that the gain for example be lowered faster than it is raised.

With speech signals that is an advantage since it prevents the gain from being unduly increased during gaps between spoken words and yet enables the gain to be decreased rapidly at the start of speech or if there is a sudden increase in amplitude of speech.

To enable different clocking up and clocking down speeds to be used the clock 9 can be replaced by the parts shown in broken lines on Fig. 1 These include two separate clocks 9A and 9B which operate at different speeds and whose outputs are passed to gate 5 depending on whether the signal on line 4B is 1 or O i.e., whether the output of the averaging circu:t 3 is above or below the range of values Al-A2. This is done using an inverter 10, two AND gates 11 and an OR gate 12. It will be apprelciated that the or each clock can be designed if desired so that its frequency can be varied to suit the input signal.

It may be advantageous in some circumstances to include detectors in addition to triggers 4C and 4D for detecting when the signal at the output of circuit 3 is at some other significant value or values. The additional detector or detectors could be used for example to vary the clocking rates when the output of circuit 3 rises above or falls below critical values different from those shown at A7 and A2. All the critical values including Al and A2 can be adjusted by suitably adjusting a reference voltage applied to the triggers 4C and 4D. A number of further modifications to the illustrated system are possible. For example the components 4D, 4E and 4F could be omitted and replaced by a system which inhibits clocking of the counter until the binary value on line 4B has remained constant during a set number of clock signals. Another possibility would be to omit the averaging circuit 3 in which case the frequency of the clock signals would need to be substantially higher than the frequency of the signal to be processed.

The invention could also be applied to a system for controlling the mark to space ratio of an input signal of fixed amplitude. The output of the digitai to analogue converter 8 would for this purpose be applied, not to the amplifier 2, but instead to some device where the mark to space ratio is controlled.

Claims

1. An automatic gain control circuit in which the gain of an amplifier is controlled by the contents of a counter which is arranged to be clocked by clock signals either up or down depending on whether an output derived from the amplifier is above or below a set level or range of levels.

2. A circuit according to claim 1 which includes means for setting upper and lower limits to a range of levels within which it is desired that the output from the amplifier be maintained and in which inhibiting means is included to prevent clocking of the counter when the output lies within that range.

3. A circuit according to claim 1 or 2 including a source of clock signals which is adapted to clock the counter in one direction faster than in the other direction.

4. An automatic gain control according to claim 1 and substantially as described with reference to Fig. 1 and substantially as illustrated therein.