GB2163275A - Ion beam lithography - Google Patents

Abstract

An ion beam lithography technique is provided in which a surface (42 or 66) to be processed is coated with an ion resist layer (41 or 67) on which an above-resist mark layer (40 or 68) is deposited (in Fig. 4, discontinuities in this layer are shown at 32.) The above-resist mark layer (40 or 68) is 15 to 50 nm thick, electrically continuous within each 100 mu m ion beam exposure field (23) and covers at least 75% of the ion resist layer (41 to 67). The ion resist layer (41 or 67) is 200 to 250 nm thick, and 70 kvolt Si<++> ions are employed to expose the ion resist through the above-resist mark layer (40 or 68). These thicknesses of the above-resist mark layer (40 or 68) and the ion resist layer (41 or 67) permit complete penetration by the ion species at the accelerating potential chosen. The electrically continuous above-resist mark layer (40 or 68) avoids surface charging and consequent inaccuracies. <IMAGE>

Description

SPECIFICATION lob beam lithography This invention relates to ion beam lithography for use inter alia in the production of microelectronic circuits and other miniaturised components such as integrated optical devices.

Lithographic techniques have been used for some years for the production of microelectronic devices on semiconductor wafers. Optical lithography, or photolithography, is the most well-known conventional technique. In processing to produce microelectronic devices, a a semiconductor wafer may undergo a series of process steps during which sucessive impurity doping, oxide and conductor patterns are applied to its surface. The patterns vary from step to step, and are defined by a set of device masks each consisting of a patterned metal layer on glass. The semiconductor wafer is covered by a layer of light sensitive material (photoresist), and exposed to light through a respective device mask. Either exposed or unexposed regions of the resist layer are then removed chemically according to whether a positive or a negative photoresist material is employed.Regions of the wafer uncovered by resist removal are available for doping or other processing operations.

The resolution achievable by photolithography is necessarily limited by the optical wavelength employed, and device dimensions much below one micron are difficult to achieve. To improve resolution and increase device density on a semiconductor wafer, electron lithography has been developed. This employs electron beam sensitive materials or electron resists in an analogous manner to photoresists in photolithography.

A limitation in the use of electron beams arises because of long range forward and back scatter of energetic electrons. This causes pattern deformation and loss of linewidth control at geometries below about two microns, and in extreme cases closely spaced features fail to be resolved in the resist. A further problem is that electron beams have voltages of or above 10 kvolts. Long range electrons can produce damage in semiconductor wafers and their sensitive surface oxide layers commonly required in processing. Such damage may affect the performance, life and radiation hardness of the electronic devices produced.

To overcome these difficulties, ion beam lithography is currently undergoing development. Ion beams can be focussed to spots less than 0.1 ,um in diameter, and can be deflected electrostatically to draw desired patterns. Ion resists are available for use in an analogous fashion to photoresists. An energetic ion beam interacts rapidly with an ion resist, which increases the speed at which patterns can be drawn. Moreover, ions of a given species and energy have a closely defined and limited range in a corresponding resist material, and the ions may accordingly be confined to the resist avoiding damage to sensitive device regions.

Implementation of ion lithography has associated difficulties, particularly beam alignment to the required very high accuracy of better than 0.1 #m. As with electron lithography, the ratio of maximum accurate beam deflection to desired accuracy is normally about 1000:1.

Distortion correction and fault-tolerant mark detection techniques increase this ratio. Accordingly, an accuracy to better than 0.1 lim dictates a maximum beam deflection over an excursion of 100 ym (or up to 1 mm with correction techniques). Electron or ion beams may be deflected electronically through at least 2 mm, but without the desired accuracy.

Semiconductor wafers to be processed are in the region of 10 cm~20 cm in diameter, and so it is necessary to abut together many exposure fields 100 ym or more square to achieve coverage. Each exposure field must be aligned with its eight respective neighbours to a relative accuracy of better than 0.1 jtm to ensure continuity of the required pattern features across exposure field boundaries.

Various techniques are known for beam alignment in electron lithography for either or both of device mask making and semiconductor wafer processing. The mask substrate or wafer will normally be arranged on a motordriven support. Accurate calibration of the motor drive combined with dead reckoning is capable of yielding coarse accuracy to f 3 ym as described in J Vac. Sci.Tech 16(6), Nov/Dec 1979. Pasieczrik et al. (Reference 1). The most widely used technique is however to employ a laser interferometer to monitor movement of mirrors attached to the specimen support, as described in Reference 1 also. In direct processing of a wafer with an electron beam, use of the interferometer is combined with detection of on-wafer reference marks, which are required at regular intervals over the entire wafer surface.To obtain the maximum accuracy of this technique, ie rf: 0.1 pm, it is necessary to provide for highly accurate temperature control of the specimen support and associated interferometer equipment to avoid thermal distortion amplified by optical lever effects. This is a severe requirement to satisfy.

Furthermore, the need to provide large numbers of on-wafer markers both consumes available device area and more importantly complicates device design, which must avoid mark locations. A further serious limitation of this technique is that distortion and height variation on the wafer cannot be allowed for directly.

The normal on-wafer alignment marks employed in electron lithography are of heavy metal (eg Ta, W) or consist of etched topographical features such as V-grooves. Metal marks provide secondary electron contrast when the electron beam passes from a semiconductor region to a metal region. Topographical features are detected by using the electron beam as a scanning electron microscope. To maximise the wafer area available for devices, use of on-wafer markers must be reduced as much as possible.

It is known to employ capacitative sensors to detect movement of the specimen support.

The support movement produces measurable changes in capacitance of sensors linked thereto. This technique is however very complex and expensive to implement. Details are given by W C Heerens in Microcircuit Engineering 81 (Reference 2).

In United Kingdom Patent No 1,350,771 (Reference 3), and electron beam alignment technique is described which avoids the use of most of the on-wafer markers required in the above interferometer method. Metal alignment marks are provided on top of a resist layer on a glass plate (for mask making) or a wafer (direct electron beam processing).

This technique is described in more refined form in the Proceedings of Semiconductor International 1982 (Reference 4). The aboveresist markers are laid over the whole surface of the resist to be processed.

They are sufficiently thick (60 to 100 nm) to generate a detectable secondary electron current when irradiated by the electron beam, and so their position may be found accurately.

The marks are however largely transparent to the incident electron beam, which processes the underlying resist through them. Aboveresist marks provide the advantage that the whole resist surface exposed to the incident electron beam is covered with alignment indicators without any penalty in loss of wafer area. Moveover, distortion correction and fault-tolerant detection techniques may be employed. If groups of marks in each 100 izm square exposure field are employed, the detected marks may be matched as a best fit to the known mark pattern, so that failure to detect an individual mark of the group is not serious. This techniquehas however not been generally accepted, as has the laser interferometry approach, despite its achievable accuracy of 50 nm, probably because of its complexity.

It is an object of the present invention to provide a viable ion beam lithography technique.

The present invention provides an ion beam lithography technique including the steps of (1) depositing an ion resist layer on a surface, (2) covering 75 to 99% of the resist layer with a metal layer having spaces therein defining above-resist alignment marks, the metal layer being formed such that it is electrically continuous within each exposure field, (3) employing an ion beam to detect the alignment marks and positioning it accordingly, (4) exposing the resist layer to the ion beam through the metal layer, the ion beam energy being sufficient to allow the ions to penetrate through the metal and resist layers.

Initial attempts to implement ion beam lithography encountered difficulties with inaccurate pattern reproduction and inadequate resist exposure, the latter resulting in failure to remove resist entirely from desired areas. It has been discovered that the pattern reproduction inaccuracy arises from electrical charging of the ion irradiated surface, and that this may be remedied by electrically connecting together all parts of the metal alignment layer within each exposure field about 100 Clm square. This is effective provided that the metal alignment layer covers at least 75% of the resist. Inadequate resist exposure has been discovered to be due to typical thicknesses of resist and alignment mark layers used in electron lithography being too great for adequate penetration by ion beams of acceptable energy.

The method of the invention may be employed in producing a device mask, the surface referred to in step (1) being glass. Alternatively, it may be employed in direct processing of a semiconductor wafer. In the latter case, the surface referred to in step (1) may be a planarising resist layer covering the oxide surface of the wafer. The metal layer of step (2) may be chromium or aluminium.

In a preferred embodiment of the invention, the metal layer is 15 nm to 50 nm thick, the ion resist layer is 200 nm to 250 nm thick and the ion beam comprises SiC + ions accelerated by a voltage in the range 65 to 90 kvolts, preferably 70 kvolts. It has been discovered that an adequate signal to noise ratio for secondary electrons ejected by the ion beam can be obtained from a metal layer 15 to 50 nm thick. Provided the ion resist layer is not greater than 250 nm, the two layers are jointly penetrable by a 70 kvolt Si+ + beam.

This compares with 250 nm of resist and 60 to 100 nm of metal for a 20 kvolt electron beam (see eg Reference 4), where the metal thickness must be larger to achieve adequate secondary electron emission.

The metal alignment mark layer preferably provides a mark pattern having groups of five substantially continuous longitudinal marks and groups of five discontinuous transverse marks spacing apart the longitudinal marks, two of each of the groups of longitudinal and transverse marks defining a 100 ym square exposure field. Electrical continuity is preferably provided by forming the metal layer with conducting bridges spanning the longitudinal continuous marks, the bridges being noncollinear to avoid non-detection of more than one mark during an ion beam scan.

In a further aspect, the invention provides an ion beam lithography technique including the steps of: (1) forming sets of marks on a surface to be processed, the sets of marks being arranged for visual intermeshing and registration with a master reference mark pattern, (2) covering the surface with a planarising resist layer, (3) covering the planarising resist layer with an ion resist layer, (4) depositing a metal above-resist mark layer on the ion resist layer in register with the sets of surface marks, covering 75 to 99% of the ion resist layer and electrically continuous within every exposure field, (5) measuring any linear and angular offsets between the surface marks and above-resist marks by microscopy, and (6) selectively exposing areas of the ion resist to an ion beam having sufficient energy to penetrate through the above-resist mark and ion resist layers, but not the planarising resist layer, the ion beam being deflected in accordance with positional indications from the above-resist marks corrected for any offset from the surface marks.

In this aspect, the invention may employ an ion beam, ion accelerating voltages, aboveresist marks and their thicknesses, patterns and conducting bridges in accordance with embodiments previously indicated. In addition, the surface marks may comprise a combination of topographical and atomic number contrast marks, such as longitudinal and transverse V-grooves together with at least one metal square mark.

In order that the invention might be more fully understood, embodiments thereof will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a schematic plan view of a lithography mask made in accordance with the invention; Figure 2 is an enlarged plan view of a master reference mark mask; Figure 3 is a further enlarged plan view of a portion of the Figure 2 mask; Figure 4 is an enlarged cross-sectional view of a device mask in the process of manufacture; Figure 5 is an enlarged cross-sectional view of the Figure 4 device mask when completed; Figure 6 is a plan view of a silicon semiconductor wafer during production of microelectronic devices; Figure 7 is an enlarged cross-sectional view of a part of the Figure 6 wafer; Figure 8 is an enlarged plan view of one corner of the Figure 6 wafer bearing on-wafer reference marks; and Figure 9 is an enlarged plan view of one corner of the Figure 6 marker showing onwafer reference marks with a superimposed resist layer (not shown) bearing above-resist marks.

In the production of microelectronic devices, a semiconductor wafer undergoes a series of operations each of which modifies its surface selectively. In one operation for example, impurity doping of large numbers of small areas might be carried out by ion implantation to form the sources and drains of MOS transistors. In another operation, a conductor pattern might be laid down to connect transistors to form an integrated circuit. A complete wafer may require fifteen or more patterns to be produced successively on its surface. This is achieved by using a set of device masks, one mask for each pattern and each mask consisting of a configured chromium layer on glass. In the above-resist electron beam technique of References 1 and 2, the device marks are laid down in a layer on top of the resist layer on the wafer by contact photolithography from the device mask.For wafer processing, each layer of device marks must be laid down in accurate register with those employed in earlier processing steps, ie each device mask must be used in accurate register with all other masks of the set. As has been said, semiconductor wafers are processed in exposure fields 100 ym square, and each 100 lim square must be located to an accuracy of less than 0.1 lim with respect to its eight neighbours. The absolute accuracy is less important, but the relative accuracy is critical for continuity of features over exposure field boundaries.

Device mask registration is obtainable provided that each mask is referred to a reference before being used. In the prior art, Reference 3 employs a master reference mark mask from which to make a device reference mark mask, from which in turn to produce a device mask.

The device reference mark mask largely reproduces the master reference marks, except that marks within individual 100 ym squares are relocated where necessary to avoid reproduction in positions where detection would be difficult, ie on the edges of resist-coated surface prominences on the wafer. Two rectangular marks per 100 lim square are employed (defining x and y coordinates) for both the master and device reference mark masks. Reference 4 employs a much larger number of marks, five per 100 ym square in each of the x and y directions, in order that fault-tolerant detection techniques may be employed. The examples of the invention to be described employ a similar marker scheme, which makes the use of a device reference mark mask unnecessary.Device masks may be made or direct ion beam processing of wafers may be carried out directly from the master reference mark mask.

Referring to Figure 1, there is shown a plan view of a lithography mask indicated generally by 10 and comprising a glass plate 11 10 cm square coated with a patterned layer of chromium 12 7.6 cm square, detail of the pattern not being visible on this scale. The mask 10 may be a master reference mark mask or a device mask depending on the nature of the pattern in the chromium layer 12.

Referring now to Figure 2, there is shown the upper left corner of a pattern 20 produced from a master reference mark mask. The pattern 20 is sufficiently enlarged to illustrate the general mark scheme, and comprises groups of five continuous marks such as 21 extending in the x direction together with groups of five discontinuous marks such as 22 extending in the y direction. The pattern repeat distance is 100 jum in either direction, and two adjacent pairs of groups of marks 21 and 22 define a respective 100 jim square such as 23. Four hundred squares 23 form a square or subfield 2 mm on a side and shown in part by chain lines 24. As has been mentioned, 2 mm is a reasonable distance through which an ion beam can be deflected electronically before mechanical movement is necessary.The mask 20 is divided up into 2 mm square subfields of this kind.

Figure 3 shows four adjacent groups of continuous and discontinuous above-resist marks 31 and 32 on an enlarged scale and defining a central 100,um square 33. A corresponding (not to scale) cross-sectional view of the marks 31 and 32 as used for making a device mask is shown in Figure 4, the section being taken along lines 4-4 in Figure 3 through marks 32 only. The marks 31 and 32 are spaces between 2 ym and 3 ,um in width formed in an otherwise continuous layer of aluminium 40 which is 0.35 ym thick. The discontinuous marks 32 are 50 yam in length. The continuous marks or spaces 31 are bridged by mutually staggered aluminium strips 34 2 #m wide so that the aluminium layer 40 is electrically continuous within each square 33.This ensures that charge deposited by an ion beam spreads in all directions. The marks 31 and 32 are formed on a layer of polymethylmethacrylate (PMMA) ion resist 41 by contact photolithography. The resist layer 41 covers a chromium layer 42 on a glass plate 43. The aluminium layer 40 is produced from a master reference mark mask having corresponding marks 3 ym wide. The photolithography and associated processing affects the mark width somewhat. The master reference mark mask is itself produced by computer aided design techniques and lithography. The aluminium layer 40 covers between 78.5% and 85% of the ion resist layer 41, depending on the width of the marks 31 and 32. More generally, coverage between 75% and 99% may be employed.

It has been discovered that the minimum thickness of the aluminium layer 40 for adequate secondary electron emission under typical ion bombardment is 10 nm, ie for 70 kvolts Si+ + ions. However, it has been found that the ion beam tends to sputter away the layer 40 to such a degree that the minimum thickness necessary is 15 nm.

The PMMA layer 41 is 225 nm thick. The minimum thickness would be 200 nm to ensure adequate layer quality and sufficiently low pinhole density. The maximum thickness is set by the criterion that the ion beam must penetrate all the way through the combined layers 40 and 41 to ensure complete exposure of the resist. For 70 kvolt Si+ + ions, the combined thickness of these layers should be less than 300 nm.

The production of a device mask is as follows. An ion beam lithography machine is loaded with the Figure 4 assembly of glass plate 42 bearing the resist layer 41 and above-resist mark layer 40. A 70 kvolt Sif + ion beam is positioned by conventional mechanical specimen movement means to within i 30 ym of the centre of a desired initial 100 jum square such as 33. The ion beam is scanned slowly and sequentially in several different search directions so that each of the four groups of marks 31 and 32 are detected.

The beam is also rapidly scanned perpendicular to the search direction in order to spread charge, to detect along a mark for averaging and to minimise exposure of the underlying resist 41. Detection is carried out by collection of the secondary electron emission from the aluminium layer 40, with which the ion beam interacts strongly. The secondary electron signals from the sequential scans are analysed by a computer, which produces a best fit of the known pattern to the detected pattern. The perpendicular scan averages out the effects of ill-defined mark edges and avoids non-detection of a mark because of passage of the ion beam over a conducting bridge 34. The computer best fit overcomes the problem of missing marks due to lithography deficiencies and surface topography, since many more marks than the minimum required are present.The overall detection system therefore has a high degree of fault tolerance, and is described in more detail in Reference 4.

The computer best fit locates the position of the ion beam in the 100,um square 33 to within 0.1 #m. The required device mask pattern appropriate to the relevant 100 ym square being processed is then drawn in the underlying ion resist layer 41 by the ion beam under computer control, the resist layer being exposed through the aluminium mark layer 40. Beam diameters in the range 0.05 to 1.0 jum are employed together with beam currents from 0.05 to 10 nAmp. This procedure is repeated for successive adjacent 100 ym squares until the 2 mm maximum electronic deflection subfield has been exposed, accurate alignment being carried out at each square.

The mechanical specimen movement means is then operated to bring a further 2 mm subfi eld into the ion beam exposure region, and the procedure is repeated until the whole device mask has been exposed. This procedure is similar to that described in Reference 3. The Figure 4 assembly is then removed from the ion beam lithography machine, and the mark layer 40 and ionexposed regions of the resist layer 41 are dissolved away. This exposes regions of the underlying chromium layer 42 which are in turn dissolved away.

This produces the device mask shown in Figure 5 and indicated generally by 50. In Figure 5, parts equivalent to those indicated in Figure 4 are like-referenced. Chromium dissolution produces spaces 51 in the chromium layer 42. The device mask 50 is used as in conventional photolithography.

In addition to its use in device mask production, the invention may be employed in direct processing of semiconductor wafers.

Referring now to Figure 6, there is shown a circular semiconductor wafer 60 in a form suitable for processing in accordance with the invention. The wafer 60 is 7.6 cm in diameter and bears a device production region 61 6 cm square. The square 61 has on-wafer reference marks (shown much larger than to scale) to be described later at corners 62 and 63 either end of a square diagonal.

A A greatly enlarged cross-sectional view of a small part of the wafer 60 is shown in Figure 7, parts indicated in Figure 6 being likereferenced. The wafer 60 bears surface prominences such as 64 produced by earlier processing or wafer distortion, and is covered by an oxide layer 65 bearing a planarising resist layer 66. An ion resist layer 67 225 nm thick bears a pattern of aluminium above-resist marks 68 0.35 ym thick, and covers the planarising resist layer 66. The above-resist marks 68 are laid down by contact photolithography, and are as illustrated in Figure 3. The planarising resist layer 66 avoids any direct interaction between the ion beam and the wafer 60, and reduces surface undulations.

Referring now to Figure 8, in which parts indicated in Figures 6 and 7 are like-referenced, there is shown an enlarged plan view (not to scale) of the corner 61 of the silicon wafer 60. The wafer 60 has longitudinal, transverse and square on-wafer reference marks 70, 71 and 72 respectively. The marks 70 and 71 each comprise a group of three 40 ym x 2,um rectangular V-section grooves such as 73 spaced on centres 1 0 #m apart and etched in the surface on the wafer 60.

The grooves produce corresponding detectable depressions in subsequent resist layers.

The mark 72 is a 25 ym by 25 ism square of aluminium evaporated on to surface of the wafer 60. The marks 70 to 72 may be produced by optical, electron or ion lithography of the wafer 60. A plan view of the corner 62 is shown in Figure 9, parts indicated in Figures 6 to 8 being like-referenced. Figure 9 illustrates the combination of the onwafer marks 70 to 72 with the above-resist marks 68.

The arrangement described with reference to Figures 6 to 9 is fabricated and employed as follows. The etched on-wafer reference marks 70 to 72 are designed to intermesh visually with the pattern of aboveresist reference marks 68. To produce the pattern of above-resist marks 68, a photoresist layer (not illustrated) is laid down on the ion resist layer 67. A master reference mark mask (see Figure 2) is placed on the photoresist layer and aligned with the marks 70 to 72 by eye using an optical microscope. This produces relative accuracy to i 2,um in position and f 0.3 in angle. The pattern of above-resist marks 68 is then laid down by contact photolithography and the wafer 60 placed in the ion beam lithography apparatus.Electron or ion lithography under computer control may alternatively be employed to lay down the pattern of marks 68. The ion beam is employed to detect the resistsurface depressions indicating the positions of the on-wafer marks 70 and 71. This is achieved by ion microscopy techniques.

Similarly, the positions of the adjacent aboveresist marks 68 are detected relative to the marks 70 and 71, and the angular and linear deviations from symmetrical relative location or intermeshing are calculated by computer means linked to detection circuits. The computer calculates a correction factor which is applied to all subsequent position determinations. If the on-wafer marks 70 to 72 are not visible to the ion beam used as a scanning ion microscope, a scanning electron microscope may be employed to determine the correction factor. A similar procedure is applicable to registering a device mask with on-wafer marks.

The above-resist marks 68 are employed to locate the ion beam position in any 100 lim square as described previously in device mask production, the correction factor being applied by the computer to determine the ion beam position relative to the wafer 60. The pattern required for device layer production on the wafer 60 is then drawn through the aboveresist marks 68 by the ion beam (70 kvolt Si+ + ions) under computer control. Computer aided design techniques are used which are known for electron lithography. This selectively exposes regions of the ion resist layer 67. The wafer 60 is then removed from the ion beam lithography machine, exposed ion resist regions are dissolved away and their immediately underlying planarising resist and oxide layers removed by conventional techniques.This exposes preselected regions of the wafer 60 for impurity doping etc as in conventional lithography. If conductor patterns are required, the oxide layer 65 may be left in place.

The foregoing procedure is repeated until every doping, conduction layer deposition or other processing stage has been applied to the wafer 60 as required to produce semiconductor devices.

Whereas ion resist and above-resist mark layer thicknesses have been described which are appropriate for use with a 70 kvolts Si+ + ion beam, other ion species and accelerating voltages may be employed. Other usable ion beams included B+ Ga+ and Au+ and accelerating voltages are in the range 30-150 kvolts. The usable ranges of thicknesses of the ion resist and above-resist mark layers will vary somewhat with the ion species and accelerating voltages. The 70 kvolts Si+ + ion beam employed in the foregoing examples provides a good compromise between ion beam range and exposure accuracy, the preferred accelerating voltage range being 65 to 90 kvolts.The estimated accuracy of the method of the invention is 0.03 ym. This compares with 3 lim and 0.1 ym for Reference 1 mechanical and optical techniques, and 0.2 ism, 0.1 ym and 0.05 jum for References 2, 3 and 4 respectively, when employed over large areas and a range of operating conditions.

Methods of making device masks and processing semiconductor wafers in accordance with the invention combine the advantages of above-resist marking electron beam lithography set out in References 3 and 4 with the greater precision and avoidance of beam-substrate interaction characteristic of ion beam techniques. This is achieved by overcoming difficulties experienced in producing adequate resist exposure and reliable ion beam positioning accuracy. As has been mentioned, these difficulties have been discovered to be due to the requirement for accurate definition of mark and resist thicknesses and avoidance of exposure field charging.

Whereas the invention has been described in the context of a microelectronic process, those skilled in the art of lithography will appreciate that it is equally applicable to the manufacture of other miniaturised components such as integrated optical devices and superconducting devices.

Claims (7)

1. An ion beam lithography technique including the steps of: (1) depositing an ion resist layer on a surface, (2) covering 75 to 99% of the resist layer with a metal layer having spaces therein defining above-resist alignment marks, the metal layer being formed such that it is electrically continuous within each ion beam exposure field, (3) employing an ion beam to detect the alignment marks and positioning it accordingly, and (4) exposing the ion resist later to the ion beam through the metal layer, the ion beam energy being sufficient to allow the ions to penetrate entirely through the metal and resist layers.

2. An ion beam lithography technique according to Claim 1 wherein the metal layer is 15 to 50 nm thick and the ion resist layer is 200 to 250 nm thick, the combined layer thicknesses being less than 300 nm.

3. An ion beam lithography technique according to Claim 2 wherein the ion beam comprises Si+ + ions accelerated by a potential difference of 65 to 90 kvolts, preferably 70 kvolts.

4. An ion beam lithography technique according to Claim 1, 2 or 3 wherein the alignment marks are substantially continuous in one direction and discontinuous in the transverse direction, the marks being in groups four of which define an ion beam exposure field.

5. An ion beam lithography technique according to Claim 4 wherein the continuous marks are spanned by non-collinear conducting bridges providing electrical continuity of the metal layer within each exposure field.

6. An ion beam lithography technique including the steps of: (1) forming sets of marks on a surface to be processed, the sets of marks being arranged for visual intermeshing and registration with a master reference mark pattern, (2) covering the surface with a planarising resist layer, (3) covering the planarising resist layer with an ion resist layer having a thickness in the range 200 to 250 nm, (4) depositing a metal above-resist mark layer on the ion resist layer in register with the sets of surface marks covering 75 to 99% of the ion resist layer and electrically continuous within every exposure field, (5) measuring any linear and angular offsets between the surface marks and above-resist marks by microscopy, and (6) selectively exposing areas of the ion resist to an ion beam having sufficient energy to penetrate through the above-resist mark and ion resist layers but not the planarising resist layer, the ion beam being deflected in accordance with positional indications from the above-resist marks corrected for any offset from the surface marks.

7. An ion beam lithography technique substantially as herein described with reference to the accompanying drawings.