GB2156153A - Alignment process for semiconductor chips - Google Patents

Alignment process for semiconductor chips Download PDF

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Publication number
GB2156153A
GB2156153A GB08507359A GB8507359A GB2156153A GB 2156153 A GB2156153 A GB 2156153A GB 08507359 A GB08507359 A GB 08507359A GB 8507359 A GB8507359 A GB 8507359A GB 2156153 A GB2156153 A GB 2156153A
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Prior art keywords
solder
placing
substrate
locations
wetting agent
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Granted
Application number
GB08507359A
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GB8507359D0 (en
GB2156153B (en
Inventor
Sameul A Heifets
Richard A Connell
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Pitney Bowes Inc
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Pitney Bowes Inc
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Publication of GB2156153A publication Critical patent/GB2156153A/en
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Publication of GB2156153B publication Critical patent/GB2156153B/en
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
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    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15717—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400 C and less than 950 C
    • H01L2924/15724—Aluminium [Al] as principal constituent

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)

Abstract

In a method of fabricating a linear array of semiconductor chips 18 such as LED's, solder is placed at selected locations on a substrate 10, semiconductor chips 18 are placed upon the solder and then the wider is melted, then cooled. As the solder melts, the semiconductor chips will align themselves due to surface tension and, upon solidifying of the solder, the chips will be secured to the substrate at the selected locations. A wetting agent may be placed at the selected locations, and a solder migration inhibitor at other locations. The selected locations may comprise depressions on the substrate. <IMAGE>

Description

SPECIFICATION Alignment process for semiconductor chips Background of the Invention In the field of electronic non-impact printers, a number of different types of device have been developed. These include laser printers, thermal printers, ink jet printers and the like. One such device that shows great promise is the light emitting diode (LED) printer. In such a device, an array of LED's is positioned to address a photoreceptive surface so that when the latter is charged, exposing the surface to light from the LED's will discharge locations on the photoreceptor so as to produce an image composed of small dots of uncharged areas. The LED's are enabled selectively by electronic drivers in response to a binary coded input to produce an image representative of information being transmitted.In a process known as reverse development, the image on the photoreceptor is developed by a toner material which may then be transferred to a record member, such as paper. The image may then be developed or fused, as is well known in the art.
In the construction of the print head of an LED printer, a chip, made of a semiconductor material, such as gallium arsenide (GaAs), is selectively doped at various locations to produce LED sites after anodes and cathodes are connected to such doped sites. Such chips with LED sites are generally referred to as monoliths. These monoliths may be attached in tandem to a substrate, such as aluminum oxide, so as to produce an LED array. The monoliths have previously been attached to the substrate by an adhesive such as epoxy resin. The monoliths must be laid next to one another in a rather precise fashion so that the cathodes of the respective modules are not so close as to short across one another. It is, therefore, necessary to have a relatively wide gap between epoxy areas when placing the LED monoliths directely on a substrate.
Aligning the monoliths is difficult since they are required to be placed within + 0.0005 in.
and moving them around causes the adhesive to move and create shorts. A still further difficulty is the brittle nature of the gallium arsenide material from which the monliths are made. As is well known, such material has a tendency to readily fracture.
Summary of the Invention It has been found that arrays of semiconductor chips may be made in a convenient and reliable manner by first applying a wetting agent at locations on a substrate in a selected pattern, positioning solder upon the wetting agent at each location, placing doped semiconductor chips on the solder and then melting the solder. When the solder is in the molten state, it has been discovered that the chips will align themselves so long as the area covered by the solder has approximately the same dimensions as the chips and the chips are placed in proximity of their proposed final positions.
Brief Description of the Drawing Figure 1 shows a plan view of a monolith with semiconductor chips located thereon; Figure 2 shows a cross-sectional view of a monolith and a chip before and after the solder has been melted; and Figure 3 shows an alternative embodiment that is similar to Fig. 2.
Detailed Description of the Preferred Embodiments The instant invention will be described as it may be utilized in an LED array, but it will be appreciated that the principles of the invention are applicable in other devices and purposes where semiconductors are attached to a surface.
Referring now to Figs. 1 and 2, an LED array is shown generally at 10 which has a substrate 12 made of a material such as aluminum oxide. A wetting agent 14, such as gold or copper, is located at a plurality of locations to form a pattern. As shown in Fig.
1, the pattern would be a longitudinal series of squares separated by a small distance.
Placed at these locations are appropriate quantities solder 16 which act as a bonding material between the substrate 12 and chips 18 that are positioned upon the solder. The solder 16 may be made of a lead-tin alloy. On an individual basis, the area, as seen in Fig. 1 of the solder 16 normally is approximately the same size as its associated chip 18 but it may be slightly larger than the chip so that a wire 20 may be embedded in the solder, as seen in Fig. 3, thereby allowing the solder to serve as an electrical connection (cathode) between the chip and a selectable power supply source or driver (not shown). The chips 18 will have a number of doped sites 22 with a lead 24 (anode) to each site thereby defining a plurality of light emitting diodes. With such construction, the LED's 18 may be selectively enabled to selectively emit light as required.
In the making of an LED array 10 as shown in Fig. 1, a pattern is formed by applying a wetting agent 14 at selected locations by any conventional method, such as depositing the wetting agent by photolithographic masking technique, to achieve the desired placement accuracy for the location of the LED chips 18.
Both the wetting agent and the semi-conductor materials are easily wet by solder, but the wetting agent may also be applied the underside of the chip 18 if desired. The difference in surface energies between the pattern regions and the nonpattern regions are sufficiently large so that liquidfied solder will not migrate into the unwet region for small dis placements of the chips. This energy difference can be enhanced by coating the nonpattern portion of the substrate, or the location about the wetting agent, with a material that will inhibit the migration of the solder. An example of such a material is polytetra-fluore- thylene which is available from E I Dupont, de Nemours 8 Co. under the trademark TEFLON.
Through use of photo-lithographic marking techniques, a thin film of the wetting agent 14, is deposited. A predetermined amount of the solder 16 in the form of a wafer may then be placed at each location 14 and a chip 18 placed upon the solder. Although the chip 18 as shown in Figs. 2 and 3 is not aligned with the solder 16 by a large amount, it will be appreciated that this is the worst case situation. After the chip 18 has been placed on the solder 16, the temperature of the solder 1 6 is increased to above its solder melting temperature. After the solder 16 melts, the chip 18 will float on the surface of the solder.If the chip 18 is within a few mils of its final desired location and a few degrees from its desired orientation, it will align itself with the desired pattern formed by the solder 16 and wetting agent 14 on the substrate 12 as a result of restoring forces. Because the restoring forces are larger than the gravitational forces, the chip will align itself to the proper position.
After the chips have assumed the proper positions, the solder is cooled and solidifies and the chips are locked in place. The time required for the chip to align itself has been found to be 5 to 10 milliseconds with a comparable dampening time for oscillations.
By using the previously described method in placing chips upon a substrate, one is able to obtain an LED array in a convenient and economical manner. This method not only allows the chips to be accurately aligned and distributed on the substrate, but in addition, it diminishes the risk of breaking chips 18 during fabrication of the LED array 10.
In an alternative embodiment, instead of creating photolithographic marking techniques, a pattern can be formed by creating depressions 26 in the substrate 12. A depression 26 is made in each of the locations of the pattern. The area, as seen in Fig. 1, of each depression being approximately the same size as the chip which is to be placed thereover. Although the depth of the depression 26 is not critical, a convenient depth of such depression may be approximately 0.005". A quantity of solder 16 would be placed within each depression with the width of the solder, as seen in Fig. 2, being slightly greater than the depth of the depression.

Claims (10)

1. A method of fabricating an array of semiconductor chips, the steps comprising: placing a quantity of solder at locations on a a substrate, placing a chip of semiconductor material upon each quantity of solder, increasing the temperature of the solder above its melting point to form a bond with the associated semiconductor chips, and cooling the solder below its melting point.
2. The method of claim 1 including the steps of placing a pattern of wetting agents at locations on the substrate and placing quantities of solder on each wetting agent location.
3. The method of claim 2 including the step of placing a solder migration inhibitor at locations on said substrate about said wetting agent.
4. A method for fabricating an LED array, the steps comprising: creating a pattern of locations on a substrate by depositing a film of a wetting agent at each location, placing a piece of solder upon each of the film locations, placing a semiconductor chip upon the solder, and melting the solder.
5. The method of claim 4 including the steps of coating the non-pattern portion of the substrate with a non-wetting material.
6. A method for fabricating an LED array, the steps comprising: creating a pattern of depression on a substrate, placing a piece of solder within each depression, placing a semiconductor chip upon each of the solder pieces, and melting the solder.
7. A method of fabricating an array of semiconductor chips, the steps comprising: placing a wetting agent in a pattern at locations on a substrate, placing a quantity of solder on each wetting agent location, placing a chip of semiconductor material upon each quantity of solder, increasing the temperature of the solder above its melting point to form a bond with the associated semiconductor chips, and cooling the solder below its melting point.
8. The method of claim 7 including the step of placing a solder migration inhibitor at locations on said substrate about said wetting agent.
9. A method for fabricating an LED array, the steps comprising: creating a pattern of locations on a substrate by depositing a film of a wetting agent at each location, placing a piece of solder upon each of the film locations, placing a semiconductor chip upon the solder, and melting the solder.
10. The method of claim 9 including the steps of coating the non-pattern portion of the substrate with a non-wetting material.
GB08507359A 1984-03-21 1985-03-21 Alignment process for semiconductor chips Expired GB2156153B (en)

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US59175984A 1984-03-21 1984-03-21

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GB2156153A true GB2156153A (en) 1985-10-02
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989008927A1 (en) * 1988-03-15 1989-09-21 Siemens Aktiengesellschaft Assembly process for producing led rows
GB2236217A (en) * 1989-08-23 1991-03-27 Itt Ind Ltd Improvement relating to electrical connectors
FR3125358A1 (en) * 2021-07-16 2023-01-20 Commissariat A L'energie Atomique Et Aux Energies Alternatives Interactive display device and method of manufacturing such a device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1457806A (en) * 1974-03-04 1976-12-08 Mullard Ltd Semiconductor device manufacture
US4074299A (en) * 1974-12-04 1978-02-14 Hitachi, Ltd. Light-emitting diode element and device
GB1553065A (en) * 1978-01-28 1979-09-19 Int Computers Ltd Circuit structures including integrated circuits
GB2062963A (en) * 1979-11-12 1981-05-28 Hitachi Ltd Semiconductor chip mountings
US4394600A (en) * 1981-01-29 1983-07-19 Litton Systems, Inc. Light emitting diode matrix

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1457806A (en) * 1974-03-04 1976-12-08 Mullard Ltd Semiconductor device manufacture
US4074299A (en) * 1974-12-04 1978-02-14 Hitachi, Ltd. Light-emitting diode element and device
GB1553065A (en) * 1978-01-28 1979-09-19 Int Computers Ltd Circuit structures including integrated circuits
GB2062963A (en) * 1979-11-12 1981-05-28 Hitachi Ltd Semiconductor chip mountings
US4394600A (en) * 1981-01-29 1983-07-19 Litton Systems, Inc. Light emitting diode matrix

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989008927A1 (en) * 1988-03-15 1989-09-21 Siemens Aktiengesellschaft Assembly process for producing led rows
US5043296A (en) * 1988-03-15 1991-08-27 Siemens Aktiengesellschaft Method of manufacturing LED rows using a temporary rigid auxiliary carrier
GB2236217A (en) * 1989-08-23 1991-03-27 Itt Ind Ltd Improvement relating to electrical connectors
FR3125358A1 (en) * 2021-07-16 2023-01-20 Commissariat A L'energie Atomique Et Aux Energies Alternatives Interactive display device and method of manufacturing such a device

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GB2156153B (en) 1988-02-24

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