GB2154366A

GB2154366A - Field effect transistors

Info

Publication number: GB2154366A
Application number: GB08420838A
Authority: GB
Inventors: Simon Christopher John Garth; William Charles Nixon
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 1984-01-06
Filing date: 1984-08-16
Publication date: 1985-09-04
Also published as: GB8400336D0; GB8420838D0; GB2154366B

Abstract

A field effect transistor is constructed so that a short section of the channel next to the drain effectively has a higher gate threshold voltage than the rest of the channel. A CMOS circuit using the transistors can be arranged to pass no current between the supply conductors during a change of state. The drain threshold voltage may be a linear function of the gate voltage thus providing a linear voltage amplifier. The high threshold section may be achieved by irradiating a conventional FET whilst a voltage is applied to its drain causing charge storage in the gate insulation, by establishing a voltage gradient near the drain end of the gate metallisation, or by modifying the channel doping near the drain. <IMAGE>

Description

SPECIFICATION Improvements relating to field effect transistors This invention relates to field effect transistors and circuits utilising them.

According to one aspect of the present invention there is provided a field effect transistor having a threshold voltage of conduction to the drain which varies in response to the voltage applied to its gate, whereby the transistor acts predominantly as a voltage amplifier.

According to a second aspect of the present invention there is provided a field effect transistor in which the effect of the gate voltage towards the drain end of the channel is reduced relative to its effect along the remainder of the channel. One embodiment of such a transistor can be realised by irradiating a conventional field effect transistor while a voltage is applied to its drain electrode. As a result of the irradiation the gate treshold voltage is increased and a source-drain threshold voltage is introduced. The effect is thought to be due to positive charges being trapped in the gate insulation oxide. The irradiation results in the generation of electron-hole pairs in the oxide and the electrons of these pairs are drawn away by the drain voltage. The holes, however, have lower mobility than the electrons and remain trapped in the oxide.This appears to be suited to the production of P-channel devices only.

In another embodiment of the invention the transistor is procided with a resisitive section in the gate metallisation close to the drain with a small part of the gate connected to the source. In use a voltage gradient is established along the gate near the drain such that the effect of the gate voltage is reduced towards the drain end of the channel.

In a further embodiment of the invention a region of different conductivity is formed in the channel adjacent the drain so that a higher gate voltage is needed to turn on that part of the channel.

In all embodiments of the invention the conductive path along the channel tends to stop short of the drain region unless a gate voltage in excess of a relatively high value is applied. In order that drainsource current can flow, the drain must be sufficiently reverse-biased for the drain junction depletion region to extend as far as to reach the conductive path. This drain threshold voltage depends on the distance from the conductive path to the drain junction which in turn depends on the gate voltage. The existence of this relationship between the drain threshold voltage and the gate voltage means that the transistor acts as a voltage amplifier.

Transistors of complementary conductivity according to the invention may be used in CMOS logic circuits. In such circuits, the transistors may have relatively low gate threshold voltages but with conventional field effect transistors there is a brief interval during each change of state when both transistors are conducting there is a low impedance current path open between the supply conductors. For use in a CMOS logic circuit transistors according to the invention may be arranged so that the sum of the source-drain voltages required for conduction of both transistors when they have the same gate voltage exceeds the supply voltage, so that there is no time during a change of state when both transistors are conducting.

Elimination of the current spike which normally occurs during the transition from one state to another means that the power consumed is reduced because the only current required is that needed to drive the load which is often largely capacitive. In addition, because of the nature of the conductive state of a transistor according to the invention a CMOS logic circuit constructed using such transistors can be faster than a CMOS logic circuit using conventional field effect transistors.

Because of the voltage amplifier characteristics of transistors according to the invention, when they are used in CMOS circuits the difference between the voltage levels representing the two logic states can be much smaller, e.g. 1 volt, than that conventionally used, about 3 > volts, because the output of a conventional field effect transistor is a current rather than a voltage.

A transistor according to one example of the invention can be manufactured to have a substantially linear voltage gain by suitable adjustment of the impurity profile along the channel.

In order that the invention may be fully understood and readily carried into effect it will now be described with reference to accompanying drawings, of which: Figure 1 is a diagrammatic cross-section of one example of a transistor according to the invention; Figure 2 is a diagram illustrative of what is believed to be the mode of operation of a transistor according to the invention; Figure 3 is the circuit diagram of a CMOS inverter circuit in which transistors according to the invention may be used; Figure 4 is a diagram showing the relationship between the input and output voltages of the circuit shown in Fig. 3; Figure 5 shows a diagram similar to Fig. 4 for the circuit of Fig. 3 using transistors having linear gate voltage to drain voltage characteristics; Figure 6 is a cross-sectional diagram of the second embodiment of a transistor according to the invention;; Figure 7 shows the cross-section of another embodiment of an enhancement mode transistor according to the invention; Figure 8 shows the cross-section of a depletion mode transistor embodiment of the invention; Figures 9 8 10 show the drain current/drain voltage characteristics for different gate voltages of the transistors of Figs. 7 and 8 respectively; and Figures 11 8 12 show the doping profiles of the transistors of Figs. 8 and 7 respectively.

Referring now to Fig. 1, the transistor shown has a substrate 1 of N-type conductivity semiconductor material in which are formed regions 2 and 3 of P-type conductivity respectively acting as the source and drain regions of the transistor. The region 4 between the P-type regions 2 and 3 forms the channel of the transistor and has formed on its surface a very thin film 5 of an insulating material such as, for example, silicon dioxide, on which is formed a conductive gate electrode 6. Source and drain connections 7 and 8 are provided connected to the regions 2 and 3 respectively.

As thus far described, the transistor is a conventional field effect transistor. According to this example of the invention, the transistor after manufacture is irradiated using an electron beam whilst a voltage is applied to the drain connection 8. As the period of time for which irradiation is applied increases so the gate threshold voltage of the transistor increases and a source-drain threshold voltage appears and increases. At the same time, the transconductance of the device falls. Typically, the irradiation is performed using a beam current of 1 nano ampere for a period of 0.5 seconds.

Although the full effect of the irradiation is not completely understood, it is believed that the irradiation causes the generation of electron-hole pairs in the gate oxide film 5. The majority of the electrons escape, but the holes having much lower mobility are thought to become trapped in the film 5 and drift under the influence of the voltage applied to the drain of the device towards that end of the channel. This causes the build-up of charge in the gate oxide in the region 9 close to the drain and when the irradiation is stopped a non-uniform charge (and hence voltage) distribution is built into the gate oxide film.

When a gate voltage is applied to the device, the inversion layer 10 induced in the channel 4 will extend only so far as the start of the region 9 unless the gate voltage is much in excess of the conventional gate threshold voltage of the device. It is thought that the trapped holes in the region 9 cause a reduction in the effect of the gate voltage in the part of the channel 4 next to the drain which results in the channel being pinched off some distance from the drain-substrate junction. Significant conduction along the source-drain path of the device will only occur when the depletion region from the drain, produced when it is reverse-biased with respect to the substrate, touches the inversion layer 10.The dependence of the drain voltage needed to cause conduction along the source-drain path on the gate voltage, because it determines the distance of the inversion layer from the drain junction, defines a voltage amplifier characteristic for the device. The gate voltage also sets up a depletion region and the boundary of the depletion region is represented by the dotted line 11, which indicates that the device shown in Fig. 1 is in a conductive state.

In Fig. 2, the charge built into the gate oxide layer adjacent the drain due to the trapped holes is represented by the dotted line 20, and the solid line 21 represents the effective gate voltage which is influenced as shown by the presence of the trapped holes. The inversion layer 10 extends along the channel towards the drain region 3 as far as the effective gate voltage exceeds the gate threshold voltage VT and the alignment of the termination of the inversion layer 10 with the position where the effective gate voltage falls below VT is indicated by the dotted line 22. In Fig. 2, no depletion layer is shown round the drain region 3 because it is assumed that no drain voltage is being applied to the device.If a drain voltage were to be applied, then the depletion layer resulting from that voltage would have to meet the depletion layer due to the inversion layer 10 for current to flow. As the drain current increases so the inversion layer 10 becomes more tapered as a result of the potential difference established in the channel due to the current.

It will be appreciated that a transistor made by the method described above must have a channel of P-type conductivity because the charge stored in the gate oxide is due to the presence of stored holes and must therefore be positive. There are other methods of manufacturing transistors having the same characteristics as that described above but capable of being manufactured with channels of both P- and N-type conductivity. In one method, the concentration of conductivity determining impurities in the part of the channel adjacent the drain region is increased above its value elsewhere in the channel and such that the conductivity type in that part is opposite that of the drain region regardless of the conductivity type of the remainder of the channel. The result of this is that the effect of the gate voltage is reduced in the part of the channel compared with in the remainder of the channel. Other methods of producing the same result are possible and any way of selectively increasing the gate threshold voltage in the part of the channel nearest the drain may be used.

With transistors of complementary conductivity types in accordance with the invention, it would be possible to produce CMOS logic circuits, and one example of such a circuit, an inverter, is shown in Fig. 3.

In Fig. 3, the drain electrodes of an N-channel transistor 30 and a P-channel transistor 31 are connected together and to an output terminal 32. An input terminal 33 is connected to the gate electrodes of the transistors 30 and 31. The source of the N-channel transitor 30 is connected to a O-volt supply conductor 34. The source of the P-channel transistor 31 is connected to a supply conductor 35 maintained at a positive supply voltage + VDD relative to the conductor 34.

The substrates of the transistors are connected to respective bias supplies and in conventional circuits are connected to the sources of the transistors; as explained later, in order to obtain the advantages described it will probably be necessary to use different bias voltages for transistors according to the invention. When the voltage VIN applied to the terminal 33 is positive, for example at the voltage of + VDD, then the transistor 30 is conducting and the transistor 31 is not conducting, so that the voltage VOUT at the terminal 32 is close to 0 volts. When the voltage VIN is 0 volts, the transistor 31 is conducting and the transistor 30 is not conducting, so that the voltage VOUT is substantially equal to + VDD.It will be appreciated that the advantage of such a circuit is that in both of the two logic states no current is being taken by the circuit itself because one of the transistors is non-conducting so that there is no direct current path from the conductor 35 to the conductor 34. However, using conventional field effect transistors in such a circuit leads to some unwanted power consumption during transitions from one state to the other because for part of the transition period both of the transistors are conducting at the same time with the result that a current of large magnitude, albeit for a short period of time, passes from the conductor 35 to the conductor 34.Whilst it is possible to construct the conventional transistors to have gate threshold voltages just greater than half the supply voltage VOD SO that there is no time during the transition from one state to the other, that both transistors are conducting and the spurious current pulse does not occur, the construction of the transistors to have such high gate threshold voltages has the result that when the transistor is on the "on" state the current through its, which is proportional to the square of the amount by which the gate voltage exceeds (in the turning on direction for the particular transistor) the gate threshold voltage, because the magnitude of the threshold voltage is half the voltage swing applied to the gate.This reduction in the current leads to a corresponding reduction in the operating speed of the circuit which is undesirable. However, using transistors according to the present invention, the effective gate threshold voltage by which is meant the gate voltage at which conduction along the entire length of the channel occurs, can be made just to exceed half the supply voltage without the restriction on the current passed by the transistor when in the "on" state which applies to a conventional fiedl effect transistor. The reason for this is that when the gate voltage VG = VOID' the inversion layer of the transistor extends for the entire length of the channel and is only waisted over a small distance close to the drain so that the conductance of the channel of the transistor is little reduced by the waisting.It follows therefore that the current consumption by the circuit can be kept to the minimum necessary to effect the voltage changes of the capacitances in the circuit because the spurious current pulses cannot occur during the transitions of the circuit, but the speed of operation is not affected in the same way as if the gate threshold voltage had been raised in a conventional field effect transistor as described above.

Because a transistor in accordance with the invention has the characteristics of a voltage amplifier, it is possible to reduce the voltage difference between the logic levels in a CMOS circuit to, say, 1 volt from the conventional value of about 2.5 volts, since the voltages at the outputs of the transistors are substantially independent of the currents drawn from them. The larger voltage difference is required for reliable operation of CMOS circuits using conventional transitors becuase their output voltages depend strongly on the currents drawn which will vary with the differing loads which may be connected to them.The reduction in the voltage difference between logic levels has the advantages that the speed of response of the circuits is increased since the changes in the charges on the stray capacitances of the circuits with a change of logic state are correspondingly reduced, and the power consumption is also reduced for the same reason. The usual 5 volt power supply should be retained to obtain the speed increase;however, it would be possible to reduce the supply voltage to, say, 2.5 volts if desired with some loss of speed.

Fig. 4 illustrates the conductive states of the transistors 30 and 31 as the input voltage VIN increases from 0 or the logic 0 level when the P-channel device 31 is "on", which condition is represented by the left-hand unshaded region A when VOu, = VDD or at any rate it exceeds the logic 1 level as indicated by the line 36. As Vm becomes more positive the output voltage Vout follows the curve 37 falling eventually substantially to 0 volts passing the logic 0 level as represented by the line 38.When the input voltage Vjn has become sufficiently positive and the output voltage Vou has fallen, the N-channel transistor becomes conducting, which state is represented by the unshaded area B, the boundary of conductive condition of this transistor being represented by the curve 39. The shaded area C occurring between the lines 37 and 39 represents the state when both transistors 30 and 31 are not conducting.

The advantages obtained from the use of transistors according to the invention in a CMOS inverter circuit as described above would also be obtained for any other type of CMOS logic circuit.

The transistors forming the CMOS circuit of which Fig. 4 represents the conductive states have non-linear drain voltage to gate voltage characteristics. The switching speed performance of the circuit would be improved by using transistors having a linear drain voltage to gate voltage characteristic when the diagram of Fig. 4 would take the form shown in Fig. 5. This is approximated to by reducing the difference between the logic 1 and logic 0 levels as shown in Fig. 4. Transistors having such a linear characteristic can be manufactured as described below using a number of e.g. two approximately Gaussian impurity profiles added together along the channel and produced by a conventional drive-in diffusions. The actual impurity concentrations required will depend to some extent on the characteristics required for the device.

Another example of a transistor according to the invention capable of being made with channels of both N- and P-type conductivities is shown in Fig. 6. The transistor has a substrate 1, for example of N-type conductivity semiconductor material with source and drain regions 2 and 3 of P-type conductivity formed, for example, by diffusion or ion implantation in the substrate 1. The channel 4 extends between the regions 2 and 3 and has a thin film 5 of insulating material such as, for example, SiO2, covering the channel. The gate metallisation is in two parts on the film 5. The larger part 40 covers most of the channel 4 from the source region 2 almost as far as the drain region 3. The smaller part 41 of the metallisation covers the section of the film 5 at the drain end of the channel 4.The section 42, for example of high resistance polysilicon, connects the part 40 to the part 41 and also lies on the film 5. A gate connection is connected to the part 40, and the part 41 is connected by a conductor 43 to the source and also to the substrate of the transistor. The effect of the polysilicon region 42 is to cause the gate voltage to taper off at the drain end of the channel so that the characteristics of the device are substantially the same as those of the device as described above. Although the transistor just described is of the enhancement mode type, it could alternatively be of the depletion mode type.

Fig. 7 shows in diagrammatic form the cross-section of another embodiment of the invention which is similar to a conventional D-MOS transistor but differs from it by having the additional diffusion 50, shown as being of P-conductivity type, at the drain 51 instead of being at the source 52. In a D-MOS transistor the channel is very highly doped whereas the channel 53 is of P- conductivity type (in an enhancement mode transistor). The device has a conventional gate oxide film 54 and an electrically conductive gate 55. If desired, all of the conductivity types could be reversed to produce a complementary device.

In a D-MOS transistor the channel is formed by the additional diffusion (in that instance at the source) and is therefore particularly short, being determined by the depth of the additional diffusion. This is because the remainder of the material between the source and the drain under the gate is readily depleted by the voltage on the drain and acts as drift region for carriers substantially unaffected by the gate voltage.

In the embodiment of the invention shown in Fig. 7 the channel 53 extends for the full distance between the source 52 and the drain 51. The section of the channel 53 outside the region 50 has a lower gate threshold voltage than the section within the region 50. The device operates in the manner described above with reference to Figs. 1 and 2, except, of course, that the oxide film 54 does not hold trapped charges and the effect is the result of the different doping of the section of the channel nearest the drain.

Fig. 12 shows the doping levels of one example of a device as shown in Fig. 7. For a linear relationship between drain voltage and gate voltage as needed to produce the circuit characteristic shown in Fig. 5, it can be shown that the required doping profile of the region 50 is closely approximated by a combination of two gaussian curves. It follows that the doping profile can be obtained by implanting an appropriate dopant into the space where the drain region is to be formed later, and then heating the wafer to diffuse the dopant laterally a small distance along the channel.

The doping profile required can be expressed as a difference equation which is solvable numerically using a programmable calculator ora a computer. The difference equation is: AV= [ (X2n+ 1 -X2n).P(Xn+ 1)/2the where AV is the gate voltage step; Xn, Xn + 1 are successive values of the distance X along the channel from the drain junction corresponding to each step AV in the gate voltage; e e is the permittivity of silicon; q is the electronic charge; and P(Xn + 1) is the dopant concentration at Xn + 1.

This difference equation is equivalent to Poisson's equation combined with the expression for the gate threshold and the requirement for a linear relationship between the gate voltage and the drain voltage. It can be rearranged to the form

The device shown in Fig. 7 is an enhancement mode transistor; it can also be produced as a depletion mode transistor as shown in Fig. 8, with (in the illustrated example) a channel 60 of N-type conductivity produced by a different implanting operation from that used to produce the source and drain regions 51 and 52. Otherwise the parts of the transistor shown in Fig. 8 which correspond to those of Fig. 7 have the same references as in that figure. The region 50 could be produced by lateral diffusion from the drain region as described above with reference to Figs. 7 and 12.The doping of the transistor shown in Fig. 8 may be as shown in Fig. 11.

There is an advantage which the depletion mode transistor shown in Fig. 8 has over the enhancement mode transistor shown in Fig. 7, and that is that it does not reach drain current saturation as readily as the Fig. 7 transistor. Fig. 9 shows three curves for the Fig. 7 transistor relating drain voltage to drain current for three values of gate voltage, the arrow 65 indicating the direction of increasing gate voltage. Fig. 10 shows the curves for the Fig. 8 transistor, the arrow 66 indicating the direction of increasing gate voltage. The substantially straght curves shown in Fig. 10 indicate that drain current saturation, which causes the curvature of the curves of Fig. 9, does not occur at such low values of drain current of the Fig. 8 transistor as in the Fig. 7 transistor.

The circuit of Fig. 3 has the characteristic shown in Fig. 5 for only one particular supply voltage and in order to operate the circuit with a different supply voltage it is necessary to reverse bias the substrate of the devices by an amount which depends on the supply voltage used. To achieve this one solution would be to provide two biassing circuits, one for the Pchannel devices and one for the N-channel devices. A typical biassing circuit for a set of devices uses a reference device of the same type as the devices of the set with an integrator supplied in parallel with the drain of the reference device and connected to bias its substrate. The gate of the reference device is held just above the gate threshold voltage and the integrator accumulates reverse bias voltage until the drain depletion region in the reference device just touches the inversion layer, when conduction starts in the reference device and holds the reverse bias at the value reached.

Although the invention has been described with reference to specific embodiments it will be appreciated that it is not limited to these embodiments and many modifications may be made without departing from the invention.

Claims

1. A field effect transistor having a threshold voltage of conduction to the drain which varies in response to the voltage applied to its gate, whereby the transistor acts predominantly as a voltage amplifier.

2. A field effect transistor in which in use the effect of the gate voltage towards the drain end of the channel is reduced relative to its effect along the remainder of the channel.

3. A transistor according to claim 2 which is so constructed that in operation the effective gate threshold voltage is higher near the drain end of the channel that it is elsewhere along the channel.

4. A transistor according to claim 2 or 3 having a P-channel and a layer of insulating material between the gate and the channel in which positive charges are trapped in the insulating material adjacent the drain end of the channel.

5. A transistor according to claim 4 formed of silicon and in which the insulating material is an oxide of silicon.

6. A transistor according to claim 2 or 3 in which the gate includes a resistive section close to the drain end of the channel which connects a small part of the gate adjacent the drain to the remainder of the gate, connections being provided to enable a potential difference to be established between the small part of the gate and the remainder of the gate.

7. A transistor according to claim 2 or 3 in which the part of the channel adjacent the drain includes a region having an increased concentration of conductivity determining dopant relative to the concentration in the remainder of the channel, the conductivity type of the region being opposite to the conductivity type of the source and drain regions.

8. A transistor according to claim 7 having source and drain regions of a first conductivity type in which the channel has dopant of the first conductivity type extending from the source region nearly to the drain region and adjacent the drain region includes a region of dopant of opposite conductivity type to the first.

9. A transistor according to claim 7 having source and drain regions of a first conductivity type, in which the channel has dopant of second conductivity type opposite to the first extending from the source to the drain with the region of increased concentration of the second conductivity type dopant adjacent the drain.

10. A transistor according to claim 8 or 9 in which the dopant profile of the part of the channel adjacent the drain is closely approximate to the sum of two gaussian curves.

11. A transistor according to claim 7, 8, 9 or 10 in which the region of increased dopant concentration in the channel is formed by lateral diffusion from the drain region.

12. A transistor according to any of claims 2 to 11 having a threshold of conduction to the drain which varies in response to the voltage applied to its gate.

13. A voltage amplifier circuit including a transistor according to claim 12 and an output circuit which produces a voltage output substantially proportional to the drain threshold voltage.

14. A transistor according to any of claims 7 to 11 wherein the channel and the region of having an increased concentration of conductivity determining dopant are such that in use conduction occurs along the channel as far as the interface between it and the region having an increased dopant concentration, and a depletion zone is set up in that region from the junction between that region and the grain region, the drain threshold voltage being sufficient for the depletion region to reach the conducting part of the channel as determined by the gate voltage and thereby permit current to flow from the source to the drain of the transistor.

15. A field effect transistor substantially as described herein with reference to Figs. 1 and 2, Fig 6 or Figs. 7 and 8 of the accompanying drawings.

16. A transistor according to any preceding claim in which the source-drain voltage required for conduction is a linear function of the gate voltage.

17. A complementary (CMOS) circuit using transistors according to any of claims 6 to 13 or substantially as described herein with reference to Fig. 6 or Figs. 7 and 8 of the accompanying drawings, with or without the feature of claim 14, in which the sum of the source-drain voltages required for conduction of the transistors connected in series when they have the same gate voltage exceeds the supply voltage, so that at no time are both transistors switched on.

18. A circuit according to claim 15 including two biassing circuits respectively connected to reverse bias the substrates of the P-channel transistors and the substrates of the N-channel transistors, wherein each biassing circuit includes as a reference device a transistor of the type to which it is connected to bias with its gate held just above the gate threshold voltage and an integrator circuit supplied with current in parallel with the drain of the reference device so that the integrator builds up a reverse bias voltage for the transistors until the reference device just starts to conduct.

19. A method of manufacturing a field effect transistor including the step of irradiating a conventional field effect transistor whilst applying a voltage to the drain of the transistor.

20. A method according to claim 19 wherein the irradiation is performed by an electron beam using a beam current of about 1 nanoampere for about 0.5 seconds.

21. A method of manufacturing a field effect transistor including the steps of forming the gate metallisation with a small part adjacent the drain separate from the remainder of the gate metallisation on a gate insulation layer, joining the small part of the gate metallisation to the remainder by a section of high resistance material also on the gate insulation layer, and producing separate connections to the small part and the remainder of the gate metallisation.

22. A method of manufacturing a field effect transistor wherein, before the source and drain regions are formed an implant of dopant of opposite conductivity type is made where the drain region is to be and the implanted dopant is then diffused laterally to influence a small part of the channel at the drain end.

23. A method of manufacturing a field effect transistor substantially as described herein with reference to Figs. 1 and 2, Fig. 6 or Figs. 7 and 8 of the accompanying drawings.

24. A transistor made by a method according to any of claims 19 to 22.

25. A field effect transistor having a variable effective gate threshold voltage in which the effective gate threshold voltage depends on the drain voltage.

26. A field effect transistor according to claim 25 in which the distance which the drain depletion region extends along the channel determines the effective gate threshold voltage.

27. A field effect transistor according to claim 25 or 26, in which the effective gate threshold voltage is substantially linearly dependent on the drain voltage.