GB2154102A - Digital transmission systems - Google Patents

Abstract

To facilitate the transfer of channel associated signalling (2 kbit/s) across an interface with 64 kbit/s TDM Channel data, a modification of the CCITT codirectional interface coding rules is used in which the octet timing signal (normally provided by level violation on every eighth bit) may or may not be present. A frame is constructed whereby the level violations of the octet timing signal are coded into a sequence of twelve known states (a frame word), followed by four further states containing the signalling information. If "0" is to be transmitted, the octet timing signal violation will not be present: if "1" is to be transmitted, the octet timing signal violation will be present. Thus the additional 2 kbit/s of signalling may be transmitted across the interface without increasing the basic channel rate and without providing a separate wired interface for the 'Time Slot 16' signalling information.

Description

SPECIFICATION Digital Transmission Systems This invention relates to digital transmission systems, and in particular to time division digital multiplex equipment and to interface equipment for use with this multiplex equipment in such systems.

One such time division digital multiplex equipment is a primary pulse code modulation (PCM) multiplex equipment for voice frequencies.

The International Telegraph and Telephone Consultative Committee (CCITT) has made recommendations for the information stream formats of two such equipments operating at a 2048 and a 1544 kbit/s overall (gross) digit-rate respectively. These formats have been published most recently in the CCITT Yellow Book, Vol. lil, Fascicle 111.3, 1981, Recommendations G.732 and G.733.

The 2048 kbit/s stream format, Recommendation G.732, includes the following characteristics. There are eight bits per channel time slot (TS); there are thirty-two channel time slots per frame, numbered 0 to 31; and the frame repetition rate is 8 kHz. Channel time slots TS1 toTS15andTS17toTS31 are assigned to 30 telephone channels numbered from 1 to 30. Thus for audio (speech) telephone transmission, each audio channel (4 kHz) is sampled at the frame rate of 8 kHz with each sample being represented in pulse code modulated form by the eight bits in its respective time slot. This corresponds to an information rate for encoded audio transmission of 64 kbit/s per channel. Channel time slotTS0 contains a frame alignment signal.

Channel time slotTS16 is assigned to signalling information for the 30 telephone channels, that is information passed between telephone exchanges concerned with the setting up and breaking down of calls on the telephone channels when they are used for audio (speech) transmission. In the arrangement known as channel associated signalling the capacity ofTS16 is sub-multiplexed over a multiframe period of 16 frames numbered 0 to 15, the multiframe repetition rate therefore being 500 Hz. TS16 in frame 0 contains a multiframe alignment signal. In each of frames 1 to 15 the 8 bits of TS16 are shared by 2 channels such that each channel is allocated a 4 bit word for signalling information per multiframe.This corresponds to an information rate of 2 kbitls per channel for signalling transmission.

Instead of being used for speech transmission, one or more of the 30 telephone channels described above may be used for data transmission at an information rate of 64 kbitls per channel. For the purpose of gaining access to a 64 kbit's information channel at a short distance from a multiplex equipment, that is to say at not more than approximately 100m and 3db loss, the CCITT has provided specifications for several types of 64 kbit/s interfaces, published most recently in the CCITT Yellow Book, Vol. III, Fascicle 111.3,1981, Recommendation G. 703.Included in the basic functional requirements for all these interfaces is that both in transmit and receive directions, three signals are carried across the interface, that is the 64 kbitls information signal, a 64 kHz timing signal and an 8 kHz timing signal. The 8 kHz timing signal divides the 64 kbit's into 8 bit blocks each of which is the 8 bits carried in a channel time slot corresponding to that channel in the 2048 kbit's stream. One of these interfaces is called a codirectional interface and is defined as an interface across which the information and its associated timing signals are transmitted in the same direction.

Code conversion rules are recommended by the CCITT for the codirectional interface which provide a three level signal incorporating the information and timing signals just mentioned. In particular, the 8 kHz timing signal is provided by violations of a polarity of alternation rule for the information signal.

These 64 kbit's interfaces, including the codirectional interface, as recommended by the CCITT have no provision for conveying the abovementioned 2 kbit's channel associated signalling information. Thus they are for use with data traffic being conveyed over dedicated routes where there is no channel associated signalling information.

When access to an encoded audio 64 kibitzs information channel and its 2 kbit's channel associated signalling information is required it has been customary to provide a special interface for the multiplex equipment which is capable of conveying both the audio information and the signalling information in a decoded form corresponding to the unencoded form in which they were present prior to entering the digital transmission network.The CCITT recommended 64 kibitzs interfaces could be used for gaining access to an encoded audio 64 kbit's information channel but it would be necessary in this case to provide, in addition to the CCITT recommended 64 kbit/s interface equipment and its associated wired path, separate interface equipment and a separately wired path to gain access to the 2 kbitls channel associated signalling information.

The basic idea of this invention is to provide a codirectionai interface which is modified with respect to that recommended by the CCITT in such a way that it can convey not only the 64 kbitls information and timing signals for a particular channel but also the 2 kbit/s signalling information associated with that channel within the same overall bit rate and without the need for a separately wired path. This is achieved by modifying the code conversion rules recommended by the CCITT so as to degrade the 8 kHz timing signal recommended by the CCITT according to a format which enables sufficient 8 kHz timing information to be conveyed while enabling the 2 kbitls signalling information to be incorporated within that degraded 8 kHz timing signal. The modification controls the abovementioned polarity violations.

According to the invention there is provided a digital transmission interface unit having a receive section adapted to convert incoming bursts of data at 2048 kbitls rate in a relevant outgoing channel time slot from a CCITT G732 multiplex equipment to an outgoing 64 kbit/s CCITT G703 codirectional interface signal, the 64 kbit/s interface signal being modified to incorporate 2 kbitls time slot 16 (T.S.1 6) data from said multiplex equipment associated with said outgoing channel, the receive section including means for receiving said T.S.16 data and for providing a violation control signal in which each 4 bit word of said T.S.16 data is incorporated into a 2ms frame structure, the modification of the 64 kbit"s interface signal consisting in the presence or absence, under control of the violation control signal, of 8 kHz timing polarity violations which would be fully present in an unmodified said 64 kbitls interface signal, the interface unit also having a transmit section adapted to convert an incoming said modified 64 kbitls interface signal to outgoing bursts of data at 2048 kbit's rate in a relevant incoming channel time slot said multiplex equipment, the transmit section including means for detecting the presence or absence of said 8 kHz timing polarity violations in said incoming modified 64 kbitls interface signal and incorporating the detected present or absent violations in a violation input signal having a 2 ms frame structure incorporating each 4 bit word of T.S.16 data associated with said incoming channel and including means for extracting each said 4 bit word of T.S.16 data from the violation input signal and transmitting it to said multiplex equipment.

Preferably the 2 ms frame structure has the format 11111 1110000XXXXwhere "1" corresponds to the presence of a said polarity violation, "0" corresponds to the absence of a said polarity violation and "X" corresponds to the presence or absence of a said polarity violation in accordance with the incorporated T.S.16 data.

The invention is particularly suitable for use at a cross-connect site, that is a central exchange site where multiplex systems radiate to remote customer or other exchange sites. Speech/signalling or data information is connected from one multiplex equipment to another within this central site either using switching equipment or, in the case of permanent dedicated connections, via hard wire interfaces. A large variety of complex interface equipment types may be provided with the multiplex equipments at the remote locations.

Hitherto a corresponding large variety of complex interface types has been used for the dedicated hard wire interfaces at the central site. In particular, each hard wire interface at the central site which conveys a speech channel and its associated signalling has customarily been particularly adapted to convey both the audio and signalling information in a decoded form corresponding to the unencoded form in which it enters the respective interface equipment at a remote location.The interface according to this invention may be used to convey a speech channel and its associated signalling from one multiplex equipment to another within a central site retaining their encoded 64 kbitls and 2 kbit's form and therefore provides a single common interface type which may be used to convey any speech channel and its associated signalling at the central site without reference to the particular complex interface equipment type associated with that channel and signalling at a remote location.

Where a dedicated hard wire interface is also required at the central site to convey a 64 kbit's data information channel with no associated signalling, the CCITT recommended codirectional interface may be used. However, use of a common interface type at the central site may be retained by using the interface according to this invention for this requirement even though the signalling information content conveyed will be zero. A 64 kbit's data information channel conveyed by the 30 channel time division multiplex system in the CCITT recommended 2048 kbitls stream format could have associated data supervisory and control information conveyed at 2 kbit"s in time slot T.S.16.In this case, the interface according to the invention may be also used as a dedicated hard wire interface at the central site to convey this supervisory and control information as well as the data information.

According to the invention there is therefore also provided a digital transmission system including an exchange site having a plurality of CCITT G732 multiplex equipments provided for radiation to remote customer or other exchange sites, in which a plurality of dedicated interfaces are provided within said exchange, each said dedicated interface being between a selected two of said multiplex equipments, each said dedicated interface comprising two interface units as in the penultimate paragraph, one of said two interface units being at each of the two multiplex equipments, and a dedicated wired path to convey said modified 64 kbit"s interface signal in both directions between the two interface units.

The invention will now be described in more detail with reference to the accompanying drawings in which: Figure 1 illustrates the code conversion rules for a 64 kbit's codirectional interface according to the above-mentioned CCITT Recommendation G.703, Figure 2 illustrates a modification of these code conversion rules according to the invention, Figure 3 illustrates the radial connection of a number of remote customer or exchange sites to a central exchange site, Figure 4 illustrates the arrangement of Figure 3 in more detail by showing the multiplex equipments at the various sites and in particular the arrangement of a number of hard wire interfaces according to the invention providing permanent connections between multiplex equipments within the central exchange, and Figure 5 illustrates an implementation of an interface unit according to the invention.

Referring now to Figure 1, line (a) shows the bit numbers 1 to 8 of each eight bit word in a continuous stream 64 kbit's information channel.

Line (b) shows the last two binary digits 10 of one word, a following word having the binary digit sequence 01001110, and the first binary digit 1 of the next following word. Line (c) shows a waveform incorporating the information of line (b) and in which Steps 1 to 3 of the CCITT code conversion rules have been operated, that is to say in Step 1 a 64 kbit's bit period of 15.6 us is divided into four unit intervals, in Step 2 information binary digits 1 are coded as a block of four bits 1100, and in Step 3 information binary digits 0 are coded as a block of four bits 1010. Line (d) shows the information waveform according to Step 4 of the code conversion according to which the binary signal is converted into a three-level signal by alternating the polarity of consecutive blocks.Line (e) shows the final form of the information stream waveform according to Step 5 of the conversion in which the alternation in polarity of the blocks is violated, V, every eight block. The violation block marks the last bit in an octet, that is to say the bit number 8 in an information word. Line (f) shows the octet timing signal having a period of 125 us (8 kHzfrequency) which is incorporated in the information stream waveform (e).

Referring now to Figure 2, line (a) shows the bit numbers 1 to 16 of a 2000 us 16 bit frame in which each bit corresponds to the 125 us period of the 8 kHz octet timing signal shown in Figure 1. Line (b) shows the format of this 16 bit frame in which bit numbers 1 to 8 are marked by the presence of a violation, V, and are in accordance with the CCITT code conversion rules shown in Figure 1; bit numbers 9 to 12 are marked by the absence of a violation, and are not in accordance with these CCITT rules; and bit numbers 13 to 16 are unspecified, X, as to the presence or absence of such a violation. The violations present in bits 1 to 8 are sufficient to maintain the 8 kHztiming information of the degraded octet timing signal.

Furthermore the format of bits 1 to 12 contains sufficient information to be able to uniquely identify the position Pat the beginning of bit 13. The 4 bit word of the 2 kbit/s signalling information stream (which occupies half the period of a time slot 16, TS16, in the 2000 lls multiframe period of an overall 2048 kbit/s stream in association with the particular 64 kbit/s information channel of that overall stream) is contained in the final 500 us corresponding to bit numbers 13 to 16 of the 16 bit frame shown in lines (a) and (b) of Figure 2. The bits of this 4 bit signalling word are conventionally designated A, B, C and D as shown in line (b).In this case, a binary digit 1 of the 4 bit signalling word is represented by the presence of a violation, V, marking one of the bit numbers 13 to 16 of line (a) and a binary digit 0 of the 4 bit signalling word is represented by the absence of a violation, marking qne of the bit numbers 13 to 16.

Line (c) shows an example of a 16 bit frame of the 8 kHz timing signal waveform degraded so as to incorporate a 4 bit word of the 2 kbit's signalling information in the manner just described with reference to lines (a) and (b). The presence and absence of violations in this example is shown in line (d), and lines (e) and (f) show that the designated bits A, B, C and D of the 4 bit word in this example are binary digits 1,0, 1 and 0 respectively.

Line (g) shows part of the fully coded 64 kbit/s information stream incorporating the 8 kHz timing signal and the 2 kbit's signalling information. Line (h) shows the corresponding bit numbers 7,8, 1 and 2 in the 64 kbitls information stream, and line (i) shows the binary digit information of these bit numbers as 1,0,0 and 1 in three successive examples. The violation, V, which occurs in bit number 13 of the frame of line (a) marks position P in the frame of line (a), conveys 8 kHz timing information and represents a binary digit 1 in the bit A ofthe 2 kibitzs signalling information word. The succeeding violation absence, and violation presence, V, representing bits B and C of lines (c) to (f) are also shown in line (g).With this particular 4 bit signalling information word, the 8 kHz timing information is absent at the beginning of bits 14 and 16 of the 16 bit frame shown in line (a). The detailed modification in accordance with this invention of the fully coded 64 kbit's information stream compared with the above described CCITT Recommendation G.703 is apparent from a comparison of line (g) of Figure 2 with line (e) of Figure 1.

Figure 3 illustrates the radial connection of a number of remote customer or exchange sites RS1 to RS6 to a central exchange cross-connect site CS.

Figure 4 illustrates multiplex equipments in the sites RS1 to RS6 and CS and their interconnection. The remote sites RS1 to RS6 each have a CCITT recommended 2048 kbit/s 30 channel primary PCM multiplex equipment, RM1 to RM6 respectively, and the central site CS has a corresponding number of CCITT recommended 2048 kbitls 30 channel primary PCM multiplex equipments CM1 to CM6 each connected by a 2048 kbitls transmission path to a respective one of the multiplex equipments RM1 to RM6. A variety of complex interface equipments may be provided to connect data information, or speech and associated signalling information, with a respective one of the 30 channels of each of the multiplex equipments RM1 to RM6.For example, speech and associated signalling information in conventional analogue form may enter and leave the digital transmission system shown in Figure 4 via one of these interface equipments. A number of such interface equipments Al to A20 are shown which are for use with dedicated routes between the remote sites RS1 to RS6. These dedicated routes are provided by permanent hard wire interfaces which convey information between the multiplex equipments CM 1 to CM6 at the central site CS.

These hard wire interfaces are shown as 116, 115, 114, 112, 126, 125, 124, 136, 135 and 134, and they each consist of two interface units C and an associated wired path. As one example, a dedicated route between the interface equipment Al connected to channel 1 at the remote multiplex equipment RM1 and the interface equipment A20 connected to channel 1 at the remote multiplex equipment RM6 is provided by interface 116 which consists of an interface unit C connected to channel 1 at the central multiplex equipment CM1 and permanently hard wire connected to another interface unit C which is connected to channel 1 at the central multiplex equipment CM6. As another example, a dedicated route between the interface equipment A7 connected to channel 22 at the remote multiplex equipment RM2 and the interface equipment Al 5 connected to channel 24 at the remote multiplex equipment RM5 is provided by interface 125 which consists of an interface unit C connected to channel 22 at the central multiplex equipment CM2 and permanently hard wire connected to another interface unit C which is connected to channel 24 at the central multiplex equipment CM5.All the interfaces 116 to 134 are the same and consist of a pair of interface units C, each of a single common type, and an associated wired path, which are adapted to convey, in both directions, a 64 kbit's information channel and associated 2 kbit's signalling information according to the code conversion rules described above with reference to Figures 1 and 2.

Referring now to Figure 5, there is illustrated an implementation of one of the interface units C shown in Figure 4. The interface unit is in the form of a card comprising three identical transmit and receive circuits so that it provides access to three of the channels carried by an associated single shelf multiplex equipment which may be any one of the multiplex equipments CM1 to CM6 shown in Figure 4. Figure 5 shows that part of the card applicable to one of the three channels, channel A. Each one of the three circuits is capable, in the receive direction, of converting bursts of data at 2048 kbitls rate appearing in a relevant outgoing channel time slot from the multiplex equipment into an outgoing 64 kbit"s codirectional data interface signal.In the transmit direction each circuit is capable of converting incoming 64 kbit"s codirectional data into outgoing bursts of data at 2048 kbit's rate in a relevant incoming channel time slot suitable for multiplexing by a common card ofthe multiplex equipment into 2048 kbit"s output.

Provision is made on the interface unit card to interface with Time Slot 16 Highways, such that signalling information from T.S.16 for each channel may be passed over the 64 kbit/s interface. The T.S.16 information is transferred across the interface by utilising the 8 kHz timing polarity violations in the 64 kbitls data stream interface signal in the manner described above with reference to Figures 1 and 2. The circuits for the T.S.16 interfaces for all three channels are contained in an Uncommitted Gate Array (U.G.A.).

The receive section 10 of the U.G.A. for channel A reads the information present on the four T.S.16 signalling receive data highways forthat channel from the multiplex equipment into input latches at a selected time instant. The 4 bit data word now present on the outputs of the input latches is converted into a serial format which is incorporated into a 2ms frame structure generated by gating the appropriate outputs from a divide by sixteen counter. The frame is sixteen bits long and has the following structure 111111110000ABCD, where A, B, C and D are the conditions existing on the T.S.16 receive highways in the selected time instant. This is the frame structure shown in Figure 2 lines (a) and (b). The serial output from the circuit which contains this frame is provided as a violation control signal VC.

An Uncommitted Logic Array (U.L.A.) circuit is provided for each of the three channels to convert between 2048 kbitls time slot data and 64 kbit"s codirectional data. The receive section 11 of the U.L.A. for channel A includes an 8-bit register which reads in a burst of 2048 kbit's rate binary data appearing in the relevant time slot from the multiplex equipment and reads it out at 64 kbit(s rate. The 64 kbit"s data is then fed into a binary to co-directional converter where data is read out in two binary streams D+ and D-.This converter is responsive to a violation generator which is used to produce 8 kHz timing polarity violations in the streams D+ and D- in the seventh and eighth bits of data, and the violation generator has an inhibit input to which is applied the violation control signal VC from the U.G.A. receive circuit 10. The two data streams D+ and D- are provided to a peripheral driver circuit 12 where they are buffered and from which a balanced transformer provides a 64 kbit's interface signal to a wired path. Thus the presence or absence, under control of the violation control signal VC, of 8 kHz timing polarity violations which would be fully present in an umodified CCITT G732 64 kbitls codirectional interface signal incorporates the T.S.16 data associated with channel A in the outgoing interface signal from the circuit 12.

In the transmit section for channel A of the interface unit, the incoming 64 kbit's co-directional interface signal is applied to a termination circuit 13 including a balanced transformer which provides two streams of codirectional data (D+ and D-) which are 180 degrees out of phase to the transmit section 14 of the U.L.A. circuit for channel A. This transmit section 14 includes a converter which converts 64 kbit/s codirectional data provided by the streams D+ and D- into binary form to provide a 64 kbit/s binary data stream. The first three bits of data are read into a 3-bit serial/parallel register by a first generated clock signal, clock 1. Bits 4--8 of data are read into a 5-bit serial/parallel register by a second generated clock signal, clock 2.This clock 2 also transfers bits 1-3 from the serial/parallel register to a 3-bit parallel/parallel register. The eight bits of data in the registers are now ready for parallel transfer into an 8-bit read out register. The eight bits of data are static in the two intermediate registers until the next burst of clock 2 occurs. Timing signals designated for channel A give a time slot pulse during which the data in the 8-bit read-out register is read out by a burst of 2048 kHz clock, and the burst of 8-bit data at 2048 kbit/s rate is provided on the 2 Mbit"s highway output of the U.L.A. section 14 to the multiplex equipment.

A violation detector is included in the U.L.A.

transmit section 14 for detecting the presence or absence of the 8 kHz timing polarity violations in the D+ and D- streams obtained from the incoming 64 kbit/s codirectional interface signal and these detected present or absent violations are incorporated in a violation input signal Vl having a 2 ms frame structure incorporating each 4 bit word of T.S.16 data associated with the incoming channel A.

This violation input signal VI, which is provided to the transmit section 15 of the U.G.A. for channel A, consists of a data stream which includes the violation status information. The U.G.A. extracts the violation status from this data stream. The presence or absence of violations in each frame is in the format 111111110000XXXX as described above with respect to the receive section. In the section 15 of the U.G.A. a 64 kHz clock, divided by eight, clocks the presence or absence of violations in the violation input signal Vl into a shift register. The outputs from this shift register are used to identify the frame and consequently extract the 4 bits of T.S.1 6 data which are fed into four data latches. The conditions on the inputs of these data latches are transferred at a selected time instant to their outputs and thus on to the four T.S.16 signalling transmit data highways for channel A to the multiplex equipment.

Claims (5)

1. A digital transmission interface unit having a receive section adapted to convert incoming bursts of data at 2048 kbit/s rate in a relevant outgoing channel time slot from a CCITT G732 multiplex equipment to an outgoing 64 kbit/s CCITT G703 codirectional interface signal, the 64 kbit/s interface signal being modified to incorporate 2 kbit/s time slot 16 (T.S.16) data from said multiplex equipment associated with said outgoing channel, the receive section including means for receiving said T.S.16 data and for providing a violation control signal in which each 4 bit word of said T.S.16 data is incorporated into a 2 ms frame structure, the modification of the 64 kbit/s interface signal consisting in the presence or absence, under control of the violation control signal, of 8 kHz timing polarity violations which would be fully present in an unmodified said 64 kbit/s interface signal, the interface unit also having a transmit section adapted to convert an incoming said modified 64 kbit/s interface signal to outgoing bursts of data at 2048 kbit/s rate in a relevant incoming channel time slot to said multiplex equipment, the transmit section including means for detecting the presence or absence of said 8 kHz timing polarity violations in said incoming modified 64 kbit/s interface signal and incorporating the detected present or absent violations in a violation input signal having a 2 ms frame structure incorporating each 4 bit word of T.S.16 data associated with said incoming channel and including means for extracting each said 4 bit word of T.S.16 data from the violation input signal and transmitting itto said multiplex equipment.

2. A digital transmission interface unit as claimed in Claim 1, in which the 2 ms frame structure has the format 111111110000XXXX where "1" corresponds to the presence of a said polarity violation, "0" corresponds to the absence of a said polarity violation and "X" corresponds to the presence or absence of a said polarity violation in accordance with the incorporated T.S.16 data.

3. A digital transmission system including an exchange site having a plurality of CCITT G732 multiplex equipments provided for radiation to remote customer or other exchange sites, in which a plurality of dedicated interfaces are provided within said exchange, each said dedicated interface being between a selected two of said multiplex equipments, each said dedicated interface comprising two interface units as claimed in Claim 1 or Claim 2, one of said two interface units being at each of the two multiplex equipments, and a dedicated wired path to convey said modified 64 kbit/s interface signal in both directions between the two interface units.

4. A digital transmission interface unit substantially as herein described with reference to the accompanying drawings.

5. A digital transmission system including an exchange having a plurality of CCITT G732 multiplex equipments provided for radiation to remote customer or other exchange sites, and a plurality of dedicated interfaces provided within said exchange, substantially as herein described with reference to the accompanying drawings.