GB2153587A - Improvements relating to semiconductor injection logic devices - Google Patents
Improvements relating to semiconductor injection logic devices Download PDFInfo
- Publication number
- GB2153587A GB2153587A GB08402477A GB8402477A GB2153587A GB 2153587 A GB2153587 A GB 2153587A GB 08402477 A GB08402477 A GB 08402477A GB 8402477 A GB8402477 A GB 8402477A GB 2153587 A GB2153587 A GB 2153587A
- Authority
- GB
- United Kingdom
- Prior art keywords
- transistor
- output
- injection
- outputs
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000002347 injection Methods 0.000 title claims abstract description 38
- 239000007924 injection Substances 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000000034 method Methods 0.000 claims description 7
- 238000001465 metallisation Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 2
- 230000035945 sensitivity Effects 0.000 description 6
- 238000010276 construction Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015654 memory Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229920000136 polysorbate Polymers 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A multi-output injection logic device comprising a plurality of electrically-interconnected switching lands (8, 9, 10) each of which embodies a single collector/output (11, 12, 13) of a multi-collector transistor which has operatively associated with it an individual injector (18, 19, 20) which is electrically connected to the other injector(s) of the device so that in operation of the device the collectors/outputs of the multi-collector transistor will be supplied with injection current over separate paths through the respective switching lands, the collectors/outputs being equidistant from their respective injectors in order to avoid differential delay. <IMAGE>
Description
SPECIFICATION
Improvements relating to semiconductor injection logic devices
This invention relates to semiconductor injection logic devices and relates more especially, but not exclusively, to integrated injection logic (12L) devices.
Integrated injection logic and similar devices (e.g.
integrated Schottky logic (ISL) devices) which are very compact and facilitate very high packing density combined with high speed operation usually comprise a vertical multi-collector transistor providing a plurality of outputs and fed by carrier injection from a lateral current source transistor in the case of 12L logic devices or from a resistor or field-effect transistor in the case of other semiconductor injection logic devices. These multi-collector and current source transistors are formed in the same general area on a semiconductor chip and consequently allow for a very compact construction facilitating high packing density which renders them particularly suitable for use in semiconductor memories.
The vertical multi-collector transistor is commonly defined by a row of n+ regions (collectors/outputs) formed on a common switching land (base) of p-type semiconductor material (e.g. silicon) which is itself embodied in an n-type semiconductor layer (emitter) carried by an n+ substrate.
The lateral current source transistor includes a p-type or p+ region emitter or injector) formed in the above mentioned n-type layer which defines the base of this transistor in close proximity to the aforesaid switching land of p-type material which may define the collector of the current source transistor or a p+ contact region may be provided in the switching land to define the collector.Carrier injection is fed to all the collectors of the multicollector transistor from the single current source lateral transistor as a consequence of which such known injection logic devices suffer from differential delays due to the n+ collectors of the multi-collector transistor being located at increasing distances from the current source transistor injector and the consequential increasing resistance and voltage drop over the current path through the common switching land to the respective collectors of the transistor. Moreover, these injection logic devices are subject to so-called fan-out sensitivity.
The problem of differential delay may be overcome by arranging that the switching land of the injection logic device is of annular configuration and that the injector region of the planar transistor is located on the n-type layer (base) at the centre of the annulus so that the collector regions of the multicollector transistor which may be diffused into the switching land are equispaced from the injector region. However, this construction does not overcome the problem of fan-out sensitivity previously referred to and other layout techniques which have been proposed to deal with both of the problems all compromise the overall performance of the logic devices.
According to the present invention a multi-output injection logic device comprises a plurality of electrically-interconnected switching lands each of which embodies a single collector/output of a multicollector transistor which has operatively associated with it an individual injector which is electrically connected to the other injector(s) of the device so that in operation of the device the collectors/outputs of the multi-collector transistor will be supplied with injection current over separate paths through the respective switching lands, the collectors/outputs being equidistant from their respective injectors in order to avoid differential delay.
The switching lands may comprise a plurality of narrow rectangular regions in parallel relationship diffused into a base layer of opposite type conductivity carried by a contact substrate. The injector regions of the device which will normally be located adjacent to corresponding ends of the switching lands and the switching lands themselves (or contact regions thereof) may be electrically interconnected by suitable multi-layer metallisation techniques.
By way of example the present invention will now be described with reference to the accompanying drawings in which:
Figures 1 and 2 show diagrammatic plan and sectional views, respectively, of a known construction of semiconductor integrated injection logic (12L) device;
Figure 3 shows a diagrammatic plan view of an 12L device constructed in accordance with the present invention; and
Figures 4, 5 and 6 show diagrammatic sectional views taken along the lines A-A, B-B and C-C in
Figure 3.
Referring to Figures 1 and 2 of the drawings, these show diagrammatic views of a known semiconductor integrated injector logic device. The device illustrated comprises a semiconductor chip (e.g.
silicon or gallium arsenide) having a vertical multicollector n-p-n transistor which in the present example consists of a p+ contact region (input) 1 and p-type region (base) forming a switching land 2 embodied by diffusion into an n-type layer (emitter) 3 and multiple collectors or outputs defined by n+ regions 4, 5 and 6.
The integrated injection logic device also comprises a current injection lateral p-n-ptransistorwhich consists of a pe emitter (injector) 7, n-type layer 3 already referred to which constitutes the base of the current source transistor and the aforesaid pt contact region 1 and the switching land 2 which define the collector of the current source transistor.
An n+ guard ring 24surrounds the switching land 2 in order to provide isolation between the injection device shown and adjacent devices.
In operation of the device injection current is supplied to the multi-collector transistor by the current source transistor and as can be appreciated from the drawings the collectors or outputs 4,5 and 6 are located at increasing distances from the injector 7 of the lateral transistor. Consequently, the resistance presented to the current flow by the switching land 2 between the injector 7 and the outputs 4,5 and 6 and the consequential voltage drop along the switching land 2 produces a differential delay be tween switching of the multiple collector outputs as well as different drive capabilitiesforthe respective outputs. The differential delay results in a different speed performance for each of the outputs 4,5 and 6.
Additionally, since the current for the outputs of the multi-collector transistor is derived from a single injector 7 so-called fan-out power sensitivity occurs.
If, for the purpose of increasing the speed performance of the device shown the two sides of the transistor collector or output regions 4,5 and 6 were to be bounded by dielectric material so as to reduce capacitance and charge storage volume the problems of differential delay and fan-out power sensitivity would be compounded. This is because the vertical cross-sectional area of the switching land 2 providing a current path to the collector or output regions 4,5 and 6 would be reduced by being confined only to that area below the collector or output regions and thus the resistance of the current path would be substantially increased. Consequently, there would be very little drive capability from the outputs 5 and 6 which are more remote from the injector region 7.
The present invention seeks to overcome the problems of differential delay and fan-out sensitivity referred to and an exemplary embodiment of the invention is shown in Figures 3 to 6.
Referring now to Figures 3 to 6 of the drawings, the integrated injection logic (12L) device depicted which may be produced by silicon bipolar processes comprises three separate p-type switching lands 8,9 and 10 which are of narrow rectangular form and parallel to one another. The switching lands embody individual collectors/outputs 11,12 and 13, respectively as well as respective input p+ contact regions 14,15 and 16. The vertical multi-collector transistor thus comprises the collectors/outputs 11,12 and 13, contact region inputs 14,15 and 16 and switching lands 8,9 and 10 and an n-type layer 17 defining the transistor emitter.The multi-collectortransistor is effectively supplied with current from an injection transistor comprising three p+ emitters (injectors) 18,19 and 20 which are electrically interconnected by means of a metal strip 21 produced by a multi-layer metallisation technique and which define a p-n-p structure with the n-type layer 17 and p+ contact regions 14,15 and 16 of the switching lands 8,9 and 10 which are also electrically interconnected by metal strip 22 as may be formed by the multi-layer metallisation technique.
As can be seen from the drawing the collectors/ outputs 11,12 and 13 of the transistor are equally spaced from their appertaining injectors 18,19 and 20 and the outputs are effectively connected in parallel relationship. Consequently the problem of differential delay and different drive capability of the outputs due to the voltage drop between collectors/ outputs on the same switching land is avoided as is the fan-out power sensitivity problem due to the effective series connection of the collectors in the known device shown in Figures 1 and 2. Additionally, a dielectric layer 23 (e.g. silicon dioxide) may be arranged to bound two sides of each of the switching lands 8,9 and 10, as shown, so that capacitance and charge storage volume are reduced and the switching speed performance of the device accordingly improved.This is possible in the case of the present invention due to the fact that the current path to the collectors/outputs 11,12 and 13 is not confined to a single switching land as in the case of the known construction shown in Figures 1 and 2 where the cross-sectional area of the land is reduced so much by the bounding of the sides of the collector regions with dielectric material as to deprive the more remote collectors/outputs of any worthwhile drive capability. In the device construction according to the present invention the current path to the collectors/outputs is divided into separate paths through switching lands 8,9 and 10 so that the reduction of the cross-sectional area of the lands due to the bounding of the collectors with dielectric material can be tolerated.
By reason of their compactness which facilitates high packing density the injection logic devices according to the invention are particularly suitable for use in integrated circuit memories and the repetitive pattern of the device layout renders it particularly suitable for semi-custom logic array applications.
It will be appreciated that the injection device depicted in the drawings is diagrammatic and that in practice metal terminal connections will be made to the various regions through windows in the dielectric (e.g. silicon dioxide).
Although the present invention has been specifically described with respect to an integrated injection logic device, it should be appreciated that the principle of the invention may be applied to other forms of injection logic devices which include a wide range of semiconductor technologies and employing different kinds of metallisation interconnection techniques.
Claims (9)
1. A multi-output injection logic device comprising a plurality of electrically-interconnected switching lands each of which embodies a single collector/ output of a multi-collector transistor which has operatively associated with it an individual injector which is electrically connected to the other injector(s) of the device so that in operation of the device the collectors/outputs of the multi-collector transistor will be supplied with injection current over separate paths through the respective switching lands, the collectors/outputs being equidistant from their respective injectors in order to avoid differential delay.
2. A multi-output injection logic device as claimed in claim 1, in which the switching lands comprise a plurality of narrow rectangular regions in parallel relationship diffused into a base layer of opposite type conductivity carried by a contact substrate.
3. A multi-output injection device as claimed in claim 2, in which the injectors are located adjacent to corresponding ends of the switching lands.
4. A multi-output injection device as claimed in claim 2 or claim 3 in which the switching lands or contact regions thereof are electrically intercon nected by multi-layer metallisation techniques.
5. A multi-output injections logic device as claimed in any preceding claim, in which the multicollector transistor is fed with injection current from a lateral current source transistor.
6. A multi-output injection logic device as claimed in any of claims 1 to 4, in which the multi-collector transistor is fed by carrier injection from a resistor or field-effect transistor.
7. A multi-output injection logic device as claimed in claim 5, in which the collectors/outputs of the multi-collector transistor are defined by n+ regions formed individually on respective switching lands of p- type semiconductor material which are embodied in an n-type semiconductor layer (base) carried by an n+ substrate.
8. A multi-output injection logic device as claimed in claim 7, in which the lateral current source transistor includes a p-type or p+ region formed in then-type semiconductor layer which defines the base.
9. A multi-output injection device substantially as hereinbefore described with reference to Figures 3 to 6 of the accompanying drawings.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08402477A GB2153587A (en) | 1984-01-31 | 1984-01-31 | Improvements relating to semiconductor injection logic devices |
| DE19853503068 DE3503068A1 (en) | 1984-01-31 | 1985-01-30 | INJECTION CURRENT LOGIC SEMICONDUCTOR COMPONENT |
| NL8500258A NL8500258A (en) | 1984-01-31 | 1985-01-30 | SEMICONDUCTOR INJECTION LOGICAL DEVICE. |
| JP60017694A JPS60187050A (en) | 1984-01-31 | 1985-01-31 | Multioutput injection logic element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08402477A GB2153587A (en) | 1984-01-31 | 1984-01-31 | Improvements relating to semiconductor injection logic devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8402477D0 GB8402477D0 (en) | 1984-03-07 |
| GB2153587A true GB2153587A (en) | 1985-08-21 |
Family
ID=10555799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08402477A Withdrawn GB2153587A (en) | 1984-01-31 | 1984-01-31 | Improvements relating to semiconductor injection logic devices |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS60187050A (en) |
| DE (1) | DE3503068A1 (en) |
| GB (1) | GB2153587A (en) |
| NL (1) | NL8500258A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1497892A (en) * | 1975-03-05 | 1978-01-12 | Ibm | Integrated circuits |
-
1984
- 1984-01-31 GB GB08402477A patent/GB2153587A/en not_active Withdrawn
-
1985
- 1985-01-30 DE DE19853503068 patent/DE3503068A1/en not_active Withdrawn
- 1985-01-30 NL NL8500258A patent/NL8500258A/en not_active Application Discontinuation
- 1985-01-31 JP JP60017694A patent/JPS60187050A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1497892A (en) * | 1975-03-05 | 1978-01-12 | Ibm | Integrated circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| NL8500258A (en) | 1985-08-16 |
| JPS60187050A (en) | 1985-09-24 |
| DE3503068A1 (en) | 1985-08-08 |
| GB8402477D0 (en) | 1984-03-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1044817A (en) | Integrated circuit and method for fabrication thereof | |
| US3993918A (en) | Integrated circuits | |
| US3823353A (en) | Multilayered vertical transistor having reach-through isolating contacts | |
| US3955210A (en) | Elimination of SCR structure | |
| US3922565A (en) | Monolithically integrable digital basic circuit | |
| US3005937A (en) | Semiconductor signal translating devices | |
| US3590345A (en) | Double wall pn junction isolation for monolithic integrated circuit components | |
| KR0133204B1 (en) | Integrated circuit with anti-latch-up circuit in complementary mos circuit technology | |
| US3961351A (en) | Improvement in or relating to integrated circuit arrangements | |
| US4825273A (en) | Semiconductor integrated circuit device | |
| US4288805A (en) | Integrated logic gate with NPN inverter, PNP clamp, coupling, Shottky diodes and diffused crossunder | |
| US3665266A (en) | Low saturation resistance,low offset voltage,monolithic analog switch | |
| CA1113614A (en) | Structure for logic circuits | |
| US3947865A (en) | Collector-up semiconductor circuit structure for binary logic | |
| US4725745A (en) | Bi-MOS PLA | |
| US4243896A (en) | I2 L Circuit with auxiliary transistor | |
| US4145621A (en) | Transistor logic circuits | |
| US4175240A (en) | Integrated logic circuit with a current source made as a field-effect transistor | |
| GB2153587A (en) | Improvements relating to semiconductor injection logic devices | |
| US4345166A (en) | Current source having saturation protection | |
| US4163244A (en) | Symmetrical integrated injection logic circuit | |
| US4158783A (en) | Current hogging injection logic with self-aligned output transistors | |
| US4979011A (en) | SCR structure for fast turn-on switching | |
| US4097888A (en) | High density collector-up structure | |
| GB1182324A (en) | Improvements in or relating to Semiconductor Matrices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |