GB2150794A - Data display arrangement with variable rate scrolling - Google Patents

Abstract

In a data display arrangement, data stored in display memory (3) or received directly from an outside source (16-17) is transferred via buffer (18) to a display memory (3) for display on CRT (1), possibly in colour. The displayed data is scrolled by processor (4) at a rate depending on the rate of reception of data. The data may be scrolled upward line-by-line as new data is written at a writing point (WP) initially near the top of the screen. If the screen above the WP becomes full, the scrolling rate is progressively increased and the WP is lowered. If the WP reaches a lower limit, the scrolling (if of characters) changes to 'hard' i.e. row- by-row. Alternatively the rate of scrolling may be a function of the amount of data in buffer (18) awaiting display. <IMAGE>

Description

SPECIFICATION Data Display Arrangements This invention relates to data display arrangements of a type for displaying as an entity on the screen of a CRT (cathode ray tube) or other raster scan display device, a quantity of data which is stored in a display memory and is accessed repeatedly for its display in a recurrent cycle of scanning lines. The scanning lines can be produced with or without interlaced field scanning.

In a data display arrangement of the above type, the stored data can comprise at least one information bit in respect of each of the pixels or dots which are produced on the screen of the display device by the scanning action. Provided that the information bits for the successive dot rows of the display are read out from the display memory in the same lines of the scanning cycle in each field, the display is a static display.

It is known that a static display as thus produced can be "scrolled" by modifying the read out operation every few fields such that information bits for the dot rows of the display are read out from the display memory in progressively different scanning lines. The displayed data can be cycled/wrapped around if dot rows "lost" at the top of the display are re-inserted at the bottom. However, it is more usual to progressively change the stored data in the display memory as the scrolling takes place. If the information bits for each dot row are read out in the preceding adjacent scanning line rather than the scanning line in which they were currently being read out, then visually smooth scrolling occurs because the displayed data is moved (up) only one scanning line every few fields.Visually smooth scrolling would also occur if the displayed data is moved up on a few scanning lines every few fields.

The scrolling can be made hard, i.e. less smooth such that it is visually "jerky", by reading out the information bits for each dot row for display positions which are not on adjacent scanning lines but which instead are disposed a number of scanning lines apart. For displayed data which is textual, comprising rows of characters, this hard scrolling can be on a character row basis where a character row is made up of a number of immediately successive dot rows. The rate at which the scrolling (smooth or hard) is effected is determined by how frequently the scanning lines for reading out the information bits for the dot rows are changed.

In a data display arrangement of the type set forth above, presently known scrolling means for effecting either smooth or hard scrolling are set to operate at a selected fixed scrolling rate which is compatible with an expected rate at which data to be displayed by scrolling is to be received. However, if the rate of data reception becomes greater than the expected rate, the selected rate of scrolling can become inadequate for dealing with the quantity of data being received. As a result, there exists the disadvantage that the data reception may have to be interrupted periodically to allow the scrolling to catch up, or that a buffer memory sufficiently large to store the data waiting for display would have to be provided.

It is an object of the present invention to provide a scrolling means which avoids these disadvantages.

According to the invention, there is provided in a data display arrangement of the type set forth above, a scrolling arrangement by which displayed data can be progressively shifted (vertically) on the screen of the display device to effect scrolling, which scrolling arrangement is characterised by comprising means for determining the rate of scrolling as a function of the rate of reception into the data display arrangement of the data to be displayed.

In carrying out the invention, the scrolling arrangement can include, for vertical scrolling, means for determining at a position intermediate the top and bottom of the screen a so-called "writing-point" at which data to be scrolled is initially written onto the screen, means for altering the position of the writing-point such as to increase the available display area of the screen where scrolling is occurring as the rate of data reception increases, and means for determining the rate of scrolling as a function of the position of the writing-point.

In operation, the scrolling arrangement can be arranged to have the writing-point initially positioned a little way above the bottom of the screen, once the screen has been filled with data from the display memory but before scrolling commences. As further data arrives for display, scrolling commences at an initial rate which increases progressively as the writing-point moves downwards with increase in the rate of data reception. When the rate of data reception slows the writing-point moves back towards its initial position and the rate of scrolling decreases correspondingly.

Conveniently, the scrolling arrangement includes a buffer memory in which received data for display is stored temporarily prior to being stored in the display memory, the position of the writing-point being determined by the relevant means as a function of the quantity of data awaiting transfer from the buffer memory to the display memory. It will be apparent that at any time, this quantity of data will depend on how fast scrolling is taking place to remove data from the buffer memory, relative to how fast data reception is taking place to insert data into the buffer memory.

Alternatively, when the scrolling arrangement includes a buffer memory, the writing-point can be fixed at a limit position at one end (top or bottom) of the screen, and the rate of scrolling is determined simply as a function of the quantity of data awaiting transfer from the buffer memory to the display memory that is, without any alteration of the writing-point position.

In a scrolling arrangement according to the invention, the size of buffer memory which is required can be considerably smaller than that which, as aforesaid, may be provided in a presently known scrolling arrangement having a selected fixed scrolling rate.

The operation of the scrolling arrangement is preferably such as normally to effect smooth scrolling at an appropriate rate, but to revert to hard scrolling and thereby increase the rate of scrolling (e.g. to one text row at a time) when the maximum rate of soft scrolling is inadequate for maintaining a progressive scrolled display of incoming data, because the rate of data reception is too great for this maximum rate.

In order that the invention may be more fully understood reference will now be made by way of example to the accompanying drawings, of which: Figure 1 shows a block diagram of a data display arrangement in which the present invention can be embodied; Figure 2 shows a block diagram of certain elements of a display timer in the arrangement of Figure 1; and Figure 3 illustrates diagrammatically the effect of the invention on displayed data.

Referring to the drawings, the data display arrangement shown in Figure 1 comprises a display device 1, a display generator 2, a display memory 3 and a processor 4. The display device 1 is suitably a colour television monitor (TV) which is connected to receive R, G, B, video signals from the display generator 2. These R, G, B, video signals are produced in the display generator 2 by three digital-to-analogue converters (DiA) 5,6 and 7, respectively. The display generator 2 also includes a colour look-up table (CLUT) 8 which is suitably a read-only memory and is responsive to digital information from the display memory 3 to produce digital signals for driving the converters 5,6 and 7.A display timer (TIM) 9 in the display generator 2 provides line and field synchronisation signals LS and FS for the television monitor 1 over a connection 10. As will be described, the display timer 9 also provides, under the control of the processor 4, timing (address) signals T for accessing the display memory 3 to cause the transfer of the digital information to the colour look-up table 8.

The display memory 3, which is suitably a random-access memory (RAM), has a capacity sufficient for storing the maximum quantity of data that is to be displayed as an entity on the screen of the television monitor 1. The display need not be a full screen display.

A combined address/data bus 12 interconnects the display generator 2 and the display memory 3 with the processor 4. A main memory 13, which is also in the form of a random-access memory (RAM), is also connected to the address/data bus 12. Data entry apparatus in the form of a keyboard 14 and a writing tablet 15 are connected to the processor 4.

Also, a teletext input apparatus 16 gives access to broadcast teletext television services such as CEEFAX and ORACLE, and a viewdata terminal apparatus 17 provides a link to a telephone line for access to external data base such as PRESTEL. The processor 4 is suitably a commercially available microcomputer.

In operation of the arrangement, under the control of the processor 4, display data generated by the data entry apparatus 14 and 15 is stored in the main memory 13. The display data stored in the main memory 13 can thereafter be selected for display.

When data is selected, it is transferred over the bus 12 from the main memory 13 to the display memory 3 where it is accessed for display, as aforesaid. This transfer is effected via a buffer memory 18. Because the display data is already stored in the arrangement (i.e. in the memory 13) it can be read-out for display at a controlled rate. Either discrete entities of data can be displayed, or data may be read out progressively and scrolled, depending on the data content.

Display data can also be derived from external transmission information received at the teletext and viewdata terminals 16 and 17. Such display data may optionally be transferred directly under the control of the processor 4 to the display memory 3 for display, without being stored in the main memory 13. Particularly as regards display data acquired at the viewdata terminal 17, the data being received may be textual and of sufficient quantity to require progressive scrolling as it is displayed on the screen of the television monitor 1.

For displaying, say, text consisting of successive rows of characters, the processor 4 can be arranged to start the display as soon as the first row of characters has been stored in the display memory 3, rather than waiting for a "full" screen of text to be stored. For this mode of display, a so-called "writing-point" at which the first row of characters is initially written (displayed) on the screen would be located at, say, a position two-thirds up from the bottom of the screen. This is illustrated in Figure 3a which shows diagrammatically a display screen DS on which is written a first character row CR1 at a writing-point position WP1. After the first row of characters has been written, the writing-point is moved to a next position WP2 at which a second row of characters CR2 is written.Thereafter, the writing-point is moved to successive further positions WP3 to WPN at which respective further rows of characters CR3 to CRN are written. Once the writing-point has reached the position WPN, succeeding rows of characters are written in turn at this writing-point position WPN. To accommodate this, the display is now scrolled upwards at an initial rate. Figure 3b illustrate by way of example a display instant at which the first row of characters CR1 has just been scrolled out of the display, so that the row CR2 is the first row at the top of the screen, and rows CR3 to CRN are now followed by succeeding rows CRN3 to CRN4 each of which were written at the writing-point position WPN.

If the initial rate of scrolling is not fast enough to displace a row of characters away from the position WPN before the next row of characters has been received for writing at that position, then as will be described, this is detected and the writing-point is moved downwards to a lower position WPN1 at which the next row of characters can now be writted. This action is accompanied by an increase in the rate of scrolling. If the rate of scrolling is still inadequate, the writing-point can be moved progressively downwards a number of further lower positions WPN2 to WPNn, in turn as indicated in Figure 3b. At each successive position, there is a further increase in the rate of scrolling. When the last position WPNn has been reached, the scrolling may thereafter be made hard to displace a complete row of characters at a time.Once the scrolling "catches-up" with the received data, a reverse operation tends to occur to restore the writing-point towards the position WPN until equilibrium is reached. The above operations are carried into effect by changing adaptively the phase of the timing (address) signals T produced by the display timer 9 relative to the line and field synchronisation signals pulses LS and FS. This may be achieved as follows.

The display timer 9 can take the form shown in Figure 2 which also shows the television monitor 1, the display memory 3, the processor 4 and the buffer memory 18. The display data in the memory 3 is in bit-map form and can be considered to be stored as at least one bit matrix comprising y bit rows each containing x bits. It is assumed that this size of matrix stores a quantity of data which is to be displayed as an entity. it is further assumed that the television monitor 1 is arranged conventionally for 625-line interlaced scanning at 25 fields per second.

The display in each field can then be composed of, say, 256 scanning lines LO to L255. If each of these scanning lines contains 256 pixels or dots, then for the display memory 3, x=256 and y=256.

The signal LS of line frequency drives the television monitor 1 for each line scan and the signal FS of field frequency drives the television monitor 1 for each field scan. A signal FD of dot frequency drives a pulse generator 20 which applies dot pulses to a dot counter 21 having a modulo-256 count. The dot counter 21 produces a recurrent cycle of 256 dot addresses DO--D255 which are used to address the x=256 bit positions in each of the y=256 bit rows of the display memory 3. Once per cycle of the counter 21, which occurs at the line frequency LS, a dot pulse is applied to a row counter 22, which also has a modulo-256 cycle, to produce a recurrent count of 256 row addresses ROR255. The signal FS synchronises the counter 22 with the scanning action of the television monitor 1.The display timer 9 also includes an adder 23, and two offset registers 24 and 25.

Assuming that an offset number applied to the adder 6 from each of the registers 24 and 25 is initially 0, then the row addresses ROR255 as produced by the row counter 22 will be applied directly to the display memory 3 to address the y bit rows in turn, starting from the first row RO. As each bit row is being addressed, all of the bit positions thereof are being addressed in turn by the dot addresses DOD255. Since the signals LS and FS are used for raster scanning of the television monitor 1, the line and field scan will be in synchronisation with the addressing of the display memory 3.However, for the display sequence assumed by way of example in the foregoing description, it is required that the first row of characters CR1 be displayed about two-thirds up from the bottom of the screen at writing-point position WP1. A row of characters will typically occupy ten successive scanning lines which, therefore, for this first row will be, say, scanning lines L90 to L99.

If the data for this first row CR1 is stored in the display memory 3 in bit rows having addresses RO to R9, then it is apparent that these bit rows will have to be addressed whilst the scanning lines L90 to L99 occur. To achieve this, the processor 4 is operable at the outset of the display sequence to insert the offset number 166 into the offset register 24. This offset number 166 is applied to the adder 23 along with the row addresses from the row counter 22, so that the row addresses as actually applied to the display memory 3 are advanced in number by 166. In, particular, the bit rows having addresses RO to R9 will be addressed by modified address R90+166= RO to R99+166=R9so as to be read out for display at writing-point position WP1 in the scanning lines L90 to L99.The data for the subsequent rows of characters CR2 to CRN are conveniently stored in immediately succeeding groups of bit rows in the display memory 3 so as to be read out for display at the succeeding writingpoint positions WP2 to WPN without further alteration of the relative scanning and addressing phases. Only a portion of the row address cycle is used for read-out, such that addressing does not occur at this time to read-out character rows which would be written below the position WPN.

Once the writing-point position WPN has been reached, it is maintained initially so that the further character rows CRN1 to CRNn can be written at this writing-point position WPN. To achieve this, scrolling now has to occur. This scrolling is effected under the control of the processor 4 by means of a scrolling offset number inserted into the offset register 25. This scrolling offset number is incremented periodically and the resultant number is also applied to the adder 23 to advance progressively the row addresses as actually applied to the display memory 3. For example, a scrolling offset number which is incremented by 1 will produce a smooth scroll, the rate of which is determined by the frequency at which incrementing occurs.The rate of scrolling is determined by the processor 4 in accordance with the quantity of data awaiting transfer from the buffer memory 18 to the display memory 3. This is signified to the processor 4 over a connection 19. Additionally, the processor 4 can be operabie in accordance with this quantity of data to determine the size of the portion of the addressing cycle used to read out character rows from the display memory 3. This has the effect of introducing the writing-point positions WPN 1 to WPNn into the display operation, as previously mentioned. Also, the part of the display memory 3 which is addressed by the active read-out portion of the addressing cycle will alter progressively as scrolling takes place and new data replaces "lost" data in the display.

As a possible modification, the processor 4 can alternately be made operable to cause the writingpoint to remain at the limit position WPNn, and simply to control the rate of scrolling as a function of the quantity of data awaiting transfer in the buffer memory 18. For this modification, it becomes unnecessary to inhibit part of the row address cycle.

Claims (7)

1. In a data display arrangement for displaying as an entity on the screen of a raster scan display device, a quantity of data which is stored in a display memory and is accessed repeatedly for its display in a recurrent cycle of scanning lines, a scrolling arrangement by which displayed data can be progressively shifted on the screen of the display device to effect scrolling, which scrolling arrangement is characterised is by comprising means for determining the rate of scrolling as a function of the rate of reception into the data display arrangement of the data to be displayed.

2. A scrolling arrangement as claimed in Claim 1, characterised by including, for vertical scrolling, means for determining at a position intermediate the top and bottom of the screen a writing-point at which data to be scrolled is initially written onto the screen, means for altering the position of the writing-point such as to increase the available display area of the screen where scrolling is occurring as the rate of the data reception increases, and means for determining the rate of scrolling as a function of the position of the writing-point.

3. A scrolling arrangement as claimed in Claim 2, characterised by comprising a buffer memory in which received data for display is stored temporarily prior to being stored in the display memory, the position of the writing-point being determined by the relevant means as a function of the quantity of data awaiting transfer from the buffer memory to the display memory.

4. A scrolling arrangement as claimed in Claim 2, characterised by including, means for determining a fixed writing-point at a limit position at one end of the screen, and a buffer memory in which received data for display is stored temporarily prior to being stored in the display memory, the rate of scrolling being determined as a function of the quantity of data awaiting transfer from the buffer memory to the display memory.

5. A scrolling arrangement as claimed in any preceding claim arrangement normally to effect smooth scrolling at an appropriate rate, but to revert to hard scrolling and thereby increase the rate of scrolling when the maximum rate of soft scrolling is inadequate for maintaining a progressive scrolled display of incoming data, because the rate of data reception is too great for this maximum rate.

6. In a data display arrangement, a scrolling arrangement substantialiy as hereinbefore described with reference to the accompanying drawings.

7. A data display arrangement embodying a scrolling arrangement as claimed in any preceding claim.