GB2150746A - MOS transistor with surface accumulation region - Google Patents
MOS transistor with surface accumulation region Download PDFInfo
- Publication number
- GB2150746A GB2150746A GB08332189A GB8332189A GB2150746A GB 2150746 A GB2150746 A GB 2150746A GB 08332189 A GB08332189 A GB 08332189A GB 8332189 A GB8332189 A GB 8332189A GB 2150746 A GB2150746 A GB 2150746A
- Authority
- GB
- United Kingdom
- Prior art keywords
- region
- ldmost
- resistance
- voltage
- drift region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009825 accumulation Methods 0.000 title abstract description 3
- 239000004065 semiconductor Substances 0.000 claims description 12
- 230000015556 catabolic process Effects 0.000 claims description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000012212 insulator Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 210000000746 body region Anatomy 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229960001866 silicon dioxide Drugs 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- ZNZNXSDPNKCWNO-UHFFFAOYSA-N S.CO Chemical compound S.CO ZNZNXSDPNKCWNO-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
Abstract
The product of the on-resistance and the area of a high-voltage LDMOST is reduced by a factor of two to four by creating a surface accumulation region along the surface of the drift region 4 in the on- state of the device, it can be created by using a semi-insulating layer 10 over a thin field oxide region 6 covering the drift region 4 or via a fourth electrode located between the gate 8 and the drain 2, and held at a constant high voltage. <IMAGE>
Description
SPECIFICATION
Reductin of the on-resistance of power mosfets by surface accumalation layers
TECHNICAL FIELD:
This invention relates to the lateral power
MOSFET's.
BACKGROUND:
THE prior art of the design of the lateral power MOS transistor is described by S.CO
LAK, IEEE Transc. on ED, 28, 1455-1466, (1981). This design is shown in Fig. 1. It comprises a source region (1) made of a semiconductor material type I (n or p), a drain region (2) of the same type, a body region (3) of the same semiconductor but oppositely doped (i.e. p or n respectively denoted type
II), a drift region (4) of type I lightly doped material, and substrate (5) of a lightly doped type II semiconductor. The surface of the device is covered by an insulating material (6) (typically SiO2). THE regions 7, 9, 8, correspond respectively to the source contact, the drain contact, and the gate metalization. THE gate and drain contacts overlaps the drift region partially THIS structure is called the
REDUCED SURFACE FIELD (RESURF)
LATERAL DOUBLE DIFFUSED MOSFET (LDMOST).THIS design, as well as it's predecessors, suffers from a well known trade off between the break down voltage and the onstate conductance of the device. Furthermore, the on-state conductance can not be increased beyond QA/L where ad is the drift region conductance, Ld is the average spacing between the gate and drain, and A is the cross section area of the drift region normal to the surface. In addition precise control of the total impurity charge in the drift region is required which affects the yield and hence the cost of the device. A refined structure of this RE
SURFed LDMOST was also proposed by S.Colak Yet, this refined structure suffers from the same defects mentioned earlier.
ESSENTIAL TECHNICAL FEATURE
According to this invention, there is provided a lateral power metal oxide-semiconductor transistor (LDMOST) with a means of creating an additional conduction path (in addition to the distributed resistance of the drift region) between the channel and the drain. This additonal conduction path takes the form of an accumulation region at the surface of the drift region. This additional conduction path exists only in the on state of the device. The following advantages can be gained from the additional conduction path: A-A factor of 2-4 increase in the on-state conductance of the LDMOST for a given device area and breakdown voltage. Alternatively a factor of 2-4 reduction in the device area can be achieved, for a given on state conductance and breakdown voltage.
B-The on-state conductance can exceed the upper limit of the conductance of the drift region = dA/Ld C-Simple device structure with no tight tolerance on doping and dimensions.
EXAMPLES:
Example 1
Fig. 2 shows the proposed new structure of
LDMOST. This particular structure is composed of a source region 1, drain region 2, a body region 3, a drift region 4, a substrate region 5, an insulating region 6, extending all over the the device structure, and a semiinsulating region 10 covering the oxide region. The contacts region 7,8,9 are as in Fig.
1. The regions 1,2 and 4 are of type I semiconductor, while regions 3,5 are of type
II semiconductor.
The semi-insulating layer can be a semiinsulating polycrystalline Silicon (SIPOS) layer. The insulator is typically made of high quality silicon dioxide. It must be thin, typically 0.1#m. THE conduction path between source and drain can be switched off by applying an appropriate voltage to the gate.
Under this condition, the linear potential variation along the SIPOS layer 10 acts to reduce the maximum electric field at the semiconductor surface. As has already been mentioned, tight tolerance on the total number of ionized impurity atoms is required for the prior-art
LDMOST. The use the SIPOS layer in the structure of Fig. 2 relaxes this requirement.
THE conduction path between the drain and source can on the other hand be turned on by applying an appropriate voltage to the gate.
Only for the ease of presentation, assume type
I semiconductor is a negatively doped (or n type) semiconductor. For this case the gate voltage needed to switch the LDMOS on is positive, typically around 10 volt, while the drain voltage is now low in range of 1-2 volts. The potential drop between the drain and the gate is uniformly distributed along the
SIPOS layer. THE SIPOS layer, thus acts an extended gate finger reaching to the drain.
given that the insulator layer 6 is thin enough, this positively biased extended gate region 7 causes an accumalation region to build up at the surface of the drift region. This accumalation layer acts to reduce the on resistance of the device. IN order to achieve the maximum reduction in the on resistance of the device, the thickness of the insulator region 6 should be as small as possible typically below 0. 15 ,um. Also, to this end, it is advantageous to replace the SiO2 over the drift region by a
Silicon nitride/Silicon-dioxide sandwich. provided that the capacitor made of drain metal/5i02/drift-region semiconductor has a negative flat-band voltage, this accumalation region extends right through to the drain region 2.IT is also obvious that the reduction of the on-resistance via the formation of the accumalation layer is over and above that reduction indirectly achieved due the tendancy of the SIPOS layer to raise the break down voltage of the device in the off-state.
Example 2
THE principle of reduction of the on-resistance of the LDMOST via a surface accumalation layer can be further enhanced as follows:
Let the potential at a given position x in the
SIPOS layer be V when the LDMOST is off.
the potential distribution, and hence, the break down voltage of the LDMOST is not affected by the introduction of a "helping" electrode at the same position x, and biased with the same voltage V. However, if this "helping" electrode is maintained at the high voltage V when the LDMOST is turned on, a significant reduction in the on-resistance takes place. The structure of the LDMOST with the helping electrode is shown in Fig. 3. Regions 1-10 are the same as in Fig. 2. Region 11 is the helping electrode metalization. The fixed bias for the helping electrode can be simply derived from an on the chip polysilicon potential divider. Fig. 4 depicts the required bias connection. Terminals 1,2,3,4 and 5 are the source, gate, helping electrode, drain and supply voltage terminals respectively.
R1 is the load and may be on or off the chip. The polysilicon potential divider R2 and
R3 can be advantageously built on the chip, which should now be provided with an extra pin for the supply voltage. In choosing the location, and hence, the fixed bias of the helping electrode, care must be exercised to insure that the voltage V, which is almost totally dropped across the insulator region 6 in the on state, is smaller than the breakdown voltage of the insulator region. It may also be noted that a helping electrode with a fixed bias can be used to reduce the on-resistance with or without a SIPOS layer.
Example 3:
THE function of the horizontal pn junction formed between the drift region 4 and the substrate 5 in prior-art LDMOST (Fig. 1) is to reduce the maximum electric fields at the surface of the semiconductor. The SIPOS layer 10 of Fig. 2 does also the same function. In fact, the SIPOS layer tends to achieve the ideal case of a uniform surface field between the body region and drain region.
Consequently we need not use the RESURF structure of Fig. 1. The simpler structure of
Fig. 5 achieves a high breakdown voltage due to the field shaping effect of the SIPOS layer 10, as well as, a low on-resistance due to the accumalation region formation. Note that the regions 1-4 and 6-10 of Fig. 5 have the same meaning as in Fig. 2. The simple structure of Fig. 5 offers the advantages of uncritical fabrication tolerances and consequently high yields relative to the RESURFED structure of Figs. 1, 2, and 3.
Claims (4)
1. A high-voltage, Lateral, Double-diffused, Metal-Oxide semiconductor Transistor (LDMOST) provided with a means of creating an accumalation region at the surface of the drift region only in the on-state of the device.
The on-resistance of this LDMOST is lower than one-dimension geometrical limit of the drift resistance.
2. The means to create the surface accumalation region claimed in claim 1 can be a semi-insulating layer over a thin insulating region covering the surface of the drift region.
It can also take the form of a helping electrode located between the drain and the gate electrodes over the insulating region covering the drift region. Alternatively, both a semiinsulating region and a helping electrode can be used together to enhance the surface accmalation layer.
3. A high voltage LDMOST claimed in claim 1 with an on-resistance one half to one fourth the on-resistance of the prior LDMOST for the same breakdown voltage and device area. Alternatively, a high voltage LDMOST is claimed with one half to one fourth the area of the prior-art LDMOST but with the same on-resistance and breakdown voltage.
4. A high voltage LDMOST as claimed in claim 1, 2 and 3 but with a simple non
Resufed structure that requires no tight processing tolerances.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08332189A GB2150746B (en) | 1983-12-02 | 1983-12-02 | Mos transistor with surface accumulation region |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08332189A GB2150746B (en) | 1983-12-02 | 1983-12-02 | Mos transistor with surface accumulation region |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8332189D0 GB8332189D0 (en) | 1984-01-11 |
| GB2150746A true GB2150746A (en) | 1985-07-03 |
| GB2150746B GB2150746B (en) | 1988-02-24 |
Family
ID=10552720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08332189A Expired GB2150746B (en) | 1983-12-02 | 1983-12-02 | Mos transistor with surface accumulation region |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2150746B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5237186A (en) * | 1987-02-26 | 1993-08-17 | Kabushiki Kaisha Toshiba | Conductivity-modulation metal oxide field effect transistor with single gate structure |
| WO1997004488A2 (en) * | 1995-07-19 | 1997-02-06 | Philips Electronics N.V. | Semiconductor device of hv-ldmost type |
| US6087232A (en) * | 1997-10-28 | 2000-07-11 | Electronics And Telecommunications Research Institute | Fabrication method of lateral double diffused MOS transistors |
| WO2001061758A1 (en) * | 2000-02-18 | 2001-08-23 | Intersil Corporation | Lateral dmos improved breakdown structure and method |
| SG92658A1 (en) * | 1999-07-23 | 2002-11-19 | Inst Of Microelectronics | Lift off gate mos device |
| CN100376020C (en) * | 2003-12-29 | 2008-03-19 | 中芯国际集成电路制造(上海)有限公司 | A method for manufacturing transistor with extending gate |
| US10937872B1 (en) * | 2019-08-07 | 2021-03-02 | Vanguard International Semiconductor Corporation | Semiconductor structures |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1110391A (en) * | 1964-07-31 | 1968-04-18 | Rca Corp | Field effect transistor |
| GB2080023A (en) * | 1980-06-16 | 1982-01-27 | Philips Corp | Lateral insulated gate field effect transistor |
| EP0069429A2 (en) * | 1981-07-06 | 1983-01-12 | Koninklijke Philips Electronics N.V. | Insulated gate field effect transistor |
-
1983
- 1983-12-02 GB GB08332189A patent/GB2150746B/en not_active Expired
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1110391A (en) * | 1964-07-31 | 1968-04-18 | Rca Corp | Field effect transistor |
| GB2080023A (en) * | 1980-06-16 | 1982-01-27 | Philips Corp | Lateral insulated gate field effect transistor |
| EP0069429A2 (en) * | 1981-07-06 | 1983-01-12 | Koninklijke Philips Electronics N.V. | Insulated gate field effect transistor |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5237186A (en) * | 1987-02-26 | 1993-08-17 | Kabushiki Kaisha Toshiba | Conductivity-modulation metal oxide field effect transistor with single gate structure |
| WO1997004488A2 (en) * | 1995-07-19 | 1997-02-06 | Philips Electronics N.V. | Semiconductor device of hv-ldmost type |
| WO1997004488A3 (en) * | 1995-07-19 | 1997-04-24 | Philips Electronics Nv | Semiconductor device of HV-LDMOST type |
| US6087232A (en) * | 1997-10-28 | 2000-07-11 | Electronics And Telecommunications Research Institute | Fabrication method of lateral double diffused MOS transistors |
| SG92658A1 (en) * | 1999-07-23 | 2002-11-19 | Inst Of Microelectronics | Lift off gate mos device |
| WO2001061758A1 (en) * | 2000-02-18 | 2001-08-23 | Intersil Corporation | Lateral dmos improved breakdown structure and method |
| CN100376020C (en) * | 2003-12-29 | 2008-03-19 | 中芯国际集成电路制造(上海)有限公司 | A method for manufacturing transistor with extending gate |
| US10937872B1 (en) * | 2019-08-07 | 2021-03-02 | Vanguard International Semiconductor Corporation | Semiconductor structures |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8332189D0 (en) | 1984-01-11 |
| GB2150746B (en) | 1988-02-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |