GB2150333A - Equipment for producing an indication for use in disabling a system - Google Patents

Abstract

In an intruder alarm system, the alarm circuitry (110) is controlled (i.e. armed, standby or set to any of a predetermined operational modes) by an access and control subsystem (100) which includes at least one remote control station (1) provided with both an input switch (2) and an annunciator (3) (e.g. buzzer), the control being effected by a coded operation of said switch. Commands such as WALK TEST, CIRCUIT SHUNT, "stand-by" and "active" are selected depending on the command. The detection loop processing control circuit (5) processes the detection loop circuit conditions and, depending on the condition of the alarm system, acts on them accordingly. <IMAGE>

Description

SPECIFICATION Equipment for producing an indication for use in disabling a system.

According to the present invention, there is provided equipment for producing an indication for use in disabling a system, the equipment comprising a switch and means for providing the said indication in response to detecting identity between an actual sequence of operations of the switch and a given sequence of operations of the switch.

The present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a functional block diagram of a burglar alarm system; Figure 2 shows details of an access and code control circuit; Figure 3 shows details of an alarm and control circuit; and Figure 4 shows a detection loop interface circuit.

Referring first to Figure 1, an intruder alert system is divided into two main parts, an access and control circuit 100 and an alarm system 101. The conditions and various modes of operation of the intruder alert system (IAS), which will be covered later, are controlled by an access code and control circuit 4, which forms part of a push button security access and control system (PBSACS) 100. The rest of the PBSACS consists of remote control panels 1 each of which consists of a push button switch 2 and an acoustic signalling device (buzzer) 3. Each remote panel is used to control the access code and control circuit 4 by inputting numbers via the push button 2 in serial format.This is carried out by pressing the push button the correct number of times corresponding to the number being entered, pausing and then entering any additional numbers, leaving pauses between each number entered. The buzzer 3 on each remote panel is used to signal system acknowledgements to the user.

The access and code control circuit 4 is responsible for putting the alarm system into a "standby" condition if the correct access code is entered on one of the remote control panels 1 or setting the system condition to "active" by pressing the push button 2 once. It is also responsible for setting or presetting modes of operation while the system is in the "standby" condition.

There are two modes available. The first mode is a facility called WALK TEST. In the case of this facility, the WALK TEST mode is put into operation by entering a seven on one of the remote control panels. The WALK TEST facility allows the user to test and therefore satisfy himself that all the sensors (except an exit/entry circuit) fitted under carpetting or on doors etc. are functioning correctly.

When the system is in the WALK TEST mode and a sensor is activated, an internal bell 9 sounds for the duration that the sensor is activated. In the case of testing an emergency circuit (PA), an outside bell 8 sounds as well as the internal bell for the duration of sensor activation. This tests for correct operation of a "panic alarm" (PA) circuit and the outside bell. To leave the WALK TEST mode, a one is entered on the push button. The system is then in the "standby" condition again.

The second mode is called CIRCUIT SHUNTING.

A typical example of its use would be with the system installed in a house. During sleeping hours it is often desirable to be able to protect the downstairs part of the house, but be able to move around quite freely upstairs, without triggering an alarm. In the case of this system, a CIRCUIT SHUNTED mode is preset by entering a nine on one of the remote control panels. When the nine has been entered, the system acknowledges this setting by causing the buzzer 3 in the remote panel to "bleep". To set the system condition to "active", a one is entered on the remote panel. The system is delayed by thirty seconds before going to the fully active condition. This gives the user time to vacate the ground floor. All remote panel buzzers sound until the system becomes fully active.During waking hours, the correct access code must be entered on an upstairs remote panel only, thus putting the system into the "standby" condition before going downstairs. The access code, if correct, is acknowledged by a "bleep" from the buzzer in the remote control panel. If no "bleep" is obtained, then the access code has not been accepted. A one must be entered to reset the code circuit and then the access code re-entered.

If the user proceeds down the stairs while the system is still "active", a pressure mat which is connected to the exit/entry circuit and which is fitted under the stair carpetting is activated and triggers the exit/entry timer circuit 6. This causes the buzzer 3 in the remote panels 1 to start bleeping, which reminds the user to go back to the upstairs remote panel and enter the access code before continuing downstairs. Going downstairs before putting the system into the "standby" condition will cause a full alarm condition. The CIRCUIT SHUNTED mode is automatically cleared when the access code is correctly entered and must be preset again if required. The CIRCUIT SHUNTED mode can be manually reset by entering an eight on the one of the push buttons 2.If the system is now put into the "active" condition by pressing the push button 2 once, all circuits will become active (after a 30 seconds delay) and if any sensor is activated on an UNSHUNTED alarm generating circuit, the system will go into the alarm condition. The alarm condition can be reset by entering the access code.

A detection loop processing control circuit 5 is controlled by the access code and control circuit 4.

Commands such as WALK TEST, CIRCUIT SHUNT, "standby" and "active" are selected depending on the command. The detection loop processing control circuit 5 processes the detection loop circuit conditions and, depending on the condition of the alarm system, acts on them accordingly. If an alarm condition is created an alarm timer circuit 7 is triggered. This circuit switches the internal bell 9 and the external bell 8 on and remains in this state for twenty minutes or until the system is reset, whichever is the sooner. The remote panel buzzers sound continuously until the system is reset. This is to let the user know that an alarm condition has occurred during his absence, which he would not otherwise know about if the bells had timed out.

The emergency loop (PA) circuit is processed continuously and if this circuit is activated, regardless of whether the system is "active" or on "standby", it will cause an alarm condition (except during WALK TEST). This alarm condition is reset in a slightly different manner from the normal alarm conditions. Instead of just entering the access code to silence the PA alarm, the access code must be prefixed with a one and then followed by the access code.

There is a tamper loop circuit which has been incorporated for the purpose of detecting if the wiring is being interfered with. With the alarm system "active", tampering will cause an alarm. With the system on "standby", tampering will cause all the remote panel buzzers only to sound. In this condition the buzzers can be silenced by entering a nine on one of the push buttons. The buzzers can be turned on again with an eight entered on one of the push buttons. In the normal condition the buzzers will silence as soon as the wiring fault is rectified. The presence of the buzzers aids the engineer to find the fault in the wiring.

The detection loop processing control circuit 5 contains anti-false alarm circuitry which prevents the system from being put into the "active" condition if any of the sensors are not in a healthy condition. This does not apply to sensors on a circuit which has been shunted.

The detection loop interface circuit 10 is a passive unit. Its function is to filter out noise from the incoming detection loops. It has facilities for connecting normally open (pressure mats) or normally closed switch contacts to the circuit 1 and circuit 2 inputs. The exit entry and tamper circuits are normally closed loops. The PA circuit is normally open. The detection loop interface circuit 10 introduces a delay of between 0.2 and 0.8 of a second from the time a sensor goes active to the time that the detection loop processing control circuit 5 receives the sensor's signal. This is a British Standard requirement and is referred to as the "break time".

The exit/entry timer circuit 6 is responsible for giving the user time to vacate (usually 30 seconds) the premises after the system active command has been entered on the remote panel nearest the exit/ entry route being used. During the exit time all remote panel buzzers 3 sound continuously and silence at the end of the exit period when the system switches to the "active" condition. The exitl entry timer circuit 6 is also responsible for allowing enough time on entering the premises, to enter the access code on the remote panel at the exit/entry route being used. Any progress made beyond the remote panel before the access code is entered will cause sensors on circuit 1 or 2 (zones 1 or 2) to be activated, thus resulting in an alarm condition. The alarm condition can be silenced by entering the access code.On entering the premises by the correct exit/entry route, a sensor connected to the exit/entry circuit triggers the exit/entry timer circuit 6 and causes the remote panel buzzers to bleep for the entry period (30 seconds). This reminds the user that the access code must be entered before any more progress is made. The remote panel buzzers continue to bleep until the access code is correctly entered. Failure to enter the access code during the entry period will cause the system to go into the alarm condition at the end of the entry period. The alarm condition can be silenced by entering the access code.

If an intruder breaks a window (without causing an alarm) near a remote panel and starts trying various access codes, the first incorrect code entered will trigger the exit/entry timer circuit 6. The timer circuit will run for approximately 30 seconds by which time if the correct access code has not been entered, the system goes into a full alarm condition. The remote panel buzzer 3 bleeps during the 30 second period.

Regarding the way the intruder alert system and conventional systems are actually installed, there are no major differences involved. The remote panels however, of which there are usually three, should be located one at the front and rear entrances to the premises (exit/entry routes) and at least one on the upstairs floor. In addition to this, one pressure mat is usually sited underneath stair carpetting and connected to the exit/entry circuit.

The intruder alert system electronics, which is housed in a steel box, should be installed at an area of maximum security and not in the exit/entry route as with conventional systems.

The following is a description of the electronic circuit operation of the intruder alert system as shown in Figures 2, 3 and 4.

Referring to Figure 2, the push button is connected between the positive supply rail and the control button input. The push switch is a normally open contact type. If the first number of the access code is a four, four pulses would be fed from the push button switch to clock input 14 of IC7, the clock line of a decade counter with 10 decoded outputs, via a simple switch debouncing circuit R34, R35, C7 and NAND gate ICla. The components D1, C11, R32, 33 and Schmitt trigger NAND gate IC1b form a selective digit circuit. This circuit separates the first, second and third numbers entered. When pulses are being entered by the push button switch, CWcharges via a diode D1. Diode D1 prevents the charge on C11 from leaking away through R34. This charge is fed via R33 to the Schmitt trigger NAND gate inputs lclb/8,9. This charge is allowed to leak away slowly through R32, which occurs when no pulses are being entered.

Whilst the number is being entered, the reset line, input 15 of IC7 is held low (reset-inactive) by output 10 of NAND gate IC2b of IC2, which allows the counter to count the four pulses being entered. For example, let the "4" output 10 on IC7 be connected via DIP switch 31 to connection "A". When the fourth pulse is entered, output line number "4" will go high (logic 1) and because "A" is connected to "4", the input 1 to NAND gate IC6a of IC6 will be high also. Input 2 of IC6a is already high because the initial state of a second counter IC8, output 3, is high.The third input 8 of NAND gate IC6a is at a logic low during the time the number is being entered and remains low until about half a second after the number has been entered, after which time C11 has discharged to a level below the threshold of the Schmitt NAND gate IC1b and the output IC1b/10 switches high, causing input 8 of IC6a to go high. The output 9 of IC6 a goes high and this is latched by input 4 of latch IC5a of IC5.

Output 2 of IC5a goes high. At the same time as IC1b/10 goes high, IC2b/8,10 go high causing the reset line IC7/15 to go high and reset the counter to zero. Output "4" on IC7/10 goes low. Also, IC8/ 14 goes high, advancing the count of counter IC8 by one, which makes IC8/3 go low and IC8/2 go high, thus enabling the second triple input AND gate IC6b at input 4 of IC6. IC6a/1,2 are now both low, but the existence of the number has been latched in IC5a. This process is repeated for the second and third numbers, connecting "B" and "C" to the selected outputs on IC7 via DIP switches 32 and 33 thus selecting the second and third numbers. These numbers can be selected by the use of wire links or switches.If the access code was to be "435", "A" would be linked via DIP switch 31 to "4", "B" would be linked via DIP switch 32 to "3", and "C" would be linked to "5" via DIP switch 33. The sequence of the access code is governed by the counter lC8/3,2,4 and IC6. The three latches IC5a to lC5c of IC5 all go high if the access code sequence was correct. This results in output 3 of NAND gate IC4a of IC4 going low, which resets the "SYSTEM SET" flip flop IC14a,b (Figure 3). This is the "standby" condition of the alarm system.

After the third number of the access code has been entered, IC8/7 ("REMOTE PANEL INIT. EX/ EN") goes high and is fed to input 5 of IC21a in Figure 3 to start the exit/entry timer (discussed hereinafter) if the three digit access code entered was incorrect. IC8/7 also takes the clock enable input IC8/13 high, thus preventing any further clocking of the counter IC8 until it is reset. To re-enter the access code - if incorrectly entered first time a Qone' must first be entered on the push button to reset the latches and counters: the reset operation is discussed hereinafter. After the Qone' has been entered, the access code can be entered. Attempting to enter numbers above "6" when the system is in the "active" condition (that is with IC4/ 3 high), causes the clock enable input IC7/13 to be taken high.This prevents any further clocking of the counter, thus inhibiting access to the control codes such as WALK TEST etc. This is achievecd via the triple input AND gate, 1C10a.

With the system in the "standby" condition, control codes such as WALK TEST, and CIRCUIT SHUNT can be entered. For WALK TEST, code seven is entered. IC4/12 is high because the system is in "standby" condition. With code seven entered, output "7" (IC7/6) goes high, IC4/13 goes high, making IC4/11 go low. IC2b/10 is prevented from going high after the pause period because IC2b/9 is now low. This condition is required because output "7" is required to remain high during WALK TEST until it is reset by entering a Qone' on the push button switch. Entering a Qone' on the push button switch (clearing WALK TEST) advances the count of IC7 making output "7" go low.

This causes IC4/11 to go high and enables IC2b.

After the pause period, IC7 is set to zero. Outputs "8" and "9" are used to reset and set the SHUNT CIRCUIT mode respectively. These outputs only remain high momentarily and are used to set or reset a "CIRCUIT SHUNTED" flip flop IC13a,b, which controls the SHUNT setting (shown in Figure 3 and explained later). It should be noted that the WALK TEST output from IC3c/3 only goes active after the pause period. It does not cause a transient output when passing the count of seven in order to enter codes "8" or "9".

To put the intruder alert system in the "active" condition, a Qone' is entered ("active" request command) on the push button switch. This causes output "1" (IC7/2) to go high, causing IC2/4 to go high momentarily after the pause period, which resets the counter IC8 to zero. IC8/7 is now low taking the clock enable input IC8/13 low also, thus reenabling the counter again. The components R38 and C14 serve to lengthen the reset pulse at IC2a/4.

This pulse at IC2a/4 will appear at output 4 of AND gate IC19a of IC19 and reset the latches IC5a,b,c causing IC4a/3 to go high I the "active" condition.

The latches IC5a,b,c will not reset, however, if IC19a/6 is low (FAULT-active), which will be the case if the "ANTI-FALSE ALARM" circuitry 30 in Figure 3 detects an alarm condition on any of the sensors before the code Qone' is entered on the push button. During the "ENTRY" mode, a "FAULT" signal output 10 on OR gate 15a of IC15, and forming input IC21/1 is overriden by a "SET" signal at input IC21/2. This is to allow the latches IC5a,b,c to be reset if an incorrect access code has been entered, regardless of whether any sensors are active. The reset pulse ("EXIT TIMER ON" pulse) of IC2a/4 is also used to trigger an "EXIT TIMER" circuit in Figure 3.When the "EXIT TIMER" is triggered by this pulse, AND gate input IC3b/9 is sent low by the timer output 010 before input 8 on IC3b is allowed to go high ("active" condition).

IC3b/8, which is driven by IC4a/3, is prevented from immediately going high by the components R37 and C12. This is to prevent the immediate generation of the "SET REQ" signal on IC3b/10. At the end of the time period (usually 30 seconds) IC3b/9 goes high and produces the "SET REQ" signal on lC3b/10. This signal QSETs' the "SYSTEM SET FLIP FLOP" IC14 in Figure 3. The system is now armed and any sensor that is activated on an un SHUNTED alarm generating circuit will cause an alarm.

Referring now to Figure 3, the Anti-False Alarm circuit 30 consists of IC12a (IC12/1,2,8,9) and IC13a (1C13/5,6,4). The "FAULT" signal outputted at It15/ 10 goes low if any of the detection circuits (except PA) are not healthy (i.e. active sensor) and is used to prevent the system from being put into the "active" condition by preventing the resetting of the latches iC5a,b,c (in Figure 2), which would result in a false alarm. However, a PA alarm must be reset by resetting the latches IC5a,b,c (Figure 2) and then entering the access code, which produces a pulse from the components R18, 19, C8 and D7 and resets the PA latch output IC5d/1. For this reason, "PA OVERRIDE" on IC15a/9 inhibits the "FAULT" signal and allows the latches IC5a,b,c (Figure 2) to be reset.The reset pulse for IC5d/1 comes from R19 via IC11a/8,10 and is also used to generate the access code acknowledge bleep on iC13d/2,3, IC10a/8,9 and clear the "CIRCUIT SHUNTED FLIP FLOP" IC13a at IC13/8.

The detection circuit consists of latches IC16a,b,c, which: (i) latch the state of any sensors going active during the system "active" condition; (ii) ignore the sensors during "standby" condition; or (iii) become "transparent" (i.e. outputs reflect inputs) during WALK TEST Mode. The PA latch IC5d/ 14 latches in "standby" or "active" mode but becomes "transparent" during WALK TEST. During WALK TEST, lC1 1 b/4,5 goes high enabling the detection latches of IC16, which are held in reset by the "SYSTEM SET FLIP FLOP" output IC14b/4. The PA latch IC5d/1,14 is held in reset by IC11a/9,10.

The outputs of the latches reflect the inputs, the results being passed to OR gates IC12b,c and used to drive the internal alarm circuitry only. During WALK TEST the external alarm is suppressed (except with PA) by IC11d/2 being taken low by output 11 of NAND gate IC4b in Figure 2. If the PA circuit is activated in WALK TEST the external as well as the internal alarm circuitry is activated due to IC11d/1 being taken high by IC5d/1 when the PA circuit is active. The exit/entry latch, 1C16b is not tested in WALK TEST. The "CIRCUIT SHUNTED" flip flop IC13a,b shunts out zone 2 (inputted to NOR gate IC20b) when IC13/10 is high, taking input 6 of NOR gate IC20a higetting or resetting SHUNT mode before entering WALK TEST mode. Exiting WALK TEST automatically clears the SHUNTED CIRCUIT mode.

The tamper loop input is usually at a logic one, whilst all other detection loop inputs are at a logic zero. Thus, if, through tampering with the system wiring, the tamper loop is open circuited or short circuited to any other connection, the detection loop conditions change, resulting in an alarm condition. Both inputs to NAND gate lC4c must remain high in order to maintain the tamper detection latch IC16d in a healthy (non-alarm) state.

To exit/entry circuit contains the "SYSTEM SET" flip flop IC14a,b which controls the state of the system, either "armed" (SET) or "standby". An oscillator consisting of NAND gate IC1c, resistor R30 and capacitor C9 and the counter IC17 form the timer circuit for exit and entry time delays. The timer is triggered by a pulse at the output 11 of NOR gate IC14c, which is caused by either inputs of NOR gate IC4d going high. Output "Q10" on IC17/14 goes low for the time period of exit or entry, allowing the input lC1c/6 to go high, which allows the oscillator to run at a frequency of about 14 Hz. The time period of the timer is adjustable by varing the frequency of the oscillator. The frequency can be adjusted by means of variable resistor R30.The various gates NAND gate IC4d, AND gate 1C10a, and OR gates IC15b,c I control the generation of an exit and bleeping entry signal, which is fed to a buzzer circuit 34 consisting of transistor TR1 (e.g. BC 327), resistors R20, 23 and diode D3 (e.g. IN914). The bleeping entry signal is derived from the "Q4" output on It17/7. lC2c allows the "EXIT" signal to trigger the counter IC17 only when the system is not "armed". The system power supply is now shown here, but basically it consists of a re-chargeable battery backed up by a mains power supply. The diode D3 is connected to the power supply regulator output and current flows through D3 to supply the buzzer circuit 34.

During a power failure, the battery (not shown) which is connected to the "+V" supply, supplies the system instead of the mains power supply and the buzzer circuit is supplied through the resistor R23 only. When the mains power supply is functioning the buzzer 3 operates at full volume, but during a power supply fault or blackout, it operates at less than half volume, thus indicating to the operator a supply fault. The resistor R23 determines the volume level of the buzzer during a mains supply failure. The buzzer used in this system is a piezo type with a self contained oscillator.

The alarm circuit 35 consists of an oscillator formed of NAND gate IC1d, variable resistor R29 and capacitor C10, a counter IC18 and gates to col lect the output conditions of the detection latches 1C16a,c/lC5d. This oscillator and counter/timer arrangement operates similarly to the "EXIT/ENTRY" timer circuit described above. When a detection latch output goes high, the counter is taken out of reset and is allowed to count pulses from the oscil later gate lC1d.Also, input 12 of AND gate IC19b goes high, resulting in internal and external alarm circuits 9,8 respectively being actuated by turning on transistors TR3,4,5,6. In the example shown, transistors TR5,3 are type BFY51 and TR6,4 are 2N3705.These alarm circuits remain on for twenty minutes, after which time output "014" (it18/3) goes high, which causes IC19b/13 to go low, which in turn switches off the alarms. The buzzers 3 in the remote panels continue to sound until the system is put into the "standby" condition due to IC10a/2 being low. The counter is reset by entering the access code, which resets the detection latches IC16a,c,d and IC5d, causing IC18/11 (counter reset) and IC10a/2 to go high. The counters IC17, IC18 may be ot the type CD4020.

A self activating bell (SAB) 38 contains its own re-chargeable battery (not shown in detail). The bell 38 sounds when the collector of TR3 of alarm circuit 8 goes low. It also sounds if the wiring running to the SAB is cut, by using its own battery.

Also, the source for the tamper loop, which runs along all the system wiring, if cut, results in the tamper detection latch being activated, which in turn causes an alarm condition, causing other bells in the system to ring.

Referring to Figure 4, the detection loop interface circuit illustrated therein is for interfacing all alarm sensors to the system. Each input line delays the sensor activation from reaching the system detection latches by between 0.2 and 0.8 of a second (break time). This is mainly to filter out electrical noise. The push button 2 is connected between pins Dl1 and Dli 0. Additional remote control push buttons are connected in parallel with the switch 2, which is a normally open contact type. All normally closed switches 41, 43, 46 (door contacts etc.) are wired in series as shown. All normally open switches 40,42 PA 44, pressure-mats 45 etc.

are wired in parallel as shown. All remote panel buzzers are wired in parallel across pins D118 and Dl16 in Figure 3. The tamper source from the SAB 38 in Figure 3 is wired to the tamper input pin QA' of tamper loop circuitry 39. All tamper loops are wired in series with all detection wiring a shown and the end of the loop should be connected to pin Dl12, which is the tamper detection input.

A 12 volt power supply is available at pin Dl17 and Dl24 for the purpose of powering detectors such as passive infra-reds etc. The power supply, pin Dl17 is fused and any attempt to short this supply would rupture the fuse F5 causing a tamper condition to occur on the positive end of capacitor C6, which would be detected by the detection latch in Figure 3, IC16d. The "stair pressure mat" 45 is connected between pins D113 and Dli 4.

Claims (8)

1. Equipment for producing an indication for use in disabling a system, the equipment comprising a switch and means for providing the said indication in response to detecting identity between an actual sequence of operations of the switch and a given sequence of operations of the switch.

2. In combination, equipment as claimed in claim 1, and a system comprising: sensing means; alarm means for producing an alarm signal in response to actuation of the sensing means; and signalling means for providing a signal in response to actuation of the sensing means.

3. A combination as claimed in claim 2, in which the system includes detection means for detecting whether the sensing means has been actuated, which detection means is responsive to actuation of the sensing means to produce an actuating signal for actuating the alarm means, and which includes means for using said indication to disable the system by inhibiting production of said actuating signal.

4. A combination as claimed in claim 2 or 3, in which the sensing means comprises a plurality of sensing devices disposed in first and second sensing zones, there being means for using said indication to disable the system by inhibiting production of said actuating signal in response to actuation of the sensing devices in the first zone only.

5. A combination as claimed in claim 2, 3 or 4 which comprises second detection means which are resposnive to said indication and which are capable of detecting an interference with the system to produce a control signal which is used for actuating the alarm means in response to such detection when said indication has not been provided and which is used for actuating the signalling means when said indication has been provided.

6. A combination as claimed in any of claims 2 to 5, which includes emergency circuitry which, when actuated, produces an actuating signal for actuating the alarm means whether or not the system has been disabled by said indication.

7. Equipment, for producing an indication for use in disabling a system, substantially as hereinbefore described with reference to, and as shown in Figure 1 of the accompanying drawings.

8. A combination comprising: a system and equipment for producing an indication for use in disabling the system, substantially as hereinbefore described with reference to, and as shown in, the accompanying drawings.