GB2149167A - Electrical circuit arrangements in fire alarms - Google Patents

Description

1 GB 2 149 167A 1

SPECIFICATION

Electrical circuit arrangements The invention relates to electrical circuit arrangements and more particularly to temperature-responsive electrical circuit arrangements. One such circuit arrangement to be described by way of example is for use with a tempera- ture detector of the type whose capability of accepting an electrical charge increases with temperature; the circuit arrangement determines the electrical state of the detector and thus can determine whether its temperature is excessive. Such a temperature detector may advantageously be of linear form so as to be mountable around an area whose temperature is to be monitored.

Various novel features of the invention will be apparent from the following description, given by way of example only, of electrical circuit arrangements embodying the invention, reference being made to the accompanying drawings in which:

Figure 1 is a block circuit diagram of one of 90 the circuit arrangements; and Figures 2 and 3 show waveforms occurring in the circuit of Fig. 1.

More specifically to be described below is an electrical circuit arrangement for monitoring the state of detecting means whose charge storage capability increases under predetermined conditions, comprising driving means operative to apply an alternately positive and negative test waveform to the detecting means, and digital testing means operative at predetermined time instants during positive and negative half cycles of the test samples are less negative than the threshold. The said second warning output may be an indication of a fault condition not being one of the said predetermined conditions. Advantage- ously, logic means is provided to inhibit the production of the said second warning output if the first warning output exists.

The testing means may include resetting means operative to take third samples of the waveform at predetermined time instants during a plurality of positive and negative half cycles thereof and to compare the magnitudes of a predetermined plurality of those samples with respective positive and negative thresh- olds whereby to produce a resetting signal, for cancelling the or each said warning output, if the magnitudes of the third samples of the positive half cycles are more positive than the positive threshold and the magnitudes of the third samples of the negative half cycles are more negative than the negative threshold.

Advantageously, the circuit arrangement includes means for integrating the positive half cycles of the said waveform so as to produce an output increasing towards a mean value at a rate dependent on the charge storage capability of the detecting means. Advantageously, means may be provided for producing a fault warning if the rate of change of the output from the integrator means exceeds a predetermined threshold.

Advantageously, the detecting means cornprises a longitudinal detector in the form of coaxial conductors separated by temperatureresponsive material which increases the charge storage capacity between the conductors as its temperature increases.

Advantageously, the testing means may include means for taking fourth samples of negative half cycles of the waveform and for comparing the magnitudes of a plurality of the fourth samples with a predetermined negative threshold and operative when the magnitudes of the fourth samples are less negative than the said threshold to produce a change signal, and means responsive to the change signal to shift the time instants at which the said first samples are taken so as to cause them to be taken at a predetermined relatively earlier instant in each said positive half cycle, whereby the shifted first samples can cause production of a said first warning output during the existence of a said predetermined condition which causes such distortion of the waveform as reduces the magnitude of first half of each positive half cycle compared with the magnitude during the second half thereof.

In a more specific sense, there will be described below a temperature responsive system, comprising a longitudinal temperature detector of the type whose electrical charge storage capability increases with increasing temperature, driving means operative to apply a symmetrical alternately positive and negative rectangular waveform to the detector, waveform to determine assymmetry of the waveform caused by an increase in its charge storage capabilities.

Advantageously, the digital testing means comprises means opertive to take first samples of the magnitude of the waveform applied to the detecting means at respective time instants during a predetermined plurality of positive half cycles and to compare the magnitude of each such first sample with a reference magnitude so as to produce a first warning output if the magnitudes of the said samples are more negative than the predetermined magnitude.

For example, the said predetermined conditions may include the condition of elevated temperature so that the said first warning output is indicative of elevated temperature or fire.

Advantageously, the testing means includes means for taking second samples of the wave form at predetermined time instants during negative half cycles thereof and for comparing the magnitudes of a predetermined plurality of the second samples with a predetermined threshold whereby to produce a second warn ing output when the magnitudes of those 130 2 GB2149167A 2 comparing means connected to compare the instantaneous magnitude of the waveform applied to the detector with a plurality of different and predetermined thresholds whereby to produce digital signals indicating whether the instantaneous magnitude of the waveform is more positive or more negative than the respective threshold, testing means operative in response to receipt of a predetermined plural- ity of said digital signals indicating that, during each of the predetermined plurality of positive half cycles of the said waveform, the instantaneous magnitude thereof is less than a first, relatively low positive, one of the said thresholds, whereby to produce a high temperature warning output, and fault sensing means operative in response to a predetermined plurality of consecutive said digital signals indicating that the instantaneous magnitude during each of a plurality of negative half cycles of the said waveform is less negative than a second, relatively high negative, one of the said thresholds, whereby to produce a fault warning output, and means preventing the fault warning output being produced during the existence of the high temperature warning output.

In the circuit arrangement now to be more specifically described, the linear temperature detector is shown at 10. The detector cornprises an elongated conductive sheath 12 of circular cross-section having an inner coaxial conductor 14. An insulting material separates the conductors 12 and 14 and is such that the capability of the detector to accept an electrical charge increases with temperature.

For example, the detector may be of the form as sold by the Applicants under the Trade Mark FIREWIRE.

In the electrical circuit arrangement to be described, one of the conductors of the detec tor 10 is held at ground potential and the other is subjected to a rectangular waveform which renders it alternately positive and nega- tive (swinging in this example between plus 5 110 and minus 5 volts). Thus, when the detector is at normal ambient temperature, the impedance of the detector is high and the voltage across the detector will swing between plus 5 and minus 5 volts in correspondence 115 with the applied waveform. However, as the temperature increases, the detector's resis tance will decrease and its capability of ac cepting charge will increase. The result will be that the voltage across the detector during the 120 positive half cycles will be reduced as com pared with that across the detector during the negative half cycles because the positive half cycles of the drive waveform are applied to the detector through a higher value resistor than are the negative half cycles. The greater reduction in voltage across the detector during the positive half cycles is partly due to the potential dividing effect of the higher value resistor but is also due to the increased cur- rent which flows because of the detector's enhanced charge accepting capabilities. This characteristic is detected by the circuit arrangement to be described so as to give a warning in response to elevated temperature of the detector. In the arrangement being described, this warning of elevated tempera ture is assumed to be a warning of a---fire condition.

A fault condition (such as caused by con tamination or mechanical damage to the de tector), which causes the electrical resistance between the conductors 12 and 14 to de crease, will have a different effect. The inequality between the decrease in voltage across the detector during positive half cycles and the decrease in that voltage during negative half cycles will not be so great because the detector's capability of accepting charge is not increased and therefore the increased volt drop effect of the charging current is not present. The circuit arrangement to be de scribed uses this effect to detect and signal such a fault.

As shown in Fig. 1, the circuit arrangement is (in this example) powered by a 28 volt DC supply on fines 16 and 18. A regulator and converter arrangement 20 produces a stabil ised DC output on lines 22 (0 volts), 24 (plus 5 volts) and 26 (minus 5 volts).

Line 22 is connected to conductor 12 of the detector 10 while lines 24 and 26 energise the plus 5 volt and minus 5 volt rails of a driver circuit 28 via connections not shown.

The circuit 28 comprises transistors 30 and 32 having their collectors connected to feed the conductor 12 of the detector 10 by respective resistors 34 and 36; these are the unequal resistors referred to above and may have resistances of 2700 and 430 ohms for example. The transistors are rendered conductive alternately, thus applying a rectangular waveform, swinging between plus 5 volts and minus 5 volts, to the conductor 14 of the detector 10 via line 38.

The transistors 30 and 32 are rendered conductive alternately by a 400 Hz signal from a divider and timing pulse encoder unit 38 on a line 40.

The unit 38 is driven by a 3.2 KHz oscillator 41 whose output frequency is divided down by 8 in the unit 38.

The waveform shown in Fig. 2A is thus the output waveform of the driver circuit 28 and is therefore the nominal waveform on line 42 (Fig. 1) when the detector 10 is cold so as to have effectively no charge storage capability.

As explained above, in order to monitor the electrical condition of the detector 10, to determine its charge storage capability and thus its temperature, it is necessary to monitor the voltage across the detector during each half cycle. A reference selector 44 provides a sequence of voltage references against which the voltage across the detector 10 during 3 GB2149167A 3 each half cycle is compared. The reference selector 44 comprises a potential divider of resistors connected between a plus 5 volt rail energised from line 24 and a minus 5 volt rail energised from line 26. The resistors are selected so as to provide tapped reference voltages of plus 3 volts, plus 1.35 volts, plus 0.5 volts, minus 2.35 volts, and minus 3.5 volts. The reference selector 44 is controlled in correspondence with the output of the divider and timing pulse encoder unit 38 via lines 70. The lines 70 therefore select each of the reference voltages in turn and the corresponding reference voltage is fed to a compar- ator 72 on a line 74.

Waveform 213 shows the sequence of the voltage references. During normal, fault-free, operation of the detector the selector 44 (Fig. 1) produces reference voltages of + 1.35 volts and + 0.5 volts alternately for successive positive half cycles of waveform 2A. However, if a fault should occur (as will be explained. in more detail below), a line 7 5 (Fig. 1) causes the selector 44 to select and produce the reference of + 3.0 volts instead of plus 1.35 vols (though during the intervening positive half cycles, the reference voltage continues to be plus 0.5 volts), all as shown in waveform 2B.

As shown by waveform 2B, during each negative half cycle of the drive waveform 2A, the selector 44 (Fig. 1) selects the reference voltage of minus 3.5 volts for the first half of the half cycle and minus 2.35 volts for the remainder of that half cycle. The reference voltages applied during the negative half cycles of the drive waveform are unaffected by any fault condition.

The comparator 72 carries out a compari- son of the voltage across the detector 10 in line 42 with the reference voltage waveform 213 on line 74. The output of comparator 72 is in the form of a binary signal, that is,---1 or -0-. Thus, if the voltage on line 42 is more negative than the voltage on line 74, comparator 72 produces a---1--- output on a line 78 but a -0- output is produced in the reverse condition. Line 78 is connected in common to four---smoother-units 80, 82, 84 and 86, each of which comprises a respective shift register whose outputs are fed into suit able logic circuitry driving an output latch.

Each shift register is clocked by a respective sequence of clock signals derived from the unit 38 via lines 70 and a timing pulse 120 generator 87.

As shown in Fig. 1, the smoother unit 80 comprises a shift register 88 having eight stages, the stage outputs being fed into a logic unit 90 driving a latch 92. The shift register 88 is clocked by clock pulses TP 1 A, these being received from the unit 87 on a line 93. As shown in waveform 2B, pulses TP1A occur during alternate half cycles of the reference waveform 2B. Therefore, each pulse 130 TP1A clocks into the shift register 88 a binary signal (on line 78) having a value depending on whether the voltage across the detector 10 is above or below the plus 0.5 volt reference.

As shown in waveform 2B, the pulses TP1 A normally occur three quarters of the way through each alternate positive half cycle. However, they can occur at a different position, one quarter of the way through each alternate half cycle, as shown dotted.

The smoother 88 therefore sets the latch 92 after eight consecutive pulses TP1 A (arranged over 16 positive half cycles) have occurred, at each of which the waveform from the detector is below 0.5 volts.

Smoother 82 is again in the form of a shift register 93, this time having four stages which are connected to logic 94. The smoother 82 is clocked by clock pulses TP1 B received from the unit 87. As shown in Fig. 2, the pulses TP1 B occur during alternate positive half cycles, the half cycles during which the pulses TP 1 A do not occur. Each pulse TP1 B occurs at a point three quarters of the way through its respective half cycle. Each pulse TP1 B therefore tests whether or not the waveform from the detector is above either plus 1.35 volts or plus 3.00 volts depending on the particular reference level during the half cycle. As was explained above, under certain conditions the selector 44 alters the reference level on line 74 during alternate half cycles from plus 1.35 volts to plus 3.0 volts and these alternate half cycles are synchron- ised with the pulses TP 1 B. If, at each occurrence of a pulse TP 1 B, the comparator 72 determines that the waveform from the detector 10 is more positive than the reference waveform on line 74, it produces a -0- output which is clocked into the register 93 by the pulse TP 'I B. When four such consecutive outputs are clocked into the register, the logic unit 94 produces a signal RE on a line 96 which is fed to an AND gate 98 connected to a reset line 100.

Smoother 84 comprises a shift register 101 having four stages which are all connected to logic 102. Register 10 1 is closed by pulses TP2 from the unit 87 and as shown in Fig. 2, these occur during each negative half cycle of the drive waveform. Each occurs one quarter of the way throuCh its respective half cycle and thus occurs when the reference level on line 74 is minus 3.5 volts. If comparator 72 determines that the waveform from the detector 10 is more negative than minus 3.5 volts, line 78 will carry a---1---when each pulse TP2 occurs and this will be clocked into the register 10 1. If four such consecutive binary sig- nals are produced, the logic 102 produces a latched output CH on a line 104. If the detector waveform is not more negative than minus 3.5 volts when each pulse TP2 occurs, binary -0- signals will be produced on line 78 and the logic 102 will be latched into a 4 GB2149167A 4 state in which it produces a signal CH on a line 106. As shown in Fig. 1, the signals CR are passed through the gate 98 onto the reset fine 100, while the signals CH are passed to the unit 87 where they shift the time of occurrence of the pulses TP1A to the dotted position shown in waveform 2A.

Smoother 86 is in the form of a four stage shift register 107 whose stages are connected to logic 108 which controls a latch 110. The shift register 107 is clocked by pulses TP3 from the unit 87 and as shown in waveform 2A these occur during every negative half cycle of the drive waveform 2A, each one occurring at three quarters of the way through the half cycle. Thus, each pulse TP3 occurs when the reference level on line 74 is at minus 2.2 volts. If the waveform from the detector is more negative than minus 2.2 volts when each pulse TP3 occurs, a binary ---1---will be clocked into the shift register 107. After four such consecutive binary si97 nals, the logic 108 will produce a signal PA.

If the waveform from the detector 10 is not more negative than the reference level on line 74 when each pulse TP3 occurs, a binary signals will cause logic 108 to produce a signal FA which will latch the latch 110 into a ---fault-state.

Latches 92 and 110 are connected to be reset by the reset line 100.

When set, latch 92 produces a fire warning signal on line 112. Similarly, when set, the latch 110 produces a fault warning signal on 100 a line 114.

The operation of the circuit arrangement as so far described will now be considered.

The first condition to be considered will be when the detector 10 is cold or at normal ambient temperature and with no fault. The waveform produced by the detector, that is, the waveform on line 42, can therefore be considered to be as shown in Fig. 2A, that is, substantially unchanged from the drive wave- 110 form. Therefore, during each pulse TP1A, the comparator 72 will produce a binary -0 signal and the latch 90 will therefore not be set and no signal will be produced on line 112. During each pulse TP 1 B, the comparator 115 72 will also be producing a binary -0- signal because the waveform from the detector will be more positive than plus 1.35 or plus 3.00 volts. After four such binary signals, logic 94 will therefore be set to produce a signal RE on 120 the line 96 which will be fed to AND gate 98. During each pulse TP2, comparator 72 will determine that the waveform from the detector is more negative than the reference level and will produce a binary---1 -. Four such binary signals will thus cause the latch 102 to produce the signal N and this will be fed to gate 98. Line 100 will therefore be energised to carry a RESET level.

During each pulse TP3, the comparator 72 130 will determine that the waveform from the detector is more negative than the reference level and will again produce a---1---output. Four such binary signals will cause the logic 108 to produce a signal PA, and the latch 110 will therefore not be set.

The effect, therefore, is that neither a fire warning nor a fault warning is produced. The RESET level on line 100 therefore has no effect because the latches 92 and 110 are already in the reset state.

It will now be assumed that a fire or other overheat occurs.

As explained above, this will increase the charge acceptance capability of the detector 10. The result will be to cause a significant reduction in the level of the detector waveform on line 42, Fig. 1, during each positive half cycle, while making relatively insignificant change in the level during each negative half cycle. The type of change which might occur is shown in waveform 2C.

Therefore, the comparator 72 will be producing a binary---1---output when each pulse TP1A occurs. After eight such signals (16 positive half cycles), the latch 92 will be set and will produce a fire warning signal on line 112.

During each pulse TP 'I B, the comparator 72 will also be producing a---1---output, but because of the inverter 79, latch 94 will not be set and no signal RE will be produced.

As is shown in waveform 2C, it is assumed that the output waveform from the detector remains more negative than minus 3.5 volts during each negative half cycle. Therefore, during each pulse TP2, a binary---1--signal will be produced by the comparator 72. After four such signals have been received, latch 102 will produce a CH output, rather than a CH output. However, the CH output will be blocked by the AND gate 98. Line 106 will not be energised.

During each pulse TP3, the comparator 72 will also produce a binary---1--output and therefore latch 110 will not be set into the FAULT condition and no fault warning will be produced on line 114.

If the fire or overheat condition should disappear, the waveform from the detector 10 will change back towards that shown in Fig. 2A. If the level of the detector waveform during positive half cycles remains above plus 1. 35 volts for four consecutive positive half cycles, the corresponding pulses TP 'I B will cause the inverter 7 9 to clock binary---1--signals into the register 93 and latch 94 will thus produce a RE signal on line 96 to the AND gate 98. Provided that the waveform from the detector is also more negative than minus 3.5 volts during four consecutive half cycles, the corresponding pulses TP2 will clock binary--- 1---signals into the register 10 1 and the logic 102 will thus produce a N output to AND gate 98. Line 100 will thus GB2149167A 5 carry a RESET signal which will reset the latch 92 (latch 110 already being in the reset state). The fire signal on line 112 will thus be removed.

If the detector 10 should be subjected to a 70 very fierce overheat or fire, so that its temper ature rises very rapidly, the waveform on line 128 may (at least initially) become as shown in Fig. 2D. This shows that the voltage three quarters of the way through each positive half 75 cycle has not dropped below plus 0.5 volts.

Therefore, the comparator 72 will not be producing binary---1---outputs when pulses TP 1 A occur three quarters of the way through each alternate positive half cycle. Latch 92 would therefore not be set into the FIRE state and no fire warning would be produced.

Register 10 1 deals with this condition. As is shown in waveform 2B, the voltage of the detector waveform during negative half cycles 85 is more positive than minus 3.5 volts. Each pulse TP2 will therefore cause a binary -0 to be clocked into the register and logic 102 will therefore produce a CH output on line 106. This has the effect of causing the unit 87 to shift the positions of the pulses TP1A to the positions shown dotted in waveform 2A.

At each dotted position of pulse TP 1 A, the waveform shown in Fig. 21) is more negative than the reference level of 0.5 volts, and thus 95 eight pulses TP1A (in the dotted position) will cause eight binary---1---signals to be clocked in to register 88 so as to set the latch 92 into the FIRE state, producig a fire warning on line 112.

If the detector becomes contaminated or mechanically damaged, for example, in such a way that the resistance between the conductors 12 and 14 becomes reduced, this will have the effect of reducing the voltage across the detector during both positive and negative half cycles. Fig. 2E shows the form which the waveform from the detector can take under such conditions. In waveform 2E, it will be noted that the voltage remains above 0.5 volts during positive half cycles and therefore the latch 92 will not be set into the FIRE state and no fire warning will be produced. During positive half cycles, however, the voltage of the waveform 2E is more negative than plus 1.35 volts so logic 94 is not set into the RE state.

During negative half cycles the detector waveform is less negative than minus 3.5 volts, so the logic 10 1 will produce a CH output on line 106 after four such half cycles. However, the resultapt shifting of the pulses TP 1 A to the dotted position shown in waveform 2A will not have any effect.

During its negative half cycles, waveform 2E is less negative than minus 2.2 volts and therefore binary---1---signals will be fed into register 86, and four such binary signals will cause the latch 110 to be set into the FAULT condition so as to produce a fault warning on line 114.

The fault warning on line 114 is also fed via line 75 to the selector 44 and has the effect of changing the reference level applied to the comparator 72 on line 74 during alternate positive half cycles from plus 1.35 volts to plus 3.00 volts. Therefore, when the fault condition disappears, register 93 will not set the logic 94 into the RE state until the waveform from the detector 10 has been more positive than plus 3 volts for four pulses TP 'I B. Provided that the waveform from the detector 10 is also more negative than minus 3.5 volts, register 101 will also set the logic 102 to produce a N output. AND gate 98 will therefore produce a RESET signal on line 100 which will reset the latch 110 and remove the fault warning from line 114. This will also switch the reference level during alternate half cycles from plus 3.00 volts back to plus 1.35 volts.

A line 122 interconnects the fault warning line 112 with an inhibit input of latch 110. Therefore, if latch 92 is set into the FIRE condition, as a result of the waveform from the detector being more negative than plus 0.5 volts during eight alternate positive half cyles, not only will a fire warning be produced on line 112 but latch 110 will be prevented from being switched into the FAULT state even if the detector waveform has become less negative than minus 2.2 vols during four pulses TP3. Similarly a line 123 prevents a fire warning, if latch 110 is in the---fault- state.

As shown in Fig. 1, an output is taken from the collector of transistor 32 on a line 128 and this is fed into an integrator 130 whose output therefore represents the inverse inte- gral of the positive half of the waveform from the detector 10. Fig. 3 shows in full line the normal shape of the waveform produced by the integrator 130, the horizontal axis representing either time or temperature provided that the temperature is rising slowly. However, if the detector is subjected to a very fierce fire, it is found that the output of integrator 130 changes to the dotted form in Fig. 3, that is, its rate of rise increases very rapidly. The output of integrator 130 can therefore be used to provide a supplementary indication of the state of the detector 10. For example, this output can be fed on a line 132 to a suitable indicator. In other words, the indication given by the indicator indicates the ---trend-detected by the detector 10.

If a fault occurs on the detector, such as due to contamination or damage and which has the effect of reducing the resistance be- tween the conductors 12 and 14, the output of the integrator 130 will rise even more rapidly. A slope unit 136 detects such a condition and produces a fault indication on a line 138. This is fed to the register 107 and immediately switches the register to produce 6 GB2149167A 6 an output which sets latch 110 into the FAULT condition, thus providing a back-up to the fault monitoring provided by the pulses TP3.

A reset unit 140 prduces a reset signal on a 70 line 142 for resetting the various logic units of the system when the power is first switched on.

It will be appreciated that the lines intercon- necting the power supply to the various units of the system have been omitted for clarity. It will be understood that various modifications can be made to the

circuit arrangement described without departing from the scope of the invention. It will also be appreciated that provision may be made for carrying out various tests on the circuit arrangement and on the detector so as, for example, to simulate fire or fault conditions and to check that an appropriate warning output is produced under such conditions.

Claims (23)

1. An electrical circuit arrangement for monitoring the state of detecting means whose charge storage capability increases under predetermined conditions, comprising driving means operative to apply an afternately positive and negative test waveform to the detecting means, and digital testing means operative at predetermined time instants during positive and negative half cycles of the test waveform to determine assymmetry of the waveform caused by an increase in the charge storage capabilities of the detecting means.

2. An arrangement according to claim 1, in which the digital testing means comprises means operative to take first samples of the magnitude of the waveform applied to the detecting means at respective time instants during a predetermined plurality of positive half cycles and to compare the magnitude of each such first sample with a reference magnitude so as to produce a first warning output if the magnitudes of the said samples are more negative than the predetermined magnitude.

3 ' An arrangement according to claim 1 or 2, in which the said predetermined condi- tions include the condition of elevated temperature so that the said first warning output is indicative of elevated temperature or fire.

4. An arrangement according to any preceding claim, in which the testing means includes means for taking second samples of the waveform at predetermined time instants during negative half cycles thereof and for comparing the magnitudes of a predetermined plurality of the second samples with a predet- ermined threshold whereby to produce a second warning output when the magnitudes of those samples are less negative than the threshold.

5. An arrangement according to claim 4, in which the said second warning output is an 130 indication of a fault condition not being one of the said predetermined conditions.

6. An arrangement according to claim 4 or 5, including logic means to inhibit the production of the said second warning output if the first warning output exists.

7. An arrangement according to any preceding claim, in which the testing means includes resetting means operative to take third samples of the waveform at predetermined time instants during a plurality of positive and negative half cycles thereof and to compare the magnitudes of a predetermined plurality of those samples with respective positive and negative thresholds whereby to produce a resetting signal, for cancelling the or each said warning output, if the magnitudes of the third samples of the positive half cycles are more positive than the positive threshold and the magnitudes of the third samples of the negative half cycles are more negative than the negative threshold.

8. An arrangement according to any preceding claim, including integrator means for integrating the positive half cycles of the said waveform so as to produce an output increas ing towards a mean value at a rate dependent on the charge storage capability of the detect ing means,

9. An arrangement according to claim 8, including means for producing a fault warning if the rate of change of the output from the integrator means exceeds a predetermined threshold.

10. An arrangement according to any pre ceding claim, in which the detecting means comprises a longitudinal detector in the form of coaxial conductors separated by tempera ture-responsive material which increases the charge storage capacity between the conductors as its temperature increases.

11. An arrangement according to any preceding claim, in which the testing means includes means for taking fourth samples of negative half cycles of the waveform and for comparing the magnitudes of a plurality of the fourth samples with a predetermined negative threshold and operative when the magnitudes of the fourth samples are less negative than the said threshold to produce a change signal, and means responsive to the change signal to shift the time instants at which the said first samples are taken so as to cause them to be taken at a predetermined relatively earlier instant in each said positive half cycle, whereby the shifted first samples can cause production of a said first warning output during the existence of a said predetermined condition which causes such distortion of the waveform as reduces the magnitude of first half of each positive half cycle compared with the magnitude during the second half thereof.

12. A temperature responsive system, comprising a longitudinal temperature detector of the type whose electrical charge storage 7 GB2149167A 7 capability increases with increasing tempera ture, driving means operative to apply a sym metrical alternately positive and negative rec tangular waveform to the detector, comparing means connected to compare the instantane- 70 ous magnitude of the waveform applied to the detector with a plurality of different and pre determined thresholds whereby to produce digital signals indicating whether the instanta neous magnitude of the waveform is more positive or more negative than the respective threshold, testing means operative in response to receipt of a predetermined plurality of said digital signals indicating that, during each of the predetermined plurality of positive half cycles of the said waveform, the instantane ous magnitude thereof is less than a first, relatively low positive, one of the said thresh olds, whereby to produce a high temperature warning output, fault sensing means operative 85 in response to a predetermined plurality of consecutive said digital signals indicating that the instantaneous magnitude during each of a plurality of negative half cycles of the said waveform is less negative than a second, relatively high negative, one of the said thresholds, whereby to produce a fault warn ing output, and means preventing the fault warning output being produced during the existence of the high temperature warning output.

13. A method of sensing temperature in crease using a temperature detector in the form of coaxial conductors separated by tem perature-responsive material which increases the charge storage capacity between the con ductors as its temperature increases, compris ing the steps of applying an alternately posi tive and negative test waveform to the detec tor, and sampling the test waveform at predet ermined time instants during positive and negative half cycles thereof to determine as symmetry of the waveform caused by an increase in its charge storage capacity of the detector.

14. A method according to claim 13, in which the sampling step comprises the step of taking first samples of the magnitude of the test waveform at respective timer instants dur ing a predetermined plurality of positive half cycles, and the step of comparing the magni tude of each such first sample with a refer ence magnitude so as to produce a first warning output if the magnitudes of the said samples are more negative than the predeter mined magnitude.

15. A method according to claim 14, in cludes the steps of taking second samples of the waveform at predetermined time instants during negative half cycles thereof and com paring the magnitudes of a predetermined plurality of the second samples with a predet ermined threshold whereby to produce a sec ond warning output when the magnitudes of those samples are less negative than the threshold.

16. A method according to claim 15, in which the said second warning output is an indication of a fault condition.

17. A method according to claim 15 or 16, including the step of inhibiting the production of the said second warning output if the first warning output exists.

18. A method according to any one of claims 13 to 17, including the step of taking third samples of the waveform at predetermined time instants during a plurality of positive and negative half cycles thereof and comparing the magnitudes of a predetermined plurality of those samples with respective positive and negative thresholds whereby to produce a resetting signal, for cancelling the or each said warning output, if the magnitudes of the third samples of the positive half cycles are more positive than the positive threshold and the magnitudes of the third samples of the negative half cycles are more negative than the negative threshold.

19. A method according to any one of claims 13 to 18, including the step of integrating the positive half cycles of the said waveform so as to produce an output increasing towards a mean value at a rate dependent on the charge storage capacity of the detector.

20. A method according to claim 20, including the step of producing a fault warning if the rate of change of the output from the integrator means exceeds a predetermined threshold.

21. A method according to any one of claims 13 to 20, including the steps of taking fourth samples of negative half cycles of the waveform, comparing the magnitudes of a plurality of the fourth samples with a predeter- mined negative threshold and operative when the magnitudes of the fourth samples are less negative than the said threshold to produce a change signal, and shifting the time instants at which the said first samples are taken, in response to the change signal, so as to cause them to be taken at a predetermined relatively earlier instant in each said positive half cycle, whereby the shifted first samples can cause production of a said first warning output dur- ing the existence of a said predetermined condition which causes such distortion of the waveform as reduces the magnitude of first half of each positive half cycle compared with the magnitude during the second half thereof.

22. A temperature responsive system, substantially as described with reference to the accompanying drawings.

23. A method of sensing temperature increase, substantially as described with reference to the accompanying drawings.

Printed in the United Kingdom for Her Majesty's Stationery Office, Dd 8818935, 1985. 4235. Published at The Patent Office. 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained-