GB2148648A - Time disparity discriminator; correlation - Google Patents
Time disparity discriminator; correlation Download PDFInfo
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- GB2148648A GB2148648A GB08328428A GB8328428A GB2148648A GB 2148648 A GB2148648 A GB 2148648A GB 08328428 A GB08328428 A GB 08328428A GB 8328428 A GB8328428 A GB 8328428A GB 2148648 A GB2148648 A GB 2148648A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
- H04N13/10—Processing, recording or transmission of stereoscopic or multi-view image signals
Abstract
A time disparity discriminator for a digital scanning video system wherein first and second digital video signals are both delayed by one video clock pulse, each undelayed video signal is then multiplied by the other delayed video signal and the two products are then compared; the discriminator outputting a two state time displacement signal, the states of which depend upon whichever of the two products is the greater. This state depends on which signal leads and which lags. <IMAGE>
Description
SPECIFICATION
A time disparity discriminator
This invention relates to a time disparity discriminator for a digital scanning video system for the correlative synchronisation of two similar but not identical digital signal waveforms derived from a pair of video cameras scanning a common scene from different viewpoints.
The synchronisation process is called stereo image-correlation and it enables the x y z coordinance of all points in the scene to be determined. The method was developed originally to automate the measurement of terrain shape with two video cameras scanning a stereo pair of aerial photographs (see for example United States Patent specification No.3621 326). A new application of stereo image-correlation is in 3D vision and space perception for industrial robots, i.e. artificial stereopsis.
Stereo image-correlation is greatly simplified when the images are co-planar and when both images are scanned in a direction precisely parallel to a line joining the centres of the camera lenses. The process is hindered more fundamentally by the complex differences in shape, of the left and right images, introduced by the different viewpoints of the two cameras. As a result correlation and matching over an extended image area is not possible unless the two images are transformed into congruence during the process. Such an image transformation system requires a disparity discriminator to sense the shape differences or errors in terms of time dependent error signals.
It is an object of the present invention to produce a time disparity discriminator that employs a minimum of components to enable error signals of sufficient accuracy to be produced at the requisite "real-time" speed.
According to the present invention a time disparity discriminator for a digital scanning video system comprises:
(i) A first input port for left-handed digital video signals;
(ii) A second input port for right-handed digital video signals;
(iii) First delay means connected to said first input port to receive and delay said left video signals by a video clock pulse;
(iv) Second delay means connected to said second input port to receive and delay said right video signals by said video clock pulse;
(v) First multiplier means connected to said first input port and to said second delay means to multiply said left video signal by the delayed right video signal;
(vi) Second multiplier means connected to said second input port and to said first delay means to multiply said right video signal by the delayed left video signal; and
(vii) Comparator means connected to said first and to said second multiplier means and arranged to output a two state time displacement signal, the states of which depend upon whichever output of said first and second multiplier means is the greater.
In a first embodiment of the invention, third multiplier means are connected to said first input port and said second input port to multiply said left video signal by said right video signal and comparator tree means are connected to said first, said second and said third multiplier means and are arranged to output a three state time disparity signal, the states of which are dependent upon whichever of the multiplier outputs is the greatest.
In a second embodiment of the invention one or more additional delay means are serially connected to said first and second delay means, an equivalent number of additional multiplier means are connected between respective additional left and right delay means to additionally multiply the one video signal by the or each additionally delayed other video signal; and comparator tree means are connected to all the multiplier means and are arranged to output a time displacement signal, the number of states of which equal the number of multiplier means and which states are dependent upon whichever of the multiplier outputs is the greatest.
Each of the above embodiments is only concerned with the comparison of individual pixels in the left and right scanned images. A further two embodiments of the invention extend the time disparity discriminator to the comparison of linear and area pixel groups.
Thus according to a third embodiment of the invention separate serial integrator means are connected between each multiplier means and said comparator means or said comparator tree means; whereby the output time displacement signal is the result of the comparison of linear pixel groups, the number of pixels in which is detemined by the integration period of said serial integrator means.
In a fourth embodiment of the invention separate lateral integrator means are connected between each serial integrator means and said comparator means or said comparator tree means; whereby the output time displacement signal is the result of the comparison of area pixel groups, wherein the number of pixel line groups is determined by the integration period of said lateral integrator means.
It is also a known technique from photogrammetry for correlation to proceed iteratively because a partial shape correction of errors extending over relatively large areas of the images leads to an improvement in the discrimination of errors extending over smaller areas. Iterative correlation is carried out by dividing the video spectrum into frequency bands and correlating the bands separately starting with the lowest frequency band and proceeding step by step to the highest frequency band. The bands should have substantially equal frequency ratios, and should cover the entire signal spectrum in a contiguous set.
In general the lower the frequency ratio, the greater the number of bands and the better the discrimination. A band frequency ratio of 2:1 seems close to optimum and is a convenient ratio for digital systems using binary arithmetic.
The precision of each band is proportional to its centre frequency so that the highest frequency band sets the system accuracy.
Unfortunately the maximum error that can be accommodated by a band (pull-in range) is inversely proportional to its centre frequency.
In general a band will not function if the images are not pre-matched to the precision of the next lower band. It is therefore necessary to the continuity of the process that each band in turn makes its contribution to image correlation and transformation. It is an extension of the present invention to produce a band combining network for iterative correlation using a series of contiguous frequency bands and the digital signals from discriminators in accordance with the invention arranged in each frequency band.
According to this aspect of the present invention a band combining network to combine the time displacement signals produced by a series of discriminators comprises:
(i) First separator means are connected to said first input port to separate the spectrum of said left video signal into a series of contiguous frequency bands,
(ii) Second separator means are connected to said second input port to separate the spectrum of said right video signal into said series of contiguous frequency bands,
(iii) A separate discriminator is connected to receive the components of said left and right video signals appearing in a respective one of said frequency bands, and
(iv) A band combining network is connected to each discriminator and comprises::
(a) Switching means, one input of which is connected to the discriminator for the highest frequency band and the other input of which is fed a zero signal,
(b) Zero decoder means connected to the discriminator for the next lower frequency band and connected to control said switching means so that only a zero signal from the next lower discriminator will switch the signal from the highest discriminator to the output of said switching means,
(c) Dividing means connected to the output of said switching means to divide the output thereof in accordance with the ratio of said frequencies of the frequency bands,
(d) Adder means, one input of which is connected to said first divider means and the other input of which is connected to said discriminator for the next lower frequency band, and
(e) Successive switching means,zero decoder means, divider means and adder means connected as above to the discriminator for each remaining frequency band in said series of frequency bands; whereby the switching means will disable frequency bands higher than one delivering a time displacement signal.
The above and other features of the present invention are illustrated in the Drawings wherein:
Fig. 1 shows one form of time disparity discriminator in accordance with the invention,
Fig. 2 shows a second form of a time disparity discriminator in accordance with the invention and
Fig. 3 shows a band combining network in accordance with an extension to the present invention.
As shown by Fig. 1 filtered or otherwise separated digital video signals having positive and negative values are input, left video signals to input port 1 and right video signals to input port 2. A first delay D1, clocked by the video clock Cv is connected to an input port 1 by line 3 and is arranged to delay left video signals by one pulse. The delay is a D type register. Similarly a second delay D2 is connected by line 4 to input port 2 and delays right video signals byone Cv pulse.
Three multipliers M1, M2 and M3 are provided, multiplier M1 being connected to input port 1 by line 5 and to the output of delay D2 by line 6, multiplier M2 being connected to input port 2 by line 7 and to the output of delay 1 by line 8 and multiplier M3 being connected to input port 1 by line 9 and to input port 2 by line 10. Multiplier M1 thus multiplies left video signals by right video signals that have been delayed by one clock pulse; similarly multiplier M2 multiplies right video signals by left video signals that have been delayed by one pulse and multiplier M3 multiplies undelayed left video signals by undelayed right video signals.
A serial integrator S1 is connected to the ouput of multiplier M1 by line 11, the second serial integrator S2 is connected to the output of multiplier M2 by line 12 and a third serial integrator S3 is connected to the output of multiplier M3 by line 1 3. Each integrator is clocked by video clock pulses Cv and is reset by line pulses R1. The serial integrators, are block integrators that will integrate the incoming signals for a given number of'pulses, set by the value of line reset R1; i.e. the serial integrators add successive pulses (representing successive linear adjacent pixels) for the number set by R1 and then outputs the sum of the added pulses. At this juncture, the serial integrator output having the highest numeric value (being a linear integration of pulses input thereto for the period set by the line reset value) will indicate the following:
If the output on line 14 is numerically the greater there will be a time lag of the left video signal with respect to the right video signal and if the output of line 1 5 is numerically greater there will be a time lag of the right video signal with respect to the left video signal line and if the output of line 1 6 is numerically the greater there will be no disparity between the left and right video signals i.e. they will be correlated.The possibility for these values are indicated by minus 1 for the output on line 14, zero for the output on line 1 6 and plus 1 for the output on line 1 5.
Typical value for line reset would be four clock pulses Cv although it could possibly be eight or two whichever is sufficient to produce statistically meaningful values at the output of lateral integrators to be described.
Three lateral integrators L1, L2 and L3 are connected to the output of serial integrators S1 S2 and S3 respectively by lines 14, 15 and 1 6. These lateral integrators integrate at right angles to the values of the serial integrators, they are clocked by line pulses Cv and are reset by group pulses Rg. The lateral integrators include delay lines which enable pixels appearing one below the other in adjacent lines of the scanned raster to be integrated, this combined with the linear integration of the preceding serial integrators means that areas of pixels are being integrated and the signals output by the lateral integrators are the sum of a number of lines of pixels set by the value of Rg multiplied by the number of pixels in a line set by the value of R1.
A comparison tree is connected to the outputs of the three integrators to determine which integrator is outputting the greatest signal and produce a three state time disparity signal and the value of the greatest signal which value forms a quality of correlation Qc.
A first comparator C1 is connected to the output of integrators L2 and L3 by lines 1 7 and 18 respectively. The output of comparator C1 is connected to the seiect input of a first multiplexer MX1 by line 19. The signal inputs to multiplexer MX1 are connected to integrators L2 and L3 by lines 20 and 21 respectively. The action of comparator C1 is to detem ine which of the outputs of integrators L2 and L3 is numerically the greater and to switch the multiplexer to output the greater integrator signal on line 22.Also the signal from the comparator on line 1 indicates whether the greater signal is on the plus 1 or the zero channel and forms the least significant bit of the output signal dt from the discriminator on line 23; the output signal dt being in twos complement binary arithmetic.
A second comparator C2 is connected by line 24 to the output of multiplexer 1 and by line 25 to the output of lateral integrator L1. The output of comparator C2 is connected by line 26 to the switching input of a second multiplexer MX2, the signal inputs of which are respectively connected to the output of multiplexer MX1 by line 22 and to the output of lateral integrator L1 by line 27. Again comparator C2 will determine whether or not the signal from MX1 or the signal from L1 is numerically the greater and will switch MX2 to output the greater signal on line 28. Thus the signal output from the comparison tree on line 28 is the greatest amongst the three signals appearing from the lateral integrators
L1, L2 and L3 and fom s the quality of correlation signal Qc from the discriminator.
The signal from comparator C2 is also output on line 29 which forms the other line for the twos complement output signal dt from the discriminator, and a signal on which will represent the output from integrator L1 being the greatest of the three integrator outputs.
The time disparity discriminator and integrator shown by Fig. 2 is similar to that shown by Fig. 1 and similar parts and components have been given the identical reference numbers. However, this discriminator works with boolean input signals whereas the discriminator of Fig. 1 works with binary twos complement input signals. Only the sign bits of the multibit filtered video signals are used by the time disparity discriminator of Fig. 2. Delays D1 and D2 are simple one bit flipflops and multipliers are fom ed by exclusive NOR gates
XNR 1 and XNR 2 and XNR 3. The output signals from the NOR gates will still be one bit.Each serial integrator S1 or S2 or S3 is a running average integrator and is shown to consist of three delays and three adders in the series delays being clocked by the video pulses Cv and the adders being fed from the preceding delay and, in each case, from the output of the appropriate XNR gate on line 11, 12 or 13. The signal from the output of each integrator on lines 14, 1 5 and 1 6 respectively will be the running average sum of the preceding four pulses and will each be a three bit binary signal.The three lateral integrators L1, L2 and L3 are each comprised of three shift registers and three adders in series, the adders being input by the preceding shift register and also by the serial integrator output signal on lines 14, 1 5 or 1 6 respectively.
The value of the delay introduced by the shift registers for the lateral integrators of any one discriminator will depend on the frequency band in which that discriminator lies. For example in the highest frequency band dealing with a single pixel the delay would be one line of 256 pixels; for the next frequency band the delay would be one line of 1 28 elements (1 element = 2 pixels); for the next frequency band one line of 64 elements (4 pixels); for the next frequency band one line of 32 elements (8 pixels) and for the next frequency band one line of 1 6 elements (16 pixels); assuming five frequency bands at 2:1 centre frequency ratio. Five bits will now be required to accommodate the signals output from each lateral integrator.Again the output signal dt from the comparator tree will be twos complement binary; the plus one and zero channel signals being present on the least significant bit line 23 and the minus one channel signal being present on the sign line 29.
The time disparity discriminator together with its associated serial and lateral integrators and the output comparison tree for an individual band shown by Fig. 2 can be of such simplicity because of the narrowness of the band frequency ratio (2:1) as a result of which very little image data is ignored even in a boolean correlation process.
Fig. 3 shows a band combining network consisting of four input ports 31, 32, 33 and 34 receiving twos complement signals from four frequency bands 1, 2, 3 and 4. The signals present on band 1 will be for states minus one, zero, plus one. The signals present for band 2 will be the same but with weighting to represent, minus two, zero, plus two; for band 3 weighted to represent minus four, zero, plus four and for band 4 weighted to represent minus eight, zero, plus eight.
Input port 31 is connected by line 35 to signal input port B of a multiplexer MX3, a zero signal being fed in on line 36 to the other signal input port A of the multiplexer. A zero decoder 37 such as a NOR gate is connected to receive band 2 signals from input port 32 on line 38 and is connected to operate the switch input of multiplexer MX3 on line 39. The output from multiplexer MX3 on line 40 is connected to a divider 41, in this case dividing by two i.e. the ratio of the centre frequencies of the bands. The output of the divider 41 is connected to one input of a first adder Al, the other input to which is also connected to receive band 2 signals from input port 32 on line 42. The output from adder Al is connected to a first signal input port B of a further multiplexer MX4 in the same manner as described above.A zero signal is fed to the other signal input of multiplexer MX4 on line 44, zero is decoded from the band 3 signal by zero decoder 45 connected by line 46 to the input port 33 and controlling the switch input of the multiplexer
MX4 on line 47. The output of multiplexer
MX4 on line 48 goes to another divider 49, itself connected to one input of a second adder A2 to the other input of which band 3 signals present at input port 33 are fed on line 50. The output from adder A2 goes to signal input port B of another multiplexer
MX5 via line 51. A zero signal is input to signal input port A of multiplexer MX5 by line 52. Another zero decoder 53 is connected to receive band 4 signals present at input port 34 by line 54 and controls the switching input of multiplexer MX5 by sequence present on line 55. The output from multiplexer MX5 is connected to another divider 56 by line 57 and a third adder A3 has one input connected to the divider 56 and the other input connected to receive the band 4 signal present at input port 34 on line 57. The output from the band combining network is present from adder A3 on line 58.
Concerning the combining network, the adders do the actual combining of the separate dt signals. The divide by two functions are for weighting the band data and the multiplexer disables bands higher than one delivering a dt signal, which are outside their capture range and delivering a noise signal. The sequence of progressive iterations is not programmed but occurs naturally. Frequently different parts of the field will be at different stages in the matching progress.
Claims (6)
1. A time disparity discriminator for a digital scanning video system comprising:
(i) A first input port for left-handed digital video signals;
(ii) A second input port for right-handed digital video signals;
(iii) First delay means connected to said first input port to receive and delay said left video signals by a video clock pulse;
(iv) Second delay means connected to said second input port to receive and delay said right video signals by said video clock pulse;
(v) First multiplier means connected to said first input port and to said second delay means to multiply said left video signal by the delayed right video signal;
(vi) Second multiplier means connected to said second input port and to said first delay means to multiply said right video signal by the delayed left video signal; and
(vii) comparator means connected to said first and to said second multiplier means and arranged to output a two state time displacement signal, the states of which depend upon whichever output of said first and second multiplier means is the greater.
2. A discriminator as claimed in claim 1, wherein third multiplier means are connected to said first input port and said second input port to multiply said left video signal by said right video signal and comparator tree means are connected to said first, said second and said third multiplier means and are arranged to output a three state time disparity signal, the states of which are dependent upon whichever of the multiplier outputs is the greatest.
3. A-discriminator as claimed in claim 2, wherein one or more additional delay means are serially connected to said first and second delay means, an equivalent number of additional multiplier means are connected between either input port and respective delay means to additionally multiply the one video signal by the or each additionally delayed other video signal; and comparator tree means are connected to all the multiplier means and are arranged to output a time displacement signal, the number of states of which equal the number of multiplier means and which states are dependent upon whichever of the multiplier outputs is the greatest.
4. A discriminator as claimed in any of claims 1 to 3, wherein separate serial integrator means are connected between each multiplier means and said comparator means or said comparator tree means; whereby the output time displacement signal is the result of the comparison of linear pixel groups, the number of pixels in which is determined by the integration period of said serial integrator means.
5. A discriminator as claimed in any of claims 1 to 3, wherein separate lateral integrator means are connected between each multiplier means and said comparator means or said comparator tree means; whereby the output time displacement signal is the result of the comparison of lateral pixel groups, the number of lines in which is determined by the integration period of said lateral integrator means.
6. A band combining network to combine the time displacement signals produced by a series of discriminators as claimed in claim 2 or claim 4 or claim 5 as dependent upon claim 2 wherein:
(i) First separator means are connected to said first input port to separate the spectrum of said left video signal into a series of contiguous frequency bands,
(ii) Second separator means are connected to said second input port to separate the spectrum of said right video signal into said series of contiguous frequency bands,
(iii) A separate discriminator is connected to receive the components of said left and right video signals appearing in a respective one of said frequency bands, and
(iv) A band combining network is connected to each discriminator and comprises::
(a) Switching means, one input of which is connected to the discriminator for the highest frequency band and the other input of which is fed a zero signal,
(b) Zero decoder means connected to the discriminator for the next lower frequency band and connected to controi said switching means so that only a zero signal from the next lower discriminator will switch the signal from the highest discriminator to the output of said switching means.
(c) Dividing means connected to the output of said switching means to divide the output thereof in accordance with the ratio of the centre frequencies of the frequency bands.
(d) Adder means, one input of which is connected to said first divider means and the other input of which is connected to said discriminator for the next lower frequency band, and
(e) Successive switching means, zero decoder means, divider means and adder means connected as above to the discriminator for each remaining frequency band in said series of frequency bands; whereby the switching means will disable frequency bands higher than one delivering a time displacement signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08328428A GB2148648A (en) | 1983-10-25 | 1983-10-25 | Time disparity discriminator; correlation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08328428A GB2148648A (en) | 1983-10-25 | 1983-10-25 | Time disparity discriminator; correlation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8328428D0 GB8328428D0 (en) | 1983-12-21 |
| GB2148648A true GB2148648A (en) | 1985-05-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08328428A Withdrawn GB2148648A (en) | 1983-10-25 | 1983-10-25 | Time disparity discriminator; correlation |
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| GB (1) | GB2148648A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2261339A (en) * | 1991-10-22 | 1993-05-12 | Fuji Heavy Ind Ltd | Distance detection system for vehicle |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB964581A (en) * | 1959-08-10 | 1964-07-22 | British Iron Steel Research | Improvements in or relating to the measurement of time intervals |
| GB1365739A (en) * | 1971-05-04 | 1974-09-04 | Hasler Ag | Method and device for the measurement of the velocity of a body |
| GB1404609A (en) * | 1971-10-29 | 1975-09-03 | Siderurgie Fse Inst Rech | Method of and apparatus for the measurement of the speed of discontinuous products |
| EP0009452A2 (en) * | 1978-09-21 | 1980-04-02 | INSTITUT DE RECHERCHES DE LA SIDERURGIE FRANCAISE (IRSID) France | Apparatus for measuring the velocity of a moving product by means of the correlation technique |
| GB1574022A (en) * | 1976-01-27 | 1980-09-03 | Siemens Ag | Target tracking systems |
-
1983
- 1983-10-25 GB GB08328428A patent/GB2148648A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB964581A (en) * | 1959-08-10 | 1964-07-22 | British Iron Steel Research | Improvements in or relating to the measurement of time intervals |
| GB1365739A (en) * | 1971-05-04 | 1974-09-04 | Hasler Ag | Method and device for the measurement of the velocity of a body |
| GB1404609A (en) * | 1971-10-29 | 1975-09-03 | Siderurgie Fse Inst Rech | Method of and apparatus for the measurement of the speed of discontinuous products |
| GB1574022A (en) * | 1976-01-27 | 1980-09-03 | Siemens Ag | Target tracking systems |
| EP0009452A2 (en) * | 1978-09-21 | 1980-04-02 | INSTITUT DE RECHERCHES DE LA SIDERURGIE FRANCAISE (IRSID) France | Apparatus for measuring the velocity of a moving product by means of the correlation technique |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2261339A (en) * | 1991-10-22 | 1993-05-12 | Fuji Heavy Ind Ltd | Distance detection system for vehicle |
| US5307136A (en) * | 1991-10-22 | 1994-04-26 | Fuji Jukogyo Kabushiki Kaisha | Distance detection system for vehicles |
| GB2261339B (en) * | 1991-10-22 | 1996-04-03 | Fuji Heavy Ind Ltd | Distance detection system for vehicle |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8328428D0 (en) | 1983-12-21 |
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