GB2147161A

GB2147161A - Battery charging system

Info

Publication number: GB2147161A
Application number: GB08331469A
Authority: GB
Inventors: M W Lowndes; Derek Stanley Adams; Neville John Arlidge
Original assignee: Lucas Industries Ltd
Current assignee: ZF International UK Ltd
Priority date: 1980-06-28
Filing date: 1983-11-25
Publication date: 1985-05-01
Also published as: GB8331469D0; GB2147161B

Abstract

A microprocessor based monitoring/charging system for the traction battery 10 of an electric vehicle evaluates the state of charge and displays it on a dashboard mounted meter 64, interfaces with a traction motor control system 20, and controls a charger 22. The battery is divided into nine 24V sub-packs. During both discharge and recharge, the battery current is integrated to obtain a value representing the charge withdrawn. During charging, in a first phase the charge withdrawn is replaced whilst progressively reducing the charging current in accordance with the charge withdrawn value. At the end of the first phase the sub-pack having the lowest voltage is found and, during a second phase, the battery is charged until the rate of voltage rise of this sub-pack falls below a critical level. This battery is then given an overcharge, and at periodic intervals the battery is given an equalising charge. <IMAGE>

Description

SPECIFICATION Battery charging system This invention relates to a charging system for a traction battery pack and also to a method of charging a traction battery pack.

When recharging a battery, the charging efficiency is reduced as the charging current increases, particularly towards the end of recharging. In the case of a lead acid battery, this inefficiency is caused by heat dissipated by the internal resistance of the battery and by electrolysis of water at voltages around 2.35 volts/cell or greater. As the battery voltage increases towards the end of a recharge, the charging current must be progressively reduced to avoid an increase in electrolysis. However, as the charging current is reduced, the overall time for charging is increased which is undesirable where there is only a limited time available for recharging. It is desirable therefore to select and vary the charging current so as to obtain a satisfactory compromise between charging efficiency and overall charging time.

It is an object of this invention to obtain such a compromise.

According to one aspect of this invention, there is provided a charging system for a battery including means for charging the battery according to a predetermined cycle, means responsive to the battery current during charging and discharging for obtaining a value representing battery current, and means for integrating the current value with respect to time to obtain a value representing charge withdrawn, said predetermined cycle including a phase in which the battery is supplied with a charge equivalent to the charge withdrawn during discharge, the charging current depending during said phase on the charge withdrawn value.

According to another aspect of this invention, there is provided a method of charging a battery in accordance with a predetermined cycle, measuring the battery current during charging and discharging to obtain a value representing battery current, and integrating the current value with respect to time to obtain a value representing charge withdrawn, said cycle including a phase in which the battery is supplied with a charge equivalent to the charge withdrawn during discharge, the charging current being dependent during said phase on the charge withdrawn value.

This invention will now be described in more detail by way of example, with reference to the accompanying drawings in which: Figure 1 is a graph of the discharge characteristics of a twelve cell sub-pack forming part of a lead acid traction battery; Figure 2 is a block diagram of a battery monitoring system embodying the various aspects of this in invention; Figure 3 is a circuit diagram of the microprocessor unit and associated memories and the clock and associated interface of the system shown in Fig. 2; Figures 4, 5 and 6 together form a circuit diagram of the analog to digital section of the system shown in Fig. 2; Figures 7, 8 and 9 together form a circuit diagram of the battery charger of the system shown in Fig. 2; Figure 10 is a diagram illustrating the configuration of a data word associated with the battery charger;; Figure 11 is a circuit diagram of the serial to parallel converter, the digital to analog converter and the override signal output circuit forming part of the system shown in Fig. 2; Figure 12 is a diagram of a status word used in the system of Fig. 2; and Figures 13 to 38 are flow charts illustrating the operation of the system shown in Fig. 2.

Turning now to Fig. 2, there is shown a general arrangement of the battery monitoring system for an electric vehicle. The monitoring system comprises a lead acid traction battery 10 which is formed from nine individual twenty four volt sub-packs which are connected in series to provide an output nominal voltage of 216 volts. Each sub-pack contains twelve cells connected in series.

The negative terminal of the battery is connected in series with a current measuring resistor 1 2.

The battery 10 provides power to a traction motor 14, which is the main traction motor of the vehicle, via detachable connectors 1 6 and 18 and a motor controller 20. The controller also receives driver controls, such as accelerator pedal position and brakd pedal position, and also an override signal as will be described below. The battery 10 may be charged by an offboard charger 22.

The reason for dividing the traction battery pack 10 into nine individual sub-packs each of which contains twelve cells will now be explained.

In the present system during the last part of discharge battery voltage is used to evaluate the remaining available charge of the battery. In a traction battery which has been subjected to deep discharge/re-charge cycling the charge storage capacity of some of the weaker cells may have fallen to 10 to 15% below their nominal capacity. Consequently, if the total battery voltage is used to evaluate the available charge some of the weaker cells may have suffered cell reversal (i.e. become charged with the reverse polarity) when end of discharge is indicated for the entire pack. Such cell reversal would cause severe damage. On the other hand, if the available charge is evaluated from the voltage of the weakest cell, then the remaining cells may still possess a substantial part of their charge when end of discharge is indicated.Also extensive circuitry would be necessary to monitor individual cells.

Consequently it is considered desirable to divide the battery pack into sub-packs and to evaluate the available charge from the voltage of the weakest sub-pack. The number of cells in each sub-pack should be selected to be as large as possible without the risk of cell reversal occuring before end of discharge is indicated, and in the case of a lead-acid battery it is considered that each sub-pack should be formed from twelve cells.

Referring to Fig. 1 there is shown the discharge characteristics for a twelve cell sub-pack forming part of a lead-acid traction battery. The sub-pack comprises eleven cells which have retained their nominal charge storage capacity as indicated by curve A and one cell indicated by curve B which has lost 15% of its storage capacity. As indicated by the dashed line, a single cell reaches its end of discharge at 1.65 volts. If end of discharge for the sub-pack is indicated when the voltage of the weak cell falls to 1.65 volts as indicated by point C then the remaining cells will still possess a substantial part of their charge as indicated by the arrow D.Alternatively, if end of discharge is indicated at point E when the voltage of the other cells has fallen to 1.65 volts, as might be the case if the overall battery voltage is used to indicate the state of charge, then the weak cell will have suffered cell reversal. However, if end of discharge is indicated when the average cell voltage has fallen to 1.65 volts as indicated at point F, then although the voltage of weak cell will have fallen well below 1.65 volts cell reversal will not have occurred. Also, the remaining cells will only possess a small part of their charge as indicated by arrow G.

The battery 10 is monitored by a microprocessor system which also controls the charger 22 and provides the override signal.

At the centre of the microprocessor system there is a microprocessor unit (MPU) 24 which together with its associated memories comminicates with a signal bus 26. The microprocessor system also includes a clock 28 which provides clock pulses CLCK to the MPU 24 and a timing signal to a logic circuit 30. The logic circuit 30 receives a power fail signal PWFL from the power supply for the microprocessor system. The signal PWFL goes low when there is a power failure and goes high when the power is restored. The logic circuit 30 also provides a non maskable interrupt signal NMI and an interrupt request signal IRQ to the MPU 24. The clock 28 also provides lapsed time information to the MPU 24 via an interface 32 and the signal bus 26.

The microprocessor system monitors the battery 10 via an analog to digital section. This section comprises a selector circuit 34 which receives various analog signals concerning the battery pack 10. These analog signals comprise a current signal from the measuring resistor 12, three temperature signals which are transmitted by a data bus 36 from two temperature probes positioned in the electrolyte of the traction battery 10 and one probe positioned in the vicinity of the system electronics, and voltage signals from the individual sub-packs which are transmitted via a bus 38. The selector 34 provides a single analog output signal to a comparator 40. The analog to digital section also comprises an interface 42 which communicates with the signal bus 26.The interface 42 provides output signals to a decoder 44 which in turn provides output signals via a bus 46 to the selector 34 and which determine the particular analog signal which is to be selected and transmitted to the comparator 40. The interface 48 which provides a second analog signal to the comparator 40. The comparator 40 provides an output signal representing the result of the comparison to the interface 42.

The MPU 24 also receives information concerning the vehicle state via an interface 50 and the data bus 26. The interface 50 receives five vehicle state signals and these are a vehicle power on signal SLO, a charger connected signal SL1, a fans running signal SL2, a gas heads signal SL3 and a charger power on signal SL4. The vehicle power on signal, charger connected signal and the charger power on signal are considered self-explanatory. The fans running signal indicates proper operation of a fan which is provided for removing gas from the space adjacent to the traction battery. The gas heads signal concerns four gas detecting heads mounted in the battery compartments of the battery 10. These gas heads monitor the rate at which gas is being generated and provide a warning signal in the event of excessive gassing.

The inferface 50 also provides control signals PSU INHIBIT and PSU HOLD to the system power supply. Power is normally supplied to the microprocessor system when either vehicle power is on or the charger power is on. However, if the signal PSU HOLD goes high, the power supply is maintained with neither vehicle power nor charger power on. When the signal PSU INHIBIT goes high, it causes the signal PWFL to go low for a short period for a purpose which will be described below.

The MPU 24 calculates the state of charge of the traction battery 10 and this information is transmitted periodically via the signal bus 26 to a meter driver 60. The meter driver 60 provides a square wave signal, the mark space ratio of which is proportional to the state of charge of the battery 10, via a detachable connection 62 to a state of charge meter 64 positioned on the dashboard of the vehicle.

The signal bus 26 also communicates with an interface 70 which converts data provided by the MPU 24 in parallel form into serial form in the complimentary return to zero (CRZ) format.

This data is transmitted on transmission lines TX. The interface 70 also converts serial data received on receiving lines RX in the complimentary return to zero (CRZ) format into parallel format for transmission to the MPU 24. The serial data on the transmission lines TX may be supplied to the charger 22 via detachable connections 72. This serial data is also supplied to a serial to parallel converter 74 via detachable connections 75. Data is transmitted in parallel format from the converter 74 to a digital to analog converter 76 which supplies an analog signal to an override output circuit 77 which in turn provides an override signal to the controller 20.

As will be explained below, when the state of charge of the battery 10 is low this override signal limits the maximum current which may be supplied to the traction motor 14.

The transmission lines TX and receiver lines RX are also connected to a converter 79. The converter converts the serial data which it receives on the transmission lines TX into serial teletype format and provides this data on its output data bus 78. It also converts incoming parallel data provided on its data bus 78 into serial from the transmission on the receiver lines RX to the interface 70. The data bus 78 is joined by a detachable connection 80 to a teletype unit 82 which is provided for initialising and monitoring the microprocessor system.

The traction battery 10 and the microprocessor system that is the MPU 24, the clock 28, the interface 32, the logic circuit 30, the selector 34, the comparator 40, the interface 42, the decoder 44, the digital to analog converter 48, the meter driver 60, the interface 50, the interface 70, and converter 79 may be removed from the vehicle as a single unit. By arranging the traction battery and microprocessor system as a single unit, the microprocessor system can monitor the battery for its entire life including periods when the battery is not positioned in the vehicle.

The details of the controller 20 are described in our published Patent Co-operation Treaty Application No. 78/00046. The remainder of the battery monitoring system will now be described in greater detail hereinafter.

Referring now to Fig. 3 there is shown the MPU 24 which is a Motorola M6802 microprocessing unit and which is connected via an address bus 100 and a data bus 102 to a read only memory (ROM) 104 and a random access memory (RAM) 106. The data bus 102 also provides data signals DO to D7. The complete programme for operating the microprocessor system is permanently stored in the ROM 104 and the variables generated during operation of the system are stored in RAM 106 and also in the internal RAM of MPU 24.

Fig. 3 also shows the clock 28. This comprises a clock pulse generator 108 which provides clock pulses CLCK at a frequency of 4MHz to the clock pulse input pin EXTAL of MPU 24. The 4MHz pulses are also supplied via line 110 to the input of a frequency divider 11 2 and this in turn provides pulses at a frequency of 1 OHz on a line 114. The line 114 is connected to the input of a divider 11 6 at the output of which there is provided elapsed time information. This elapsed time information is connected via a data bus 11 8 to the peripheral data inputs of interface 32. On the side of the interface 32 which communicates with the MPU its data inputs are connected to the data bus 102.

Also shown in Fig. 3 is the logic circuit 30. This comprises an inverter 120, the input of which receives the signal PWFL and the output of which is connectd to the input of an inverter 122. The output of inverter 112 provides a signal NMI which is provided to the non maskable interrupt pin NMI of MPU 24.

The output of inverter 1 20 is supplied to the input of a delay circuit 124, at one output of which there is provided a signal RESET which is provided to the reset line RESET of MPU 24.

Thus the signal PWFL is supplied in inverted form and with a delay to the reset line RESET of MPU 24. Consequently, when the signal PWFL goes high indicating resumption of power supply after a power failure the MPU 24 receives a reset signal.

The output of delay circuit 1 24 is also connected to the input of an inverter 1 26 the output of which is connected to the D input of a flip-flop 1 28. The C input of flip-flop 1 28 receives the 1OHz signal from the line 11 4 and the reset input R of flip-flop 1 28 is connected via a line 1 30 to a peripheral data output of interface 32. The Q output of flip-flop 1 28 is connected to the interrupt request pin IRO of MPU 24. In normal operation of the system, the flip-flop 124 provides interrupt signals to MPU 24 at a frequency of 1OHz, the flip-flop 128 being reset immediately after supplying each interrupt signal.

Referring now to Fig. 4, there is shown the circuit diagram for the interface 42, the decoder 44 and the digital to analog converter 48. On the side of the interface 42 which communicates with the MPU its data inputs receive the data signals DO to D7. On its other side, some of its peripheral data outputs are supplied to the input of the digital to analog converter 48, the output of which is connected via a line 1 50 to the comparator 40. A peripheral data input of interface 42 receives the output signal from the comparator 40 on a line 1 52. The remaining peripheral data outputs of interface 42 are connected to the input of the decoder 44.The decoder 44 has fourteen outputs which are connected respectively to lines 1 60 to 1 73. Lines 162 to 160 provide respectively temperature selection signals T1 to T3. Lines 160 to 162 are also connected to three inputs of an OR gate 1 80 at the output of which there is provided the temperature selection signal TEMP. The line 1 63 provides the current selection signal IAV and the line 164 provides the current selection signal IPEAK. The lines 1 65 to 1 72 are connected respectively to the first inputs of OR gates 181 to 188 and the lines 166 to 173 are connected respectively to the second inputs of these OR gates.The line 1 65 provides the voltage selection signal B9 and the output of OR gates 181 to 188 provide the voltage selection signal B8 to BO.

The line 1 65 and the outputs of OR gates 182, 184, 186, 1 88 are connected to the five inputs of an OR gate 190, at the output of which there is provided the voltage selection BATT.

Referring now to Fig. 5 there is shown a circuit for generating a signal representing the voltage of one of the sub-packs and which forms part of the selector 34 shown in Fig. 2. As mentioned above, the battery 10 is divided into nine sub-packs and these are denoted in Fig. 5 by reference numerals 201 to 209. The negative terminal of sub-pack 201 is connected to the input of a switch 220, and the positive terminals of sub-packs 201 to 209 are connected respectively via potential divider 211 to 219 to the inputs of switches 221 to 229. The control inputs of switches 220 to 229 respectively receive the voltage selection signals BO to B9. The outputs of switches 220, 222, 224, 226 and 228 are connected to the negative input of a difference amplifier 240 and the outputs of switches 221, 223, 225, 227 and 229 are connected to the positive input of this amplifier.At the output of amplifier 240 there is provided the signal VBATT which represents the voltage of one of the sub-packs. In operation, if for example the output of decoder connected to line 1 70 goes high, then the voltage selection signals B3 and B4 will go high and so the signal VBATT will represent the voltage of the subpack 204.

Referring now to Fig. 6, there is shown the circuit for the remainder of the selector 34 and the comparator 40. This circuit comprises three temperature probes 251, 252 and 253, the probes 251 and 252 being positioned in the electrolyte of the traction battery 10 and the probe 253 sensing the temperature of the system electronics. The output of probes 251 to 253 are connected respective to the inputs of switches 255 to 257, the control inputs of which receive the temperature selection signal T1 to T3. The outputs of switches 255 to 257 are connected to the inputs of a further switch 258 which receives the temperature selection signal TEMP. The analog signal VBATT is connected to the input of a switch 260, the control input of which receives the voltages selection signal BATT.

The resistor 1 2 which senses the current flowing in the battery 10 is connected across the two inputs of a difference amplifier 262, the output of which is connected through a resistor 263 and a capacitor 264 to earth, and the junction of resistor 263 and capacitor 264 is connected to the input of a switch 265. The control input of switch 265 receives the current selection signal IAV. The output of comparator 262 is also connected to the input of a peak detector 266, the output of which is connected to the input of a switch 267. The control input of switch 267 receives the current selection signal IPEAK.The output of switches 260, 258, 267 and 265 are connected through a polarity controller to the positive input of comparator 40, and the negative input of comparator 40 receives the output from the digital to the analog converter 48 via line 1 50. The polarity controller 268 functions to invert negative signals so that a positive signal is always applied to the non-inverting input of comparator 40. As mentioned before the output of comparator 40 is connected via line 1 52 to a peripheral data input of interface 42.

In operation, if for example the output of decoder 44 connected to line 1 64 goes high, the current selection signal IPEAK will go high thereby rendering switch 267 conductive and supplying a signal representing peak current to the positive input of comparator 40 which will therefore compare the peak current with the output of the digital to analog converter 48. Thus, all the analog signals may be converted in turn into digital form.

The detailed circuit diagram of the battery charger 22 is shown in Figs. 7 and 9. Referring in particular to Fig. 7, the battery charger may be connected to the traction battery pack 10 through a socket 930 associated with the charger and a plug 932 associated with the traction battery pack. The charger will be described connected to the battery pack 10.

A main power supply is connected to the charger at terminals L and N and these terminals are connected through fuses 933 and 934 and contacts 935a and 935b of a relay 935 to the two ends of a primary winding 936 of a main transformer 937. A lamp 938 is connected across the winding 936 to indicate that the charger is working. The transformer 937 ha a secondary winding 939 and an auxiliary secondary winding 940. One end of the winding 939 is connected through a fuse 941 to the anode of a thyristor 942 and to the cathode of a thyristor 943. The other end of winding 939 is connected through a fuse 944 to the anode of a diode 945 and to the cathode of a diode 946. The anode of diode 946 is connected to the anode of thyristor 943 and the cathode of diode 945 is connected to the cathode of thyristor 942.The anode of thyristor 942 is connected to the anode of diode 945 through a resistor 947, a capacitor 948, and a capacitor 949, connected in series. The gate and cathode of thyristor 943 are connected to a pair of control terminals TH 1 and the gate and cathode of thyristor 942 are connected to a pair of control terminals TH2.

The cathode of thyristor 942 is connected through a ballast inductor 950 to a rail 951 which is connected through a fuse 952 to the positive terminal of the battery 10. The negative terminal of battery 10 is connected through a fuse 953 to a rail 954 which is connected through a current measuring resistor 955 to a rail 956. The rail 956 is connected to the anode of thyristor 943.

Thus, when contacts 955 and 935b are closed and suitable timing signals are applied to the control terminals TH 1 and TH2, the battery 10 will be charged.

The traction battery pack 10 includes four pressure control switches 962 to 965, and a fan 966 for providing ventilation to the battery. The pressure controlled switches 962 to 965 are mounted at four separate positions and are arranged to detect the rate at which gas is being generated in the battery 10. If the rate of gassing is below a predetermined level, the switches are closed. Provided in the vehicle there is an auxiliary 1 2 volt battery 960 which is charged from the main traction battery 10.

The positive terminal of battery 960 is connected to the rail 968 and the negative terminal is connected to earth by a OV rail 969. The rail 968 is connecteda to the OV rail through a coil 970a of a relay of a relay 970, a diode 971 bridging the coil 970a with its cathode connected to the OV rail. The rail 968 is also connected to one end of a coil 973a of a relay 973, the other end of which is connected to the collector of an NPN transistor 974. The emitter of transistor 974 is connected to the OV rail, and its base is connected through a resistor 975 to a rail 976.

The rail 976 receives a signal PH6 as will be described below. The relay coil 973a is bridged by a diode 972, the cathode of which is connected to the rail 968. The switches 962 are connected in series between the positive terminal of battery 960 and a rail 978. The rail 978 is connected through a pair of contacts 979a of a relay 979 to a rail 980. The rail 980 is connected to one end of a relay coil 982a of a relay 982, and the other end of coil 982a is connected to the collector of a transistor 983. The emitter of transistor 983 is connected to the OV rail and its base is connected through a resistor 984 to a rail 985 which receives a signal DV as will be explained below.

The terminals L and N are connected through contacts 970b and 970c of relay 970 to rails 990 and 991. Rail 990 is connected to one end of the primary winding of a transformer 992, the other end of which is connected through the relay coil 979b of relay 979 to rail 991. The coil 979b is bridged by a resistor 993. The secondary winding of transformer 992 is connected through fuses 994 and 995 to the fan 966.

The L terminal is connected through contacts 982b of relay 982 to one end of the coil 935c of relay 935 to the N terminal. Also, the L terminal is connected through contacts 973b of relay 973 and a ready lamp 997 to the terminal N.

In operation, when socket 930 is connected to plug 932, relay coil 970a will be energised thereby closing contacts 970b and consequently energising fan 966. Then, providing switches 962 to 965 are closed, the positive terminal of battery 960 will be connected to rail 978. If the fan 966 is operating correctly, relay coil 979b will be energised thereby closing contacts 979a and so connecting rail 978 to rail 980. Then, if a high signal is present on rail 985, transistor 983 will be rendered conductive thereby energising relay coil 982 and so closing contacts 982b. Consequently, relay coil 935c will be energised thereby closing contacts 935a and 935b and so supplying mains power to the transformer 937.Also, if a high signal is present on rail 976, which will be the case when charging is completed, transistor 974 will be rendered conductive thereby closing contacts 973b and energising the ready lamp 997.

As will now be explained, the circuit shown in Fig. 7 may provide the vehicle state line signals SL1 to SL4. As rail 968 will be high when the socket 930 is connected to the plug 932, this rail may be used to provide the signal SL1, which indicates that the charger is connected. The signal SL2 which indicates that the fan 966 is operating may be provided by a further pair of contacts associated with relay 979. The signal SL3 which indicates that the switches 962 to 965 are closed may be provided by rail 978 and the signal SL4 which indicates that the charger is on may be provided by a further set of contacts associated with relay 982.

Referring now to Fig. 8 there is shown a full wave rectifier 1010, the input terminals of which are connected across the secondary winding 940 to the mains transformer 937 shown in Fig. 7 and the output terminals of which are connected to rails 1012 and 1013. Rail 1012 is connected through a capacitor 1014 to the rail 1013 and also through a resistor 101 5 to the base of a transistor 101 6, the collector of which is connected to the rail 1012 and the emitter of which is connected to a rail 101 7. The base of transistor 1016 is also connected to the cathode of a zener diode 101 9, the anode of which is connected to the rail 101 3. The rail 1017 is connected through a fuse 1018 to a rail 1020 and a constant voltage will normally be present between rails 1013 and 1020.

The secondary winding 940 is also applied to the input terminals of a second full wave rectifier 1025. One output terminal of rectifier 1025 is connected to rail 101 3 and the other output terminal is connected through a resistor 1026 to the cathode of a zener diode 1027, the anode of which is connected to the rail 101 3. A capacitor 1028 is connected across zener diode 1027 and the cathode of zener diode 1027 is connected through a resistor 1 030, and a resistor 1031, connected in series, to rail 1013.

In operation, a clipped fully rectified waveform will be present at the junction of resistors 1030 and 1031.

The junction of resistors 1030 and 1031 is applied to the base of an NPN transistor 1032, the emitter of which is connected to the rail 1013 and the collector of which is connected through a resistor 1034 to the rail 1020 and through a resistor 1035 to the rail 101 3. The junction of resistors 1034 and 1035 is connected through a resistor 1036 to the base of an NPN transistor 1038, the emitter of which is connected to the rail 101 3 and the collector of which is connected through a capacitor 1040 to the rail 101 3. The rail 1020 is connected to the anode of a diode 1042, the cathode of which is connected through a resistor 1043 to the collector of transistor 1038.The collector of transistor 1038 is also connected to the noninverting input of an operational amplifier 1 044, the output of which is connected to its noninverting input and also through a capacitor 1046 to the cathode of diode 1042.

In operation, a ramp-shaped waveform will be present at the output of amplifier 1 044.

The output of amplifier 1044 is connected through a resistor 1048 to the inverting input of an operational amplifier 1050, the output of which is connected to its non-inverting input through a resistor 1052. The output of amplifier 1050 is connected through a capacitor 1053 and a resistor 1054, connected in series, to rail 1020. The junction of capacitor 1053 and resistor 1054 is connected to the anode of diode 1055, the cathode of which is connected to the rail 1020, and also to the input of a monostable 1056. The output of monostable 1056 is connected through a resistor 1058 and a resistor 1059, connected in series, to rail 101 3, and the junction of resistors 1058 and 1059 is connected through a resistor 1060 to the base of an NPN transistor 1062.

The emitter of transistor 1062 is connected to the rail 1013 and its collector is connected through the primary winding 1064 of a transformer 1065 to the anode of a zener diode 1066, the cathode of which is connected to the rail 1020. The collector of transistor 1062 is also connected to the anode of a diode 1067, the cathode of which is also connected to the rail 1020.

The transformer 1065 has two secondary windings 1071 and 1072. A resistor 1073 is connected across the winding 1071, and one end of winding 1071 is connected to the anode of a diode 1074, the cathode of which is connected through a resistor 1075 to one of the thyristor control terminals TH 1 shown in Fig. 7. The other terminal of winding 1071 is connected directly to the other control terminal. A resistor 1076 is connected across the winding 1072 and one end of this winding is connected to the anode of a diode 1077 the cathode of which is connected through a resistor 1078 to one of the thyristor control terminals TH2. The other end of this winding is connected to the other control terminal.

The rail 954 connected to one end of measuring resistor 955 shown in Fig. 7 is connected to the rail 1013 and the other end of measuring resistor 955 is connected through a resistor 1080 and a resistor 1081, connected in series, to rail 1013. The junction of resistors 1080 and 1081 is connected to the non-inverting input of an operational amplifier 1082, the output of which is connected through a resistor 1083 to its inverting input and its inverting input is connected through a resistor 1084 to rail 101 3. The output of amplifier 1082 is also connected through a resistor 1085 to the rail 1013.

In operation, the output voltage of amplifier 1082 will be representative of the current supplied to the traction battery 10.

The output of amplifier 1082 is connected through a resistor 1090 to the non-inverting input of an operational amplifier 1091, the output of which is connected to its inverting input through a resistor 1092.

The rail 1020 is connected through a resistor 1094 to a rail 1093. The rail 1093 is connected to the cathode of a zener diode 1095, the anode of which is connected to the rail 1013, and the diode 1095 is bridged by a capacitor 1096.

The rail 1093 is connected through a resistor 1100, a preset resistor 1101, and a resistor 1103, connected in series, to rail 101 3, and the junction of resistors 1101 and 1103 is connected through a relay contact 1 102ato a rail 1104. The rail 1093 is connected through a resistor 1105, a variable resistor 1106 and a resistor 1108, connected in series, to the rail 1103 and the junction of resistors 1106 and 1108 is connected through a relay contact 11 07a to the rail 1104. The rail 1093 is also connected through a resistor 1110, a variable resistor 1111, and a resistor 11 3 connected in series, to the rail 101 3, and the junction of resistors 1111 and 1113 is connected through a relay contact 111 2a to the rail 1114. The rail 1093 is connected through a resistor 1115, a variable resistor 1116 and a resistor 1118, connected in series, to the rail 1104 and the junction of resistors 111 6 and 111 8 is connected through a relay contact 111 7a to rail 1104.The rail 1093 is connected through a resistor 11 20, a variable resistor 11 21 and a resistor 1123, connected in series, to the rail 1104, and the junction of resistors 1121 and 1123 is connected through a relay contact 1 122ate the rail 1104. Finally, rail 1093 is connected through a resistor 1125, a variable resistorl 126 and a resistor 1128, connected in series, to the rail 101 3, and the junction of resistors 11 26 and 1128 is connected through a relay contact 1 127ate the rail 1104.

The rail 1104 is connected through a resistor 1140 and a capacitor 1142, connected in series, to rail 101 3, and the junction of resistors 1140 and the capacitor 1142 is connected through a resistor 1143 to the inverting input of amplifier 1 091.

In operation, in accordance with the current required, one of the contacts 1102a, 11 07a, 111 2a, 111 7a and 11 22a will be closed and so amplifier 1091 will compare a signal representing actual current with a signal representing the required current and so its output will be an error signal.

The output of amplifier 1091 is connected through a resistor 11 50 to the non-inverting input of an operational amplifier 1152, the output of which is connected through a resistor 11 53 to its inverting input and its inverting input is connected through a resistor 1155 to the rail 1013.

The rail 1020 is connected through a resistor 11 54 and a variable resistor 1156, connected in series, to the rail 101 3 and a tapping on resistor 11 56 is connected through a resistor 11 57 to the non-inverting input of amplifier 1152. The rail 1020 is also connected through a capacitor 11 58 and a resistor 1159, connected in series, to the rail 101 3, and the junction of capacitor 11 58 and resistor 11 59 is connected to the anode of a diode 1160, the cathode of which is connected through a resistor 1161 to the non-inverting input of amplifier 1152.

The output of amplifier 11 52 is connected through a resistor 11 70 and a capacitor 11 72 to the rail 1013 and the junction of resistor 1170 and capacitor 1172 is connected through a resistor 11 74 to the non-inverting input of an amplifier 1050.

In operation, during each half cycle of the mains power supply, the output of amplifier 1050 will go low when the voltage applied to its inverting input exceeds that applied to its noninverting input. When the output goes low, the monostable 1056 will be triggered thereby rendering transistor 1062 conductive and applying output pulses across the thyristor control terminals TH1 and TH2, Consequently, the thyristor 942 or 943 which is forwardly biased will be rendered conductive.

When the charger is first energised, a high voltage will initially be present at the junction of capacitor 11 58 and resistor 11 59 thereby ensuring that the initial charging current is low.

Subsequently, this voltage will decay thereby allowing a gradual build-up of the charging current until it reaches the value determined by the voltage on rail 1104.

Referring now to Fig. 9 there is shown a serial to parallel converter forming part of the charger and indicated by the chain line 1 200. The serial signal TX in CRZ format from interface 70 is received as two signals TXS and TXM, TXM going high for a binary "1" and TXS going high for a binary "0". The signal TXS and the OV rail are connected through detachable connections 72a to a pair of rails 1 203 and 1 204 and the signal TXM and the OV rail are connected through detectable connections 72b to a pair of rails 1 208 and 1 209. The rail 1 203 is connected through a resistor 1210 to a supply rail Vcc and to the rail 1204 by a capacitor 1211.The rail 1203 is also connected to the input of a Schmitt inverter 1212 the output of which is connected to one input of a NAND gate 1214. The rail 1208 is connected to the Vcc rail by a resistor 1216 and to the rail 1209 by a capacitor 1217. The rail 1208 is also connected to the input of a Schmitt inverter 1218 the output of which is connected to one input of a NAND gate 1220. The output of NAND gate 1214 is connected to the other input of NAND gate 1 220 and the output of NAND gate 1220 is connected to the other input of NAND gate 1214. Thus, the two NAND gates 1214 and 1220 function as a flip-flop. Consequently, the serial data which is received in the return to zero (CRZ) format is converted by flip-flops 1214 and 1220 into the non-return to zero (NRZ) format.

The output of NAND gate 1214 is connected to the data input D of a four stage latch 1230.

The Q3 output of latch 1 230 is connected to the data input D of a four stage latch 1 232. The Q3 output of latch 1 232 is connected to the D input of a flip-flop 1 234 and the Q output of flip-flop 1 234 is connected to the D input of a flip-flop 1 236.

The outputs of the two inverters 1 21 2 and 1 218 are connected to the two inputs of a NAND gate 1238, the output of which is connected to the two inputs of a NAND gate 1 240. The NAND gates 1 238 and 1 240 produce clock pulses at a frequency corresponding to the transmission frequency of the incoming serial data.

The output of NAND gate 1240 is connected to one input of a NAND gate 1 242. The output of NAND gate 1242 is connected to the clock input C of a four stage binary up-counter 1 246.

The 01 and 03 outputs of counter 1 246 are connected to the two inputs of a NAND gate 1247, the output of which is connected to the other input of NAND gate 1242. The output of NAND gate 1 247 is also connected to the two inputs of a NAND gate 1248, the output of which is connected to one input of each one of NAND gates 1250 and 1251. The output of NAND gate 1 250 is connected to the reset input R of counter 1 246.

The output of NAND gate 1 242 is connected to the clock input of shift register 1230, to the clock input of shift register 1232, to the C input of flip-flop 1 234 and to the C input of flip-flop 1 236. The 00 and Q1 outputs of shift register 1230 are connected to the two inputs of an - AND gate 1260, the output of which is connected to one input of an AND gate 1 261. The O output of flip-flop 1236 is connected to the other input of AND gate 1261, and the output of AND gate 2161 is connected to the other input of NAND gate 1251.

The Q2 and 03 outputs of shift registers 1 230 and the 00 output of shift register 1 232 are connected respectively to the data inputs D2, D3 and D4 of a latch 1 270. The Q1, Q2 and 03 outputs of shift register 1 232 and the Q output of flip-flop 1 234 are connected respectively to the data inputs D1 to D4 of a latch 1271. The output of NAND gate 1250 is connected to the clock inputs C of latches 1270 and 1271.

The Vcc rail is connected through a resistor 1 275 and a capacitor 1 276 to the OV rail. The junction of resistor 1 275 and capacitor 1 276 is connected to the A input of a type 4528 monostable 1278, the 0 output of which is connected to the reset inputs R of shift registers 1230 and 1 232 and flip-flops 1234 and 1236. The 0 output of monostable 1278 is connected to the CD input of another type 4528 monostable 1 280. The 0 output of monostable 1 280 provides the signal DV which is supplied to rail 985 shown in Fig. 7. The outout of NAND gate 1251 is connected to the A input of monostable 1280.

As shown in Fig. 10 the converter 1 200 receives ten bit words. Each word comprises a start bit which is set to a binary 0, seven data bits, an address bit which is set to a binary 1 when the converter 1 200 is being addressed, and a stop bit which is also set to a binary 1. In between words, a binary 1 is transmitted and consequently the output of a NAND gate 1214 is high.

When a new word is received, the start bit will cause the output of NAND 1220 to go high thereby causing the output of AND gate 1 250 to go high and hence resetting the counter 1 246. This will cause the output of NAND gate 1247 to go high thereby permitting clock pulses from NAND gate 1 240 to pass through NAND gate 1 242. These pulses will cause the incoming word to be clocked into the shift registers 1 230 and 1232, the flip-flop 1 234 and the flip-flop 1236.

When an entire word has been received, the counter 1 246 will be set to the binary number 1010 and consequently the Q1 and Q3 outputs will be high. Consequently the output of NAND gate 1 247 will go low thereby blocking the passage of further clock pulses through NAND gate 1 242. Also, the output of NAND gate 1 248 will go high thereby providing a high signal to one input of NAND gate 1250.

Also, when a complete word has been received, the QO output of shift register 1230, which corresponds to the stop bit, will go high, the Q1 output of shift register 1230, which corresponds to the address bit, will go high, and the 0 output of flip-flop 1 236, which corresponds to the inverse of the start bit, will also go high. Consequently, the output of AND gate 1261 will go high thereby causing the output of NAND gate 1251 to go low and the data bits to be clocked into latches 1270 and 1271.

Providing incoming words are received periodically, the output of NAND gate 1251 will go low periodically thereby ensuring that the Q output of monostable 1 280 remains high. Thus a high signal will be supplied to rail 985 shown in Fig. 7 thereby causing the main contacts 935a and 935b to be closed. If for some reason, the incoming words are not received, then the signal DV will go low thereby preventing charging.

It is to be noted that the monostable 1 278 is provided for initially resetting the shift registers 1230, 1232, 1234 and 1236, and also monostable 1280.

The Q3 and Q4 outputs of latch 1270 and the 01 output of latch 1 271 are connected respectively to the C, B and A inputs of a 3 to 8 decoder 1 290. The outputs CH 1 to CH6 of decoder 1290 provide signals PH 1 to PH6. These signals are indicative of the phase of the charging cycle which is being performed. In the arrangement shown, only the signal PH6 is utilized and when this signal is high it indicates that the charging cycle has been completed.

The signal PH6 is supplied to the rail 976 shown in Fig. 7 and, as may be readily appreciated, a high signal on this rail causes the ready lamp 997 to be energised.

The 02, 03 and Q4 outputs of latch 1 271 are connected to the C, B, and A inputs of a 3 to 8 decoder 1 292. The outputs CH 1 to CH6 of decoder 1 292 indicate respectively six current levels at which charging proceeds. These outputs CH1 to CH6 are connected respectively through resistors 1295 to 1300 to the bases of NPN transistors 1305 to 1310. The emitters of transistors 1 305 to 1 310 are connected to the OV rail and their collectors are connected respectively through relay windings 11 02b, 1107b, 111 2b, 111 7b, 11 22b and 11 27b to rail Vcc. Energisation of these relay windings cause closure respectively of relay contacts 11 02a, 1107a, 111 2a, 111 7a, 11 22a and 11 27a. The collectors of transistors 1305 to 1310 are also connected to the Vcc rail by diodes 1315 to 1320, the cathodes of these diodes being connected to the Vcc rail.

Thus, a high signal on one of the outputs CH 1 to CH6 of decoder 1 292 will cause the associated transistor to be rendered conductive thereby causing energisation of the associated relay winding and closure of the respective contacts shown in Fig. 8.

Referring now to Fig. 11 there is shown the detailed circuit diagram for the serial to parallel converter 74, the digital to analog converter 76, and the override output circuit 78 which provide the signal for overriding the controller 20. The purpose of this circuit is to limit the maximum current drawn by the traction motor 14 during the last 10 Ah of available charge of the traction battery 10 progressively from 100% of the normal maximum current to 40%.

The serial to parallel converter 74 is identical to the converter 1 200 shown in Fig. 9 except that it does not include an element equivalent to the monostable 1 280. The various elements of the converter 74 are denoted by identical reference numerals to the corresponding elements of converter 1 200 with the addition of the suffix A. The Q2, Q3 and Q4 outputs of latch 1 270A and the 01, 02, Q3 and 04 outputs of latch 1271A are connected respectively to the inputs of digital to analog converter 76. The output of converter 76 is connected to the non-inverting input of an operational amplifier 1400, the output of which is connected through a capacitor 1 401 to its inverting input.The output of amplifier 1400 is connected through a variable resistor 1402 and a resistor 1403, connected in series, to the OV rail, and also through a resistor 1404 to the base of a PNP transistor 1405 is connected to a rail 1406 and its collector is connected through a resistor 1407 to the OV rail. The collector of transistor 1405 is also connected to the base of a transistor 1408, the emitter of which is connected to the OV rail and the collector of which is connected to the rail 1406.

The rail 1406 is connected to the base of transistor N3 shown in Fig. 3 of our abovementioned Patent Co-operation Treaty Application No. 78/00046.

In operation, the maximum current which may be withdrawn from the traction battery 10 will be indicated in binary from at the 02, 03 and 04 outputs of latch 1270A and at the Q1, Q2, Q3 and 04 outputs of latch 1 271 A. Consequently, the output of the amplifier 1400 will be an analog signal representing the maximum current. In Fig. 3 of our above-mentioned Application, the signal at the base of transistor N3 represents the current demanded by the accelerator pedal.

If the current demanded is less than the maximum current permitted by the signal of the output of the amplifier 1400, then transistor 1 405 will be non-conductive and no interference will be made to this current damand signal. However, if the current demand signal exceeds the maximum current permitted by the output of amplifier 1400, then transistors 1405 and 1408 will conduct so as to limit the maximum current to the value determined by the output of amplifier 1400.

As mentioned above, the programmes for controlling the battery monitoring system are stored in ROM 104 shown in Fig. 3 and the general structure of these programmes will now be described.

Referring now to Table 1 below, the programmes include a set of control programmes, a set of interrupt programmes, and a set of utility sub-routines. The control programmes include a programme RESET which is entered after power is restored to the system. Upon completion of the programme RESET, the programme INTERR is entered and this programme is responsible for communication between MPU 24 and interface 70. The control programmes also include a programme POWERFAIL and this is entered upon failure of the power supply system.

As explained with reference to Fig. 3, the interrupt request pin IRO of MPU 24 normally receives interrupt signal from flip-flop 1 28 at a frequency of 1 OHz. If during execution of the programme INTERR an interrupt signal is received, then the interrupt programmes are entered.

These programmes include a 0.1 second routine which is performed each time an interrupt signal is received, i.e. at 0.1 second intervals, a one second routine which is performed at the end of each tenth pass through the 0.1 second routine, i.e. at one second intervals, and a ten second routine which is performed at the end of each tenth pass through the one second routine, i.e. at ten second intervals. If an interrupt signal is received during execution of the one second routine or the ten second routine, then the 0.1 second routine will be entered. After the interrupt programmes have been executed, programme control reverts to its previous position which may be in the programme INTERR, or in the one second routine or in the ten second routine.

The utility sub-routines comprises a set of programmes which may be called from the other programmes.

An eight bit status word CHWORD is used to communicate between the various programmes and the arrangement of this status word is shown in Fig. 1 2. In this word, bits 0, 1, and 2 indicated the charger current level, and bits 3, 4 and 5 indicate the charging phase, each charging cycle having five phases. Current levels 1 to 6 correspond respectively to charging currents of 1A, 5.5A, 8A, 15A, 20A, 30A.

The flow charts for the various progrlammes will now be described in detail.

Referring now to Fig. 13, there is shown a flow chart for the programme RESET. When power is restored to the system, the power fail signal PWFL goes high and after a short delay the signal RESET goes low thus causing the programme RESET to be entered. In an operation S10 at the beginning of this programme, the system is initialized and the signal PSU HOLD is set high and then in an operation S11 data which has been saved in RAM 106 is restored to the internal RAM of MPU 24. The programme flow then jumps to the programme INTERR.

Referring now to Fig. 14, after the programme INTERR has been entered data is transmitted from the output stack of the MPU 24 to the interface 70 for subsequent transmission in serial form to the charger 22 or interface 74. Then, in an operation S20, the interrupt mask of the condition code register of MPU 24 is examined. As will be explained below, this mask is set in the one second routine when a transition in the vehicle status has taken place from an active state to an idle state. If the mask is set, then in an operation S21 the signal PSUINHIBIT provided by the data output of interface 50 is set high thereby causing the signal NMI to go low for a short period with the result that the programme POWERFAIL is entered.If the mask is not set, then the programme continues with an operation S22 which permits the contents of the MPU memory to be examined and modified via the teletype 82.

The programme POWER FAIL shown in Fig. 1 5 is entered when the signal NMI goes low. The sole function of this programme is to save data from the MPU RAM in the RAM 1 06. RAM 106 has its own power supply, and so data is not lost in the event of power failure.

The flow chart of the sole programme INTSERV for the 0.1 second routine is shown in Fig.

1 6. This programme is entered each time the signal IRQ goes low thereby causing an interrupt.

After this programme has been entered in an operation S30 the flip-flop 1 28 is reset in preparation for issuing the next interrupt signal.

Then, in an operation S31 the vehicle state lines are read via interface 50 and then in an operation S32 a test is made to see if the vehicle is in an active state. If it is in an active state, then in an operation S33 the meter driver 60 is loaded with the present value of a variable DEFLN. The variable DEFLN represents the state of charge of the battery pack 1 0. Next, in an operation S34, a test is made to see if one second has elapsed since the last execution of the one second routine. If one second has elapsed then a jump is made to the programme TRANS but otherwise a return from interrupt is performed. If in operation S32 it is found that the vehicle is not in an active state, a test is made in an operation S33 to see if the transition has occurred between an active state and an idle state.If such transition has occurred, then a jump is made to the programme TRANS. If no such transition has occurred, then a test is made in an operation S35 to determine if one second has elapsed since the vehicle became idle. If one second has elapsed, then the interrupt mask is set before return from interrupt is performed.

The flow chart to the programme TRANS is shown in Fig. 1 7. After this programme has been entered, a test is made to see if the transition in the vehicle state has taken place between an active state and an idle state. If no such transition has been made, then a jump occurs to the programme ADCONV. If the transition has occurred, then the jump is made to an appropriate one of the transition programmes. These programmes are responsible for carrying out certain operations when a transition has occurred. These programmes are DRVIDL, CHRDL, IDLDRV, and IDLCHR, and these programmes are executed respectively after a transition has been made from vehicle power on to idle, from charger connected to idle, from idle to vehicle power on, and from idle to charger connected. These programmes will be now described.

Referring now to Fig. 18, there is shown the flow chart for the programmes CHRIDL and DRVIDL. As may be seen, the operations performed in the programme DRVIDL also form part of the programme CHRIDL.

After the programme CHRIDL has been entered, in an operation S40 variables CWD and OCA are added together and the result is tested. The variable CWD represents the charge which has been withdrawn from the battery less the amount which has been replaced and the variable OCA represents the additional charge which should be given to the battery during the third phase of charging less than the amount which has been given. Calculation of the variable OCA will be discussed with reference to the programme IDLCHR. If the result is zero this implies that the battery was completely charged during the previous charging cycle and a partial charge flag is reset. If the result is not zero this implies that the battery was not completely recharged and the partial charge flag is set.

After the programme DRVIDL has been entered, the time for which the idle period commenced is recorded, and then in an operation S41 a variable ECWD stored as a variable ALFA and the variable DEFLN is stored as the variable BETA. The variable ECWD represents the variable CWD corrected to take account of the rate at which the charge has been withdrawn and the calculation of this variable will be described with reference to the programmes DISCH and LKUPl. Finally, before a return from interrupt is performed, the interrupt mask is set so as to cause the signal PSUINHIBIT from interface 50 to go high in operation S21 of programme INTERS.

In Fig. 1 9 there is shown the flow chart for the programme IDLDRV. After this programme has been entered, a jump is made to the sub-routine SDCALC to calculate the self discharge which has occurred during the idle period and then a jump is made to the sub-routine MDCALC to calculate the present value of the variable DEFLN. The variables ECWD and DEFLN are then stored as the variables ALFA and BETA before a jump is made to the programme ADCONV.

In Fig. 20 there is shown a flow chart for the programme IDLCHR.

At the beginning of this programme, the sub-routine SDCALC is called to calculate the self discharge which has occurred during the idle period. Next, the variable CWD is examined. If this is greater than 5.33Ah then a variable FGK is set to ECWD/CWD, and if it is less than or equal to 5.33Ah, then the variable FGK is set to unity. The variable FGK is used in the programme STATE1 to calculate ECWD.

Next, in an operation S50, an AHL corrected flat is examined. This flag is explained below. If this flag is not set, then the programme jumps to an operation S51 but otherwise this flag is reset and the programme continues with an operation S52. In operation S52 the partial charge flag is examined and, if set, the programme jumps to operation S51. Otherwise, the programme continues with an operation S53 in which a variable CW is calculated as the average of its previous value and AHL/CWFT. The variable CW represents the charge capacity of the battery at 30 celsius, the variable AHL represents the actual capacity of the battery at the temperature at which it is being used, and the variable CWFT is a function of temperature used to calculate AHL from CW.As will be explained with reference to the programme DISCH, if during discharge the lowest sub-pack voltage falls below a certain value, then the variable AHL is calculated as a function of this voltage and as a function of the variable ECWD. The AHL corrected flag is set at the same time to indicate that this calculation has been performed. In operation S53 this new value of AHL is used to calculate the variable CW providing the battery has been fully charged during the previous charging cycle. Thus the value of CW is corrected and up-dated so that it corresponds closely to the actual capacity of the battery, which may be expected to fall during its working life. By correcting the value of CW the accuracy of the state of charge calculation is improved.

In operation S51, the status word CHWORD is sets to current level 6 and charging phase 1.

In an operation S55. a variable AHT is calculated. The variable AHT represents total cumulative discharge so far from the battery during its working life and it is used in the subroutine SDCALC. Then, in an operation S55, the variable OCA is calculated as a function of a constant K1, a constant K2, a variable SD representing the self discharge which has occurred, a constant K3, and a variable EOA which represents equalizing charge which is given to the battery at periodic intervals. Then, in an operation S56, the partial charge flag is examined and, if it is set, then the variable OCA is increased.

Next, in an operation S57, the sub-routine MDCALC is called and then the variable ECWD is stored as the variable ALFA and the variable DEFLN is stored as the variable BETA. Lastly, before jumping to the programme ADCONV, the variable DEFLN is set to zero.

Referring now to Fig. 21, there is shown the programme ADCONV. This programme is responsible for converting the various analog signals into digital form. At the beginning of this programme, the temperature of the system electronics is read and stored as a variable TELEC and then the temperature of the battery electrolyte is read and stored as the variable TBATT.

Next, the average and peak currents as sensed by the current measuring resistor 1 2 are read and stored respectively as variables CURR and IPEAK. Lastly, before jumping to the programme CHARGE, the sub-pack voltages are read and stored as variables SBPK1 to SBPK9.

During each pass through the one second routine, the programme CHARGE is executed followed by one of the programmes STATE1 to STATES, these programmes corresponding respectively to phases 1 to 5 of the charging cycle. The flow chart for the programme CHARGE is shown in Fig. 22 and will now be described.

After this programme has been entered, a test is made to determine if the charger is connected. If it is not connected, then the jump is made to the programme DISCH. If the charger is connected, then in an operation S60, a test is made to see if seven days have elapsed since the battery was given an equalizing charge. If seven days have elapsed, then the variable EQA is increased by a constant amount to ensure that the battery will be given an equalizing charge during phase 4 of the charging cycle. Next, in an operation S61, the sub-routine AVCURR is called and then a jump is made to an appropriate one of the programmes STATE1 to STATES.

Turning now to Fig. 23, there is shown the flow chart for programme STATE 1, which controls phase 1 of the charging cycle during which the charge withdrawn frm the battery is replaced.

As this programme is only executed at each eighth pass through the one second routine, a test is made in an operation S70 to determine if the present pass is an eighth pass. If it is not the eighth pass, then a jump is made to the programme SEND but otherwise the programme continues with operation S71 in which the sub-routine SPTST is called. In this sub-routine, the total battery voltage, the lowest sub-pack voltage, and the address of the sub-pack having the lowest voltage are found. Next, in an operation S72, a variable IEFF which represents the effective charging current is calculated from a variable AVCUR which represents the actual charging current by multiplying AVCUR by 0.95 which represents charging efficiency. In a modification of the system, the value which represent charging efficiency is a function of battery voltage.Then, the variable CWD is calculated by subtracting IEFF from the present value of the variable CWD.

As the state of charge of the battery is calculated during charging, it is necessary to calculate the variable ECWD. The variable FGK was calculated during the programme IDLCHR as ratio of ECWD to CWD and now, an an operation S74, ECWD is calculated by multiplying CWD by FGK. Thus ECWD falls linearly to zero with CWD.

In order to maintain the charging efficiency at a high value and also in order to avoid excessive gassing, the current level is reduced as charging proceeds in accordance with the amount of charge which remains to be replaced as represented by the variable CWD. In a set of operations S75 to S78. the variable CWD is examined. If CWD lies within the range of 10 to 20Ah then the current is reduced to level 5 and if it is less than 1 OAh then the current is reduced to level 3. Finally, before a jump is made to the programme SEND, in an operation S79 variable CWD is examined. If it is equal to zero, the status word CHWORD is set to charging phase 2 so that phase 2 of the charging cycle is executed during the next pass through the one second routine.

During phase 2 of the charging cycle the rate of voltage rise of the sub-pack found to have the lowest voltage at the end of phase 1 is examined and this phase is terminated when the rate of rise falls below a critical value. This phase ensures that the weakest sub-pack is fully charged.

This phase is controlled by the programme STATE2 and the flow chart for this programme is shown in Fig. 24.

There is an overall time limit of 11 8 minutes in phase 2 and after the programme STATE2 has been entered the time spent in phase 2 is tested. If 118 minutes have expired then the status word CHWORD is set to charging phase 3 and the jump is then made to the programme SEND. If 11 8 minutes have not yet expired, then in an operation S80 the sub-pack voltage LOWV is compensated for temperature. In order to do this, a temperature co-efficient equal to 6.5my/" celsius for each cell is used to normalise the lowest sub-pack voltage to 50 celsius.

LOWV represents the present voltage of the sub-pack found to have the lowest voltage at the end of phase 1.

Then, in an operation S81, the variable LOWV is averaged over 16 passes through the one second routine. Next, in an operation S82, this average value of LOWV is used to calculate the average rate of rise of the sub-pack voltage LOWV over 255 passes through the one second routine and in an operation S83 the value of this rate of rise is examined. If the rate of rise is less than the critical rate of rise, which is 2.54mV/ cell in four minutes sixteen seconds, then the status word CHWORD is set to charging phase 3 before a jump is made to the programme SEND.

Turning now to Fig. 25, there is shown the flow chart for the programme STATE3. This programme is responsible for controlling phase 3 of the charging cycle during which the battery is over charged by an amount determined by the variable OCA.

As this programme is only executed at each eighth pass through the one second routine, an initial check is made to see if the present pass is an eighth pass and, if not, a jump is made to the programme SEND. If the pass is an eighth pass, then in an operation S90, the variable OCA is decremented by the present value of the variable AVCUR. The variable OCA is then examined in an operation S91. If OCA is equal to zero, then the status word CHWORD is set to current level 2 and charging phase 4 so that phase 4 of the charging cycle is performed during the next pass through the one second routine. A jump is then made to the programme SEND.

After the battery has been discharged and then recharged in accordance with the charging phases controlled by the programme STATE 1, STATE2 and STATE3 some of the individual cells of the battery may not be as well charged as the other cells. In order to ensure that all the cells are fully charged and in order to avoid some of the cells becoming progressively less well charged with further discharging and charging cycles, an additional charge known as an equalising charge is supplied to the battery at periodic intervals. The supply of this additional charge is controlled by the programme STATE4, the flow charge of which is shown in Fig. 26.

As this programme is executed only at each eighth pass through the one second routine, an initial check is made to determine if the present pass is and eighth pass. If it is, then the variable EQA is decremented by an amount equal to the variable AVCUR and then, in an operation S100, the variable EOA is examined. If it is less than or equal to zero, then the status CHWORD is set to charging phase 5 and current level 1. Then, a jump is made to the programme SEND.

Turning now to Fig. 27, there is shown the flow chart for the programme STATES which controls the fifth and last phase of the charging cycle. This phase is the "READY" phase and charges the battery at current level 1 so that it is kept fully charged. In this programme STATES, the variable EQA is examined and, if it is equal to zero, a jump is made to the programme SEND. If it is not equal to zero, then the status word CHWORD is set to current level 2 and charging phase 4 so that the battery receives equalising charge during the next pass through the one second routine.

When the vehicle is being driven, the programme DISCH is executed during the one second routine in order to monitor discharge to the battery and also to decide if the armature current of the motor 14 should be limited. The flow chart for this programme as shown in Fig. 28 and this will now be described.

After this programme has been entered, the sub-routine SPTST is called to determine the lowest sub-pack voltage which is stored as the variable LOWV, the address of the sub-pack having the lowest voltage and the total battery voltage, which is stored as the variable TOTV.

The sub-routine VPCALC is also called to calculate the polarisation voltage and this is stored as a variable VPOL. In the next part of the programme beginning with an operation S110 the variables CWD and ECWD are calculated.

In operation S110, the variable CURR is examined to determine if the battery is being discharged, in which case this variable is negative, or if it is being recharged which will be the case during regenerative braking and in which case the variable will be positive. If the variable is negative, then in an operation S111 the sub-routine LKUP1 is called in which the variable IEFF is calculated and represents the discharge current adjusted in accordance with the rate of discharge. Then, the variable CWD is increased in accordance with the variable CURR and variable ECWD is increased in accordance with the variable IEFF.

If in operation S110 it was found that the battery was being charged, then the programme jumps to an operation S113. The total battery voltage is examined and a variable ETA which represents the charging efficiency is set accordingly. If the battery voltage is less than 260V, then ETA is set to 0.8, if it is between 260 and 280V, it is set to 0.4, and if it is greater than 280V it is set to 0. Then, in an operation S114 the variable IEFF is calculated by multiplying CURR by ETA. The variable CWD is then decreased by an amount IEFF and the variable CWD is likewise decreased by an amount IEFF. The programme then jumps to an operation S115.

Battery voltage falls more rapidly towards the end of discharge and becomes progressively more reliable parameter for estimating the remaining available charge of the battery. Also, insofar as end of discharge for the entire battery should be indicated before any of the cells go into cell reversal, the ultimate performance of the battery will be limited by the first cells to reach their end of discharge points. In the next part of this programme providing three conditions are fulfilled, the lowest sub-pack voltage is used to determine the remaining charge of the battery and this is used to calculate the remaining charge and the charge storage capacity.

The first condition is that the discharge current lies in the range 80amps to 100amps. This condition is examined in operation S112 and if the current lies outside this range a jump is made to the operation S115. If the current lies within this range, then the lowest sub-pack voltage is corrected in accordance with the electrolyte temperature, in an operation S116. This compensation is effected by normalising the value of LOWV to 30 celsius using a temperature co-efficient of 2.7my/" celsius for each cell. Then, in an operation S117, the variable LOWV is compensated to take account of polarisation voltage and in order to do this it is increased by an amount VPOL.

The next condition is that the lowest sub-pack voltage is less than 1 .9V/cell. In an operation S118 the lowest sub-pack voltage is examined and if it is greater than 1.9cell a jump is made to the operation S11 5. If it is less than 1.9cell then the programme continues with an operation S119.

The third condition is that the lowest sub-pack voltage represented by LOWV is less than the previous value of this voltage represented by the variable VLAST and this condition is examined in the operation 8119. If the lowest sub-pack voltage is not less than the previous reading, then a jump is made to the operation S115 but otherwise the programme continues with an operation S120.

Providing all the three conditions have been fulfilled the remaining charge is then calculated and stored in a location TEMP. A graph showing the relationship between the remaining charge and the lowest sub-pack voltage is shown in Fig. 29.

The charge storage capacity of the battery represented by the variable AHL is then calculated in an operation S121 by adding the variable TEMP and ECWD and storing the result as the variable AHL. The new AHL flag and the AHL corrected flag are then both set to indicate respectively that a new value for the charge storage capacity is available and that the value for the charge storage capacity has been corrected. The variable LOWV is then stored as the variable VLAST in an operation S122 before operation proceeds to operation S115.

In the last part of the programme DISCH commencing with the operation S115 a variable ILIM, which represents the maximum current which may be supplied to the traction motor 14, is calculated. In order to achieve this, in the operation S11 5, the remaining charge of the battery is examined and if it is equal to zero then the variable ILIM is set to zero before a jump is made to the programme SEND. Thus, if there is no remaining charge, the traction motor 14 is disabled. If the remaining charge is greater than lOamp-hours, then the variable ILIM is set to the normal maximum demand current of the motor 1 4.If the remaining charge is between 0 and lOamp-hours, then in an operation S123, the variable ILIM is calculated as a function of the variable TEMP in such a manner that the maximum current of the motor 14 is reduced linearly as the remaining charge falls from 1 Oamp-hours to Oamp-hours from the normal maximum value of 0.4 of this value. A jump is then made to the programme SEND.

By reducing the maximum motor current in this way, damaging discharge to the battery, which may result for example in cell reversal, is avoided, and at the same time the vehicle remains drivable during low states of charge.

Turning now to Fig. 30, there is shown the programme VPCALC in which the polarisation voltage is calculated and stored as the variable VPOL. It has been found that polarisation voltage is a complex function of time and current which may be expressed as follows: VP = 0.076 10.377 and r=29.3-4.71 in (1) where VP is polarisation voltage as time tends to infinity, T is the peak current, and T is the time constant.

The programme VPCALC calculates VPOL by simulating the filter shown in Fig. 30a. This filter uses constants K1 6 and K1 7 and also a variable VPLAST which are defined as follows: K17 = I 1T K16 =1 -K17 VPLAST = K16.VP + K17.VPOL Turning now to Fig. 31 there is shown a flow chart for the programme SEND. This programme is responsible for loading data into the output data stack for transmission to the interface 70 during the programme INTERR.

After this programme has been entered, in an operation S130 a test is made to see if the vehicle power is on. If the vehicle power is on then the variable ILIM is loaded into the output data stack so that the maximum demand current of the armature of the motor 14 will be limited if appropriate. If the vehicle power is not on, then the status word CHWORD is transmitted to the output data stack in order to control the charger 22.

Then, a check is made to see if ten seconds have elapsed since the last execution of ten seconds routine. If ten seconds have elapsed, then a jump is made to the programme FGCALC but otherwise a return from interrupt is executed.

Referring now to Fig. 32 there is shown the flow chart for the programme FGCALC. This is responsible for calculating the state of charge of the battery and storing the result as a variable DEFLN.

After the programme has been entered in operation S140 a test is made to see if the charger is connected. If the charger is connected, then a jump is made to an operation S141 but otherwise the programme continues with an operation S142.

In operation S142, the variable CWFT is calculated as a function of the electrolyte temperature. Then, in an operation S143 the AHL corrected flag is examined to see if the value of AHL has been corrected during the programme DISCH. If it has been corrected, then a jump is made to an operation S144. If AHL has not been corrected, then it is calculated in an operation S145 by multiplying the variable CW by the variable CWFT. The variable CW represents the charge storage capacity of the battery at 30 celsius. By multiplying this by CWFT, it is effectively derated by 0.8%/ celsius.

In the operation S144, the new AHL available flag is examined. If the flag is not set, then the sub-routine MDCALC is called to calculate the variable DEFLN before performing a return from interrupt. If a new value of AHL is available, then the present value of DEFLN is stored as variable BETA and the variable ECWD is stored as the variable ALFA before calling the subroutine MDCALC. As will be explained with reference to the sub-routine MDCALC this results in rescaling the meter 64 each time AHL is adjusted during the programme DISCH to avoid a discontinuity in the meter reading.

In operation S141 the variable ALFA is compared with a constant and, providing it is greater than this constant, the value of DEFLN is calculated as shown in the operation S146. in operation S146 "MAX" represents the value of DEFLN which corresponds to maximum deflection of the meter 64. If it is found in operation S141 that the value of ALFA is less than or equal to the constant, the operation S146 will not produce an accurate value to the variable DEFLN and so it is calculated instead as shown in operation S147. After DEFLN has been calculated, a return from interrupt is performed.

Turning now to Fig. 33 there is shown the flow chart for the programme AVCURR which calculates the average current during charging and stores this as the variable AVCUR. The value of AVCUR is calculated by totalling the value of CURR over eight passes through the one second routine.

In general, the charge which may be withdrawn from a battery decreases with increasing discharge current because of the selection of progressively more preferential reaction cites at the surfaces of the battery plates at high occurrence. In the programmes described above, the variable IEFF has represented the discharge current corrected to take account of the rate of discharge. Peukert has shown that the variable IEFF is related to the variable CURR as follows: IEFF = 12 (CURR/12)" where 12 is the current which will discharge the battery in two hours, and n is a constant having a typical value of 1.15 for lead-acid batteries.

The value of IEFF is calculated in the sub-routine LKUP1, the flow chart of which is shown in Fig. 34, on the basis of the above equation.

In Fig. 35 there is shown the flow chart for the sub-routine SPTST in which the voltage of the sub-pack having the lowest voltage is found and stored as the variable LOWV, the address of the sub-pack having the lowest voltage also being stored, and in which the total battery voltage, that is the sum of the individual sub-pack voltages, is found and stored as the variable TOTV.

During idle period, the battery will undergo self discharge and the flow chart of the subroutine SDCALC which calculates this is shown in Fig. 36. This sub-routine is performed at the end of each idle period.

After this sub-routine has been entered in an operation S150 the period for which the battery has been idle is calculated and stored as a variable SDT. Next, the variable AHT which represents total accumulative discharge of the battery during its life so far as examined and used to calculate a variable SDR representing the self discharge rate. If AHT is greater than 30000Ah, then SDR is set to a discharge rate of 4% of the total battery capacity per day, if AHT lies in the range of 1 5000 to 30000Ah then the variable SDR is set to the value which corresponds to 2% per day, and if it is less than 1 5000 then SDR is set to the value which corresponds to 1 % per day.

Then, in an operation S151, the self discharge which has occurred is calculated by multiplying SDR by SDT and storing the result as the variable SD. Finally, the variable SD is added to both the variables CWD and ECWD before a return from sub-routine is executed.

The flow chart for the sub-routine MDCALC which is called by the programme IDLCHR, IDLDRV and FGCALC which calculates the variable DEFLN is shown in Fig. 37.

After this programme has been entered, in an operation S160 the variable ALFA is sub-tracted from the variable AHL and the result is compared with a constant equal to 5.3Ah. If the result is greater than 5.3Ah, then the value of DEFLN is calculated as shown in an operation S161, before a return from sub-routine is executed.

The reason for the equation shown in operation S161 will now be explained with reference to Fig. 38. If DEFLN was simply calculated as being proportional to ECWD/AHL and discharge commenced with a full battery it would initially be set to a value corresponding to the maximum deflection of the meter 64. Then, if the value of AHL was initially AHL1, then the value of DEFLN would fall linearly with increasing ECWD as indicated by line 11. Then, if at point X a new value of AHL was calculated as AHL2, the value of DEFLN would jump from dl to d2. It is in order to avoid this jump that this equation is used. As the variables BETA and ALFA are set respectively to the present values of DEFLN and ECWD each time the value of AHL is corrected, the jump is avoided and the variable DEFLN is effectively rescaled.

Returning now to operation S160 if it is found that the result is less than or equal to 5.3Ah, then the equation shown in operation S161 cannot be used as the quantity (AHL-ALFA) is too small for accurate division. Instead the value of DEFLN is calculated as shown in operation S162 before the return from sub-routine is executed.

TABLE 1 PROGRAM STRUCTURE CONTROL PROGRAMS RESET INTERR POWRFAIL INTERRUPT PRO GRAMS 0.1 SECOND ROUTINE INTSERV 1 SECOND ROUTINE TRANS CHRTDL ADCONV CHARGE DISCH SEND DRVIDL STATE 1 VPCALC IDLDRV STATE 2 IDLCHR STATE 3 STATE4 STATE 5 10 SECOND ROUTINE FGCALC UTILITY SUB-ROUTINES AVCURR LKUP1 SPTST SDCALC MDCALC

Claims

1. A charging system for a battery including means for charging the battery according to a predetermined cycle, means reponsive to the battery current during charging and discharging for obtaining a value representing battery current, and means for integrating the current value with respect to time to obtain a value representing charge withdrawn, said predetermined cycle including a phase in which the battery is supplied with a charge equivalent to the charge withdrawn during discharge, the charging current depending during said phase on the charge withdrawn value.

2. A charging system as claimed in claim 1, in which during charging the current value is adjusted in accordance with a value representing the charging efficiency.

3. A charging system as claimed in claim 2, in which the value representing charging efficiency is a function of battery voltage.

4. A charging system as claimed in any one of claims 1 to 3, in which said system includes means responsive to the battery voltage and in which said charging cycle includes a second phase which is terminated when the rate of rise of the battery voltage falls below a predetermined value.

5. A charging system as claimed in claim 4, in which the battery is divided into a plurality of sub-packs, said second phase being terminated when the rate of rise of voltage of the sub-pack having the lowest voltage falls below a predetermined value.

6. A charging system as claimed in claim 4, or claim 5, in which the charging cycle includes a third phase in which the battery is given an overcharge.

7. A method of charging a battery including charging the battery in accordance with a predetermined cycle, measuring the battery current during charging and discharging to obtain a value representing battery current, and integrating the current value with respect to time to obtain a value representing charge withdrawn, said cycle including a phase in which the battery is supplied with a charge equivalent to the charge withdrawn during discharge, the charging current being dependent during said phase on the charge withdrawn value.

8. A method as claimed in claim 7, in which during charging the current value is multiplied by a value representing the charging efficiency.

8. A method as claimed in claim 7, in which during charging the current value is adjusted in accordance with the charging efficiency.

9. A method as claimed in claim 8, in which the value representing charging efficiency is a function of battery voltage.

10. A method as claimed in any one of claims 7 to 9, in which the method includes measuring the battery voltage and in which said charging cycle includes a second phase which is terminated when the rate of rise of the battery voltage falls below a predetermined level.

11. A method as claimed in claim 10, in which the battery is divided into a plurality of subpacks, said second phase being terminated when the rate of rise of voltage of the sub-pack having the lowest voltage falls below a predetermined level.

1 2. A method as claimed in claim 10 or claim 11, in which the charging cycle includes a third phase in which the battery is given an overcharge.

1. A system for monitoring a battery and controlling charging, said system including means for charging the battery, means for controlling the charging means so that charging is performed according to a predetermined cycle, means responsive to the battery current during charging and discharging for obtaining a value representing battery current, and means for integrating the current value with respect to time during both charging-and discharging to obtain a value representing charge withdrawn, said predetermined cycle including a phase in which the battery is supplied with a charge equivalent to the charge withdrawn discharge, during said phase the charging current being progressively reduced so that the instantaneous charging current is a function of the instantaneous charge withdrawn value.

2. A charging system as claimed in claim 1, in which during charging the current value is multiplied by a value representing the charging efficiency.

7. A method of monitoring a battery and controlling charging, said method including charging the battery in accordance with a predetermined cycle, measuring the battery current during charging and discharging to obtain a value representing battery current, and integrating the current value with respect to time during both charging and discharging to obtain a value representing charge withdrawn, said cycle including a phase in which the battery is supplied with a charge equivalent to the charge withdrawn during discharge, diring said phase the charging current being progressively reduced so that the instantaneous charging current is a function of the instantaneous charge withdrawn value.