GB2147126A - Improvements in and relating to computers - Google Patents

Abstract

Apparatus arranged to extend the operation of a computer having a single CRT display to enable it to communicate with at least one additional CRT terminal. The apparatus comprises a control apparatus 12 arranged to control the additional terminal and to interface it with the computer whereby data can be transferred between the computer and the additional terminal. <IMAGE>

Description

SPECIFICATION Improvements in and relating to computers This invention relates to computers and concerns apparatus arranged to extend a computer having a single cathode ray tube (CRT) display to enable it to communicate with at least one additional CRT terminal.

There are available many microprocessor controlled computers ranging from the simple home microcomputer which relies on the use of a television receiver as a monitor to quite complex microcomputers for home, office and scientific applications.

The more complex microcomputers are quite powerful in operation but if designed for use with a single CRT terminal and keyboard it is found that they are rarely tasked by their work load.

For this reason alone there is often a requirement for the computer to be adapted so that it can communicate with one or more additional terminals which can time share its facilities and thus avoid the more expensive expedient of buying a separate computer installation for each operator.

In addition, there is often a need for service operators to have access to common information and to modify or input more of such information; another good reason for a computer adapted to communicate with more than one terminal.

The present invention provides apparatus arranged to modify a computer having one CRT terminal to enable it to communicate with at least one additional CRT terminal, comprising a control means arranged to control the or each additional terminal and to interface the or each additional terminal with the computer whereby data can be transferred between the computer and the or each additional terminal.

Where the apparatus according to the invention is for modifying a computer having a microprocessor which is programmed in microcode stored in read only memory (ROM), the apparatus advantageously comprises replacement ROM programmed in microcode which may be substituted for the existing ROM, for controlling the microprocessor so that the microprocessor can handle the or each additional CRT terminal.

Advantageously, the replacement ROM is programmed to allocate part of the main memory in the computer as memory address locations for the or each additional terminal and the control means comprises a CRT control circuit for the or each additional terminal arranged to read information from the allocated main memory addresses in the computer and to generate therefrom video signals for the or each additional CRT.

The invention will now be described more particularly, by way of example, with reference to the accompanying drawings which illustrate apparatus arranged to modify a known single-CRT-terminal computer to a multiple-CRT-terminal computer. The known computer is the J500 computer manufactured by Jacquard Systems of California, U.S.A. Those skilled in the art will, appreciate how the invention may be applied to other single-CRT-terminal computers.

In the drawings: Figure 1 shows a block schematic diagram of the J500 computer with one embodiment of a control apparatus according to the invention adapting the computer to enable it to communicate with two additional CRT terminals; Figure 2 is a block schematic diagram of one embodiment of control apparatus according to the invention for use with the arrangement of Fig. 1; Figure 3 is a block schematic diagram of a circuit according to the invention for interfacing a CRT terminal and its associated keyboard with the control circuit of Fig. 1 or 2; Figures 4 to 14 show circuit diagrams of individual parts of the control apparatus of Fig. 2; and Figure 15 is an embodiment of an interface circuit for use in Figs. 1 and 3.

The embodiment of the invention to be described comprises a printed circuit control board and some controlling firmware arranged to allow two additional CRT terminals to be added to an existing single CRT terminal computer system such as a computer model J500 manufactured by Jacquard Systems of California, U.S.A. The J500 Computer extensively uses TTL Shottky Low Power Technology together with high density Bi-polar programmable read only memories. These form a compact 16 'bit-slice' microprogrammed processor and input/output (I/O) controllers on a single printed circuit board. The invention adds a second printed circuit board to the computer containing further l/O controller circuits for the additional CRT terminals. Also a modified and extended set of Bi-polar programmable read only memories is provided in order to control the extra circuitry.In addition to the above, another aspect of the invention also includes the design of a low cost CRT terminal to work in connection with the above. This was necessary as the l/O structure between the printed circuit board of the invention and the CRT terminal is of a non standard nature. A Coaxial cable is used to transmit the video picture to the CRT terminal for display and a multicore cable is used to send separate horizontal and vertical retrace signals to the CRT terminal. The multicore cable also carries the keyboard to the I/O controller in serial bit form. The J500 Computer I/O is a single CRT terminal 16 bit computer, and comprises dual flexible diskette drives, power supply, CRT screen and printed circuit logic board, in a single desk top housing.The printed circuit logic board contains the processor. main memory, microcode, flexible diskette controller, hard disk controller, two communications controllers, an auto-dialer controller, a keyboard and CRT controller, a printer controller, and various circuits for co-ordinating the operation of all these. The processor is quite powerful and is rarely fully tasked by the workload imposed from the single CRT terminal.

As aforementioned, in a situation requiring several operators to be working simultaneously, several machines had to be supplied in order for this to be possible. In addition, a major drawback to this was that multiple operators worki,#g on separate machines could not simultaneously access information contained on the same disk media, be it a flexible diskette or a hard disk cartridge. The present invention provides the means for several operators to simultaneously use a single processor such as the J500 and to access information on a single medium. The following description will be directed to a control apparatus which will enable a J500 Computer to communicate with two additional CRT terminals and their associated key boards.

The control apparatus 12 (Fig. 1) is mounted on a printed circuit board and will control two CRT terminals 14 and 16 of a specific type, and interface them with the bus structure of the J500 processor. Also the microcode within the main J500 processor is modified and extended, in order that the processor can transfer data between itself and the two controllers on the printed control circuit board for the two additional terminals. Furthermore each additional CRT terminal is so designed that an operator can enter and receive information to and from the J500 processor via the new controller.

The CRT terminal controller on the J500 is known as a "Memory Mapped" controller, meaning that the screen image is produced from a section of main Memory. This section of main memory is from Hex Addresses 'FCOO to FFFF'. This same technique is utilised by the Control circuit board 12, Main Memory addresses of Hex 'F400 to F7FF' and Hex F800 to FBFF are used for the two additional CRT terminals. The CRT controller sections of the control circuit board 12 consist of an L.S.I. CRT Controller I.C. integrated circuit 18 which is programmed to generate the video picture for the CRT terminal 14 or 16 from the information written into the above main memory addresses. Each time that the controller IC 18 generates a Memory address, sixteen bits of data are read from memory and encoded into sixteen dots to be displayed on the screen of the CRT terminal 14 or 16.These are then loaded into a shift register and changed into a bit serial format to be sent to the CRT terminal along line 20 for display.

The keyboard (not shown) attached to the CRT terminal 14 or 16 will send characters in a similar but slower bit serial stream along line 22, from the CRT terminal to the controller 12. In the controller 12 they are received by a universal asynchronous receiver transmitter (UART) l.C.

24 and converted into an eight bit parallel format for transfer to the J500 processor. Each time a a character is received from the keyboard an interrupt signal is generated by the control circuit board 12. This requests the main processor to accept the character from the controller 12.

In order that the Control board 12 interferes as little as possible with the operation of the processor 10, it contains some Random Access Memories, these contain a verbatim copy of the information to be found in the main memory addresses mentioned previously. The RAM's are updated simultaneously with the main memory each time the processor 'writes' to main memory but are not concerned with any read operations by the J500 processor.

The original J500 microcode has been modified and extended in order that it can handle keyboard interrupts from the M505 board and to enable the processor to have control of the cursor and data to be displayed on the M505 CRT terminals. The microcode is contained in 28 programmable read only memories which are Signetics 8251 85N or similar.

Each additional terminal 14, 16 consists of a power supply, CRT monitor, interface card and keyboard unit. The power supply and CRT monitor are standard products. The interface circuit card 25 (Fig. 1 5) is used to buffer the signals between the CRT monitor and the cable from the Control board 12. The card 25 contains only two i.c.'s, one to receive the CRT display signals and one to transmit the keyboard data.

The keyboard is a custom designed unit (such as manufactured by Alphameric Ltd of Woking, England) and is laid out in such a manner as to be similar in operation to the keyboard supplied with the J500 computer. The electronics of the keyboard convert the keycode into an eight bit ASCII character format and send this in serial bit stream, via the interface card 25, to the control board 1 2.

Sumbus Connections Referring now to Fig. 4, four 24 Pin Connectors mounted on the J500 Logic Board at locations 1 7B, 1 7C, 1 9B and 1 9C feed the sixteen sumbus signals onto a single 34 way ribbon cable. This cable connects to Connector J1 on the MPC 12.

Each of these signals is fed through a 270 ohm resistor (R1 to R16) on the MPC board 12, in order to reduce ringing. The sumbus is then buffered by two 74LS244 i/c's at locations U10 and U21 on the MPC, the output from these i/c's being the buffered sumbus, BSUM 0-15.

SBTMMR This signal is brought from position 40D on the J500 Logic Board to pin 8 of connector J4 on the MPC 12. It is then fed through a 270 ohm resistor R17 to reduce ringing. The signal indicates when a valid memory address is on the sumbus.

CLRACA- CAS- CAS. WRT These three signals are memory write control commands and enter the MPC at socket J3.

They are each fed through a 270 ohm resistor (R18 to R20) to reduce ringing.

Memory Address Decode and Write Control 26 (Fig. 5) U9 and U20 in conjunction with U55 are used to decode the start address of the CRT buffer, either X'F800 for CRT2 or X'F400 for CRT3. Pin 8 of the respective I/C going low in conjunction with SBTMMR- going low produces either F4MAL- or F8MAL- at U45 pin 12 or U45 pin 4 respectively. Either F4MAL- or F8MAL- going low will cause the respective memory address latch to be loaded with BSUMO-9. CRT2 Memory address latch comprises U30 and U42 whilst CRT3 latch comprises U29 and U41. If the J500 CPU is only performing a memory read cycle then nothing further will happen on the MPC during that cycle.

Flip Flop Circuit If BCAS.WRT- goes low, then U44 Pin 9 will go high as the flip-flop sets. This signal, through U36, will give the appropriate CPUACCESS- signal for the CRT concerned. The CPUACCESS- signal is used by the memory address multiplexer (MUX) (Fig. 6) 80 nanoseconds after BCAS.WRT- goes low, BCAS- goes low, and via the appropriate gate in U43 generates the signal BCAS.CPUACCESS. This signal loads the content of the sumbus into the memory data latch U30, U42 or U29, U41 for CRT2 or CRT3 respectively and also generates the appropriate WE- signal, via U35.

Memory Address Multiplexer 28 (Fig. 6) Three 74LS157 quad 2:1 multiplexer I/C's 26 to 28 and 38 to 40 are used for each CRT.

CRT2 uses U26, U27 and U28 whilst CRT3 uses U38, U39 and U40.

The A inputs are connected to the outputs of the appropriate memory address latch U30, U42, U29, U41, ADR0-9. The B inputs are connected to the LSI CRT Controller refresh signals, REFRI-10. The select input (pin 1) of each I/C, is connected to the respective CPUACCESS- signal. When CPUACCESS- is false (high state) then the memory address signals, ADR0-9, will appear on the output of the multiplexer. The signal CPUACCESS- will only be active during a memory write cycle.

CRT Buffer Memory 30 (Fig. 7) The CRT buffer memory consists of a 1024 location by 16 bits wide memory for each CRT.

This is made up from four 2114 type static RAM I/C's, US, U6, U16 and U17 for CRT2 and U3, U4, U14 and U15 for CRT3. The ten address inputs to each I/Care common and are connected to the signals A0-9 from the respective memory address multiplexer. The write enable pin on each memory I/C is connected to the respective WE- signal. The data lines are numbered l/0-0 to 1/0-1 5 and are used for both reading and writing data to or from memory.

Write Memory Data Latch 34 (Fig. 8) The buffered sumbus, BSUM0-1 5, is the input to the latch. In order to minimise the effect of noise pickup by the Jl cable and also to avoid the effects of ringing, the data on the sumbus is latched by the rising edge of BCAS.CPUACCESS. The memory write enable signal, WE-, is used to enable the output of the latch. CRT2 memory data latch comprises U8 and Us 9, CRT3 latch comprises U7 and U18.

Word to Byte Generator 36 (Fig. 9) As each 16 bit word is read from memory during refresh, it has to be split into two 8 bit bytes. This is achieved by using another multiplexer. For CRT2 this multiplexer comprises U1 and U 1 2 whilst for CRT3 it comprises U2 and U 1 3. The 16 bit word split across the multiplexers and REFRO is used to gate out the correct byte onto the D0-D7 lines. The multiplexer outputs can be disabled by the BLANK- signal. This is used to prevent memory write data from causing spurious video signals.

Display Control Logic 38 (Fig. 10) The display enable signal, DISPEN, has to be synchronised before it is suitable for providing the video window in this circuit. This is done by flip flop U46 for CRT2 and flip flop U49 for CRT3. When DISPEN goes high the signal NEWDISPEN is synchronised to the first character being loaded into the video shift register and, likewise, the signal NEWDISPEN will not go low until the last character has been fully displayed. During a CPU write cycle the appropriate CPUACCESS- signal will set the respective half of flip flop U48. This will cause the remainder of the character scan to be blanked. The flip flop will be cleared by the next SRLOAD signal.At the start of each display character the BYTECLOCK, via U43 will set flip flop U49 and cause the signal SPLOAD to be generated. 100 nanoseconds later the signal IDIOT clears the flip flop 49 and SRLOAD goes low again.

Character Generators 40 (Fig. 11) These are similar to those used on the System J500 in order to create similarity of display characters. Each character byte from the word to byte generator 36 addresses the character generator 40 along with the horizontal scan signals from the LSI CRT controller 42 (Fig. 14).

Ten horizontal scans per character row are used, the same as the System J500. Enabling of the 2516 and 28S42 character generators U11 and U22 is also similar to the System 5500. where the first 8 scan lines are provided by IC. 2516 at position Us 1. (U25 for CRT3) and the last two scan lines by the I.C. 28S42 at position U22 (U24 for CRT3). The gating for switching between these two i/c's is contained in U35 and U36 (U37 for CRT3). The shift register for producing the video signal is U34 for CRT2 and U23 for CRT3. The register is loaded by the SRLOAD signal together with the rising edge of the DOTCLOCK signal. The 8 bits are then shifted out by DOTCLOCK. The resultant video signal is called CRTDOTS.

Unlike the System 5500. Data bit 7 is also connected to the character generator chips 40 and there is no interlace facility. The locations in the character generator 40 corresponding to the character codes from X'80 up to X'FF are all set to zeros in the standard chip set. This allows for user defined fonts to be programmed into the controller 1 8.

Keyboard data reception and Interrupt generation 44 (Fig. 12) A matching system of a DIL crystal oscillator and a Baud rate generator at positions U62 and U60 are used to produce 300 baud rate clocks to achieve compatability with the Jacquard Computer System J500. The Baud rate generator produces two clocks for the CRT UART's at locations U32 and U53. These chang#e the serial data from the Keyboard into 8 bit parallel data.

Once the 8 bits per character are received, DRECD goes high and loads the keyboard character into the keyboard data latch, U33 for CRT2 and U54 for CRT3. This signal is synchronised with the vertical refresh signal from the CRT controller i/c to allow Interrupt to the System J500 to occur only during vertical refresh time. This is to reduce the effect of Memory write flicker on the CRT screen. CRTKBDINT- goes low and enters the System J500 board via connector J4.

The microcode sets GATEKBD- low in reply. This resets DRECD from the UART and places the keyboard character onto DO-7. The character goes via the J2 cable to the J500 board at location 22J and then through a driver i/c at location 21J and onto the IDB. The microcode places this character into ACO lower byte and forces a CRT buffer start address of F8 or F4 into ACO higher byte. PWRRST- from the system is used as a master clear signal to both CRTs, the two LSI CRT Controllers and the two UART's.

VDU Interface 46 (Fig. 13) Cable driver I/C's at locations U56, U57 and U58 are used as current drivers for the various signals to each CRT screen. This creates compatability with the Jacquard system J500 product where cable runs of 1000 feet are possible. All of the CRT signals are connected to the CRT Connector Board (CCB) via cable J5.

LSI CRT Controllers 42 (Fig. 14) A DIL crystal oscillator of 16 MHz produces the DOTCLOCK signal timing which clocks the shift registers to produce video. A divide by 8 counter in U50 produces the byte clock for each of the LSI CRT controller I/C's. These I/C's, at positions U31 and U52, produce the refresh addresses necessary for the reading of CRT Buffer memory. They also produce Vertical synchronisation and Horizontal synchronisation, Display enable (valid data displayed area) and cursor position information. Horizontal scan count is controlled by RAO-3 to count 10 scans per character row. The LSI I/C's require parameter loading on power-up in order to specify the options listed on the next page. The parameters enter the LSI I/C's via DO-7. These are tristate lines fed from IDBO-7 on the System J500. The LSI I/C's have 16 major registers and one address (pointer) register each. When V44(RS) is low the DO-7 bus will be written into the LSI I/C. The cursor is controlled by the new microcode of the System J500 where each DOC command places the contents of ACO into the respective CRT Controller I/C register.

REGISTER USAGE HEX CONTENTS RO Horizontal Total 63 R1 Horizontal Displayed 50 R2 Horizontal Sync. Position 52 R3 Horizontal Sync. Width OF R4 Vertical Total 18 R5 Vertical Total Adjust 00 R6 Vertical Displayed 18 R7 Vertical Sync. Position 18 R8 Interlace Mode 00 R9 Max Scan Line Address 09 R 10 Cursor Start 48 R11 Cursor End 08 R12 Start Address High 00 R 1 3 Start Address Low 00 R14 Cursor High 00 R15 Cursor Low 00

Claims (14)

1. Apparatus arranged to modify a computer having one CRT terminal to enable it to communicate with at least one additional CRT terminal, comprising a control means arranged to control the or each additional terminal and to interface the or each additional terminal with the computer whereby data can be transferred between the computer and the or each additional terminal.

2. Apparatus according to Claim 1 for modifying a computer having a microprocessor which is programmed in microcode stored in read only memory (ROM), the apparatus comprising replacement ROM programmed in microcode which may be substituted for the existing ROM, for controlling the microprocessor so that the microprocessor can handle the or each additional CRT terminal.

3. Apparatus according to Claim 2, in which the replacement ROM is programmed to allocate part of the main memory in the computer as memory address locations for the or each additional terminal and the control means comprises a CRT control circuit for the or each additional terminal arranged to read information from the allocated main memory addresses in the computer and to generate therefrom video signals for the or each additional CRT.

4. Apparatus according to any one of the preceding claims in which the control means receives information from the computer in parallel format and converts it to serial format for transmission along a transmission link to an additional CRT for display.

5. Apparatus according to any one of the preceding claims, further comprising an asynchronous receiver transmitter (UART) for receiving information transmitted in serial form along a transmission link from a keyboard of an additional terminal and then converting the information parallel format for transfer to the computer under the control of the control means.

6. Apparatus according to any one of the preceding claims, wherein the control means is connected to the bus structure of the computer and further comprises means for generating and transmitting an interrupt signal to the computer to request the computer to accept a character generated by the keyboard of the or any associated additional terminal.

7. Apparatus according to any one of the preceding claims comprising random access memory arranged to store a copy of the information contained in the allocated main memory addresses, and arranged to be updated with the main memory each time the computer writes information into the main memory.

8. Apparatus according to Claim 7, comprising a large scale intergrated circuit programmed to read the contents of the random access memory and to provide therefrom a video display signal at the or an additional CRT terminal.

9. Apparatus according to any one of the preceding claims including a transmission link between the computer and the or each additional terminal, the transmission link comprising (1) a co-axial cable for transmitting video pictures to the CRT, and (2) a multicore cable for (a) transmitting horizontal and vertical retrace signals to the CRT and (b) for transmitting signals from the keyboard to the computer.

10. Apparatus according to Claim 9, in which the or each transmission link includes one or more current drivers.

11. Apparatus according to any one of the preceding claims, in which most of the components of the apparatus are mounted on a single printed circuit board.

12. Apparatus arranged to modify a computer having one CRT terminal to enable it to communicate with at least one additional CRT terminal, substantially as hereinbefore described with reference to and as illustrated in Fig. 2 or Fig. 2 and Figs. 4 to 14 of the accompanying drawings.

13. An interface circuit for interfacing apparatus according to any one of the preceding claims and an additional terminal, substantially as hereinbefore described with reference to and as illustrated in Figs. 2 and 3 or Figs. 2, 3 and 15 of the accompanying drawings.

14. A computer installation comprising a computer modified to communicate with at least one additional terminal comprising apparatus according to any one of the preceding claims.