GB2146874A - Decoding of minimum redundancy codes - Google Patents

Abstract

A decoder for decoding variable length codes of the type having a first group of n identical bits and a second group of m bits which can be different. The decoder includes a counter 23 which counts the number of n bits in each code word and shift register 24 which receives successive bits of each code word. The outputs of the counter and the shift register provide address signals for a ROM 25 in which are stored decoded values of the codewords. The decoded value is read directly from the ROM. <IMAGE>

Description

SPECIFICATION Decoding of Minimum Redundancy Codes This invention relates to the decoding of minimum redundancy codes. The invention has particular but not exclusive application to the decoding of the variable length Huffman codes used in facsimile systems.

The implementation of a coding method using variable length codes does not usually present any problems. However, the decoding process is generally regarded as being much more difficult, pafticularly for large code tables, and as a result such coding methods have not been used widely until recently. The present invention relates to a decoder which is economic to construct, very reliable in operation and capable of operating atthe very high speeds which are now available on some of the new data networks. The decoder was specifically designed to be incorporated in high speed Group 4 facsimile terminals (currently being standardised in CCITT). However, the decoder can be used in a wide range of systems, for example, in systems in which documents have been coded for storage and a decoding system is required so that they can be displayed.A particular advantage of this decoder is that documents scanned at high resolution can be decoded in a few seconds.

There are two main methods of decoding variable length codes, namely tree-followers and look-up decoding methods. Tree-follower decoders make use of the fact that Huffman codes have a structure similar to a tree. Hence, one way of decoding these codes is to construct an array of logic circuits which correspond to the structure of the particular code to be decoded. The decoding method consists of applying successive bits from the coded data stream to the array so that a particular path through the nodes in the logic tree is activated. When a terminal node is reached, a particular codeword has been found and can be identified. The main disadvantage of this method is that the logical arrays can be large and complex for large code tables and the decoder may be slow to operate. However, an advantage of this method is that it provides instantaneous decoding of the codewords.That is, each codeword is decoded when the last bit of each codeword is delivered to the decoder and the decoding process for the next codeword can begin immediately. An example of a decoder using this method is given in U.S. Patent No. 3 918 047.

In look-up decoders, the basic decoding technique is to apply a fixed length segment of the coded input stream to the address input lines of a read-only memory device. The length of the code segment is usually equal to the longest codeword to be decoded. The memory can then be programmed to provide the decode value immediately. In effect, the memory is programmed by making use of the prefix property of Huffman codes. The prefix property relates to the fact that no codeword in a particular Huffman code table is the prefix (i.e. forms the first few bits) of any other codeword in the same table.

This means that a sequence of coded bits will always be decoded into a specific set of decode values. A look-up decoder operates by allocating to each codeword a particular section of the memory so that when the bit sequence of the codeword is applied to the most significant address line of the memory, the decode value of that codeword always appears on the output of the memory. The prefix property always ensures that a unique output always occurs for each codeword irrespective of the coded bits which follow each codeword.

An advantage of this method is that the decode value is provided immediately; however in this decoding method the length of the codeword decoded is not known. Hence, an additional memory device must be included in the decoder to provide information relating to the length of each codeword in the code table. So the decoding method in practice consists of applying a fixed length code segment to two memory devices, one containing the decode values and the second the codeword length information. Then, when a codeword has been decoded, the length information is used to 'clock on' or reposition the coded data stream in preparation for decoding the next codeword. The main disadvantage of this method is that large memory devices are required for large code tables. For example, if the longest codeword in a code table is 13 bits, then two memory devices are required each with 213=8192 locations.It is possible to reduce the amount of memory required by using a hierarchy of memories consisting of a primary memory and several secondary memories. The size of the code segment is reduced and the primary memory is used for short codewords but for decoding codewords longer than a certain size both the primary and secondary memories are required.

However, this adds complexity to the system and reduces the speed of the decoder. U.S. Patent Nos.

3 883 847 and 4 228 467 give examples of designs using the direct look-up technique.

According to the present invention there is provided a decoder for decoding variable length codes of the type having a first group of n identical bits and a second group of m bits which can be different, the decoder comprising means for counting the number of n bits in each codeword to provide an output representing said count, shift register means for receiving successive bits of each codeword, said counter output and said register output providing address signals for memory means in which are stored decoded values of said codewords whereby when the address signals represent a recognisable codeword the corresponding decoded value is output from the memory means.

When the decoded value is output the shift register and counter are cleared for the next codeword.

The memory means may be a ROM.

The invention will be described now by way of example only with particular reference to the accompanying drawings. In the drawings: Figure 1 is a block schematic diagram of a facsimile receiver incorporating a decoder in accordance with the present invention; Figure 2 is a block schematic diagram of a decoder in accordance with the present invention; Figure 3 is a detailed circuit diagram of a decoder in accordance with the present invention.

The decoder to be described has been designed to decode Huffman codes. These are varaible length codewords which have the general structure .... . O,A, .. . Am. That is each codeword comprises a series of leading zeros which can have any length from zero to n followed by the sequence A1... Am where A can be 0 or 1. Additionally the particular complete sequence of bits which make up a given codeword is not a prefix of any other codeword.

Those skilled in the art will appreciate that the codewords in the case of facsimile transmission systems can be terminating codewords, make-up codewords or end of line codewords.

Referring now to Figure 1 a facsimile receiver comprises a peripheral interface card 10, a decoder interface 11, a decoder 12 and a receiver peripheral 14 such as a printer. The decoder 12 is designed to decode information coded using the onedimensional run-length coding algorithm using a modified Huffman code which is specified in CCITT Recommendation T.4. One specific application of the decoder is in a high speed facsimile receiver. In this case the peripheral circuit card is a network interface system, which controls the data stream arriving on the transmission line from a transmitter and processes it so that it is in a suitable form for presenting to the decoder circuitry. Also, in this application, the receiver peripheral is likely to be a printing device. Another application for the decoder is for decoding documents which have been coded and stored in a computer archive system.In this case the peripheral interface card may be a computer interface and the receiver may be a visual display unit or printer or some other form of storage medium such as a disc drive. The following describes the control signals which flow to and from the decoder circuit to the peripheral systems by means of an interface circuit.

Referring to Figure 1, the flow of the coded data into the decoder 12 from the peripheral circuit card and the flow of the decode values to the receive peripheral are controlled bythe interface circuit 11.

When the decoder is in the idle state, the interface circuit 11 inhibits the clock pulses to the decoder and transmits a "decoder ready" signal on line 15 to the peripheral interface card 10. The peripheral card then provides the next 8 bits of the coded data stream, which is called a code segment, on lines 16 and latches them in parallel into the decoder. When the bits in this segment are valid, a pulse appears on the "code segment available" line 17. This causes the clock pulses to be switched into the decoder which then begins to decode the code segment, as will be described below.

The clock pulses now continue until one of two events occur, either of which cause the clock pulses to the decoder to be halted temporarily. Firstly, if a terminating codeword is generated, the decoder applies a "run-length ready" (RLRDY) signal on line 18 to the interface and this inhibits the clock pulses, preventing the decoder from processing any further data. When the receiver peripheral has processed the decode value, it transmits a "run-length taken" signal to the interface 11 and this generates a clear pulse CL2 which is used to clear the output latches in the decoder circuitry as will be described later. In addition, this signal re-enables the clock and the decoder begins to decode the next codeword.

Secondly, the clock pulses to the decoder circuit 12 are turned off when all 8 bits of a code segment have been processed. This situation is detected by the interface circuitry 11 which inhibits the clock pulses and issues a "decoder ready" signal to the peripheral card 10. As a result, a further code segment is latched into the decoder 12, as described above, and the decoding process continues.

The decoder to be described below has features of both the tree decoding method and the direct look-up decoding method. That is, a memory device is used to store the decode values and coded data is presented to the input address lines of the memory one bit at a time until a valid decode value is found.

The decoding method makes use of the fact that each codeword in a Huffman code table has the structure 1 . . ....... Am. Thus each codeword is considered to be made up of a sequence of leading 'zeros' O, . . . n, which can have a length of between zero and n, followed by a sequence A1... Am, which characterises each particular codeword and which consists of a sequence of "1's" and "0's" having a length of between zero and m. One codeword in the code table will consist of all "0's" (such a codeword exists in all Huffman code tables) and, in the above notation, this codeword will consist of a sequence of n "0's" and Awl . . . Am is a null string for this codeword. In effect, this codeword defines the maximum value of n.

The decoder operates by first applying the coded data sequence to a counter to determine the number of leading zeroes in the bit sequence. This value is applied to certain specified address lines of a memory device instead of the leading zeroes themselves. The subsequent coded bits from the data stream are then presented to the remaining memory addresses of the memory device one bit at a time until a valid decode value is found. As each successive bit is presented to the memory, the bits previously presented are moved by one bit towards the least significant address lines by means of a shift register. A decode value is provided instantaneously when the final bit of a codeword is presented to memory.

The decoder has two main features. First the method of counting leading zeroes enables the size of the memory to be reduced compared with the memory size required by a direct look-up decode method. The amount of reduction depends upon the particular code and can be substantial for long code tables with long codewords. For example, if the maximum values of n and m for a particular code are 7 and 4 respectively, then a direct look up decoder would require a memory of 211=2048 locations. However, using the above technique, the size of memory required is 8x24-128, which is a reduction by a factor of 16. Secondly each codeword is decoded instantaneously since it is possible to decode each codeword in a sequence of codewords without reference to succeeding code symbols.

After each codeword has been decoded, the decoder is immediately ready to start decoding the next codeword and this is useful in applications where speed of operation is important. Also this arrangement means that a second memory device to store codeword length data is not required.

The decoder comprises a parallel-in-serial-out (PISO) shift register 21, an R-S flip-flop 22, a counter 23, a serial-in-parallel-out (SIPO) shift register 24 and a read-only-memory (ROM) 25. In this particular circuit, by way of an example, the counter 23 is a three bit counter and the SIPO 24 has 8 parallel output bits. In any particular installation, the size of this counter and SIPO will depend upon the specific Huffman code to be decoded as will become apparent below.

The operation of the decoder is as follows. Data is input into the decoder in the form of code segments, which consist of blocks of 8 coded bits, under the control of the interface circuit, as has been described above, by means of the PISO 21. A code segment may consist of two or more concatenated codewords or part of a much longer codeword.

Coded data is then clocked one bit at a time from the PISO 21 into the decoding circuitry using the clock pulses CLK. A codeword such as '001011' is fed into the decoder in the bit order 0, 0, 1,0, 1, 1, i.e. from left to right as written. When a previous codeword has been decoded, a clear pulse CL is used to clear (i.e. set to logical level "0") the outputs of the counter 23 and the SIPO 24. In addition, a clear pulse CL is applied to the R-S flip-flop 22 so that the Q output of this circuit element is set to a level which enables counter 23. The decoding circuitry is now ready to decode the next codeword.

On the rising edge of the next clock pulse CLK, the next bit of the coded data stream DA (i.e. the first bit of the next codeword to be decoded) is fed into the SIPO 24 so that it appears on the first output line OA of the SIPO and is also fed into the R-S flip-flop 22. If the data bit is of level "0" then the flip-flop 22 remains set and counter 23 remains enabled. In this case, the output of the counter is incremented by one on the falling edge of the same clock pulse CLK.

On the other hand, if the data bit is a "1" the R-S latch 22 will be cleared causing the counter to be disabled. This prevents the counter from being incremented on the falling edge of the clock pulse and this counter will only be re-enabled by the clear pulse CL after the current codeword has been decoded.

The outputs of the counter 23 and the SIPO 24 form the address lines of the read-only-memory (ROM) 5. This ROM has a number of output data lines 26 upon which the decode values appear and a single output line 27, labelled VDC in Figure 1, which changes state when a valid codeword has been detected. This change of state is detected by the interface circuit 11 (Figure 1) which inhibits the operation of the decoder by stopping the clock pulses, processes the decode value on the outputs of the ROM and then issues a CL pulse to the decoder in preparation for the next decoding operation.

If a codeword is not detected after the input of the first bit to the SIPO 24, the next bit from the code data stream is input into the SIPO 4 and appears on output line OA. At the same time, the data bit previously on OA is shifted to the output line OB. In addition, the counter 23 will be incremented again according to the logical level of the bit and according to whether the counter is enabled or not as described above. Again if a codeword is not detected, a further bit is input into the decoder and this process continues until a codeword is recognised and a corresponding decoded value is output on lines 26.

In Figure 2 the address lines to the ROM are connected as follows. The most significant bit (MSB) of the counter 23 is connected to the most significant address line of the ROM. The next MSB of the counter is then connected to the next most significant address line of the ROM and so on until all the outputs from the counter have been connected. Following this, the first output line OA from the SIPO 24 is connected to the most significant remaining address line of the ROM. This is followed by connections from OB, OC, and so on, to the address lines of the ROM until all outputs are connected to the address lines of the ROM in most significant order. This particular connection order has been made since it makes the programming of the ROM as easy as possible. However, the order of connection does not have to follow this scheme and any order can be used as required by the designer.

Thus it will be seen that by making use of the structure of the Huffman codes it is possible to construct a decoder whose memory requirement is considerably less than conventional look-up decoders. Furthermore, by making use of the shift register 24 the decoder has the tree-type device feature of providing instantaneous decoding.

Figure 3 shows in detail a decoder for decoding run-length values coded using the modified Huffman code tables adopted for Group 3 facsimile equipment as specified in CCITT Recommendation T.4.

The basic circuit elements of the decoder circuit shown in Figure 3, i.e. elements 22, 23 and 24 are the same as shown in Figure 2. However, as will be described in detail below, in Figure 3 the counter 23 is a 4 bit counter, there are additional connections to the ROM 25 and the least significant output line of the SIPO 24 is fed into the ROM via an OR gate 30 which is also connected to the most significant output line of the counter. Also, the circuitry in Figure 3 provides three additional functions which will be described below. It enables black and white decoded run lengths to be distinguished and latches are provided to separate make-up and terminating codewords. Also the circuit includes a means for detecting end-of-line (EOL) codewords so that the first bit of the coded data stream relating to the start of the next scan line can be determined.

The ROM 25 is a 4096x8 bit device having twelve address lines labelled..... All and eight data lines labelled DO... D7. The address lines A0 . . . A6 are connected to the outputs OG . . . OA of the SIPO 24 and the address lines A7 . . . Al0 are connected to the counter 23. The output OH of the SIPO is connected to the address line A10 through the OR gate 30. The most significant address line All is connected to a black/white selector, which comprises a flip-flop 32. As stated earlier, the order of connection of the ROM address lines is not significant except for the fact that it makes it easier to assemble the decode data to be inserted in the ROM. Six of the data output lines DO . . .D5 (DO is the least significant bit) of the ROM 25 are connected to the inputs of both a make-up codeword latch 33 and a terminating codeword latch 34. The outputs of the two latches form a 12 bit word CO . . . C11 (CO is the least significant bit) which is the binary representation of each decoded run length value. The decode data relating to the two modified Huffman code tables representing black and white runs is stored in two separate areas of the ROM and, for each decoding sequence, the appropriate area of ROM is selected by means of a signal from flip-flop 32 as will be described below.

Flip-flop 32 also provides an output on line 36 which indicates the colour of the run (i.e. black or white).

The remaining two output lines from the ROM 25 D6 and D7 which are also labelled VDC and MU respectively in Figure 4 are connected to flip-flops 40 and 41. Normally VDC is at level "0", but when a valid codeword has been detected by the ROM, VDC changes to the level "1 ". MU is at level "0" when a terminating codeword is detected and at level "1" when a make-up codeword is detected. Hence MU is used together with VDC to indicate when and which type of codeword has been detected. The flip-flops 40 and 41 are then used to control the feeding of the decode values into either latch 33 or latch 34 as will be described below.

At this point the reasons for using a 4-bit counter in the position of counter 23 will be explained. The decoder in Figure 3 decodes codewords using the R-S latch 22, the counter 23, the SIPO 24 and the ROM 25 in the same manner as described for Figure 2. The structure of the modified Huffman code specified in CCITT Recommendation T.4 is such that no codeword in the code tables have a prefix consisting of more than 7 consecutive '0's' and hence these code tables could be decoded by using a 3-bit counter in the position of counter 23.

However, because the code tables include a special sequence of bits to designate an end of a scan line, namely the EOL code word '000000000001' as will be described later, the decoder must also be able to recognise and deal with the sequences '000000001', '0000000001' and '00000000001'. No valid codewords have these sequences as a prefix but they may be produced, by chance, as a result of a transmission error. Thus counter 23 is increased to become a 4-bit counter (as shown in Figure 3) in order to detect the occurrences of these sequences and 3 memory locations in ROM 25, which are not required to contain decode data relating to other codewords, are reserved to decode these sequences.This is achieved by connecting the most significant bit (MSB) output of counter 23 to one of the ROM address lines (in this case Al 0) via the OR gate 30, which is also connected to one of the output lines of SIPO 24 (line OH in this case). This arrangement ensures that no increase in memory size is necessary as a result of increasing the size of counter 23. The action to be taken when these invalid sequences occur is dependent upon the particular application. In this installation the ROM 25 is programmed to indicate that a run length of zero length has occurred.

The operation of the black-white selector (flip-flop 32), the ROM 25 and the end-of-line (EOL) detection circuitry will now be described in more detail. At the beginning of each coded scan line, the flip-flop 32 is cleared (the output is set to "0") by NAND gate 44.

This occurs whenever an EOL codeword is detected, as will be described in later paragraphs. Clearing the flip-flop 32 causes its output to select the area of the ROM 25 which contains the decode data relating to the white run length code table. This is required since the first run on each line is always a white run.

After every subsequent terminating codeword has been decoded, the flip-flop 32 is toggled (i.e. its output level is changed from "0" to "1" or vice versa) by means of an AND gate 46 and the output of this AND gate is used to select the appropriate area of the ROM for the next decoding sequence.

That is, the selected area is changed from that relating to the white runs to that relating to the black runs or vice versa. This is because the coded data stream consists of alternate black and white run lengths.

Each decoding sequence involves either the decoding of a single terminating codeword or the decoding of two codewords from the same (i.e.

black or white) code tables, namely a make-up codeword followed by a terminating codeword. A decoding sequence ends when a terminating codeword has been detected. When a codeword is detected, VDC goes to level "1" and the Q output of flip-flop 40 goes to level "1" on the next clock pulse CLK. If MU is "0", indicating a terminating codeword, then the Q output of flip-flop 41 becomes a "1" and the output of AND gate also goes to level "1". In this case the output of the AND gate 11 remains at "0". Thus the decoded value at the ROM outputs is fed to the latch 34. However, if MU is a "1", then the output of AND gate 10 remains at level "0", the output of AND gate 11 changes two level "1" and the decode data if fed to the latch 33.

After every make up or terminating codeword has been decoded, circuit elements 22,23 and 24 are cleared using pulse CLl,which is generated by a flip-flop 50. When the valid decode signal VDC goes high, the flip-flop 50 is enabled and its Q output changes from level "0" to level "1" on the falling edge of the clock pulse CLK. When the outputs of counter 23 and SIPO 24 are cleared to level "0", this causes VDC to change to level "0" and clears flip-flop 50 in preparation for the next decoding operation. Latches 33 and 34 and flip-flops 40 and 41 are cleared using the clear pulse CL2 at the beginning of the next decoding sequence. This pulse is generated by the interface circuit when it receives a "run-length taken" pulse from the receiver peripheral.

The decode values contained in the ROM 25 are as follows. If a terminating codeword is detected, then the decode value consists of the binary representation of the run length indicated by that codeword. However, if the codeword is a make-up codeword, the decode value consists of the binary representation of the make-up value divided by 64.

For example, if a codeword corresponding to the make-up run length value 64 is decoded, then the output sequence C10 . . . C6 would be "00001" and if the decode value is 128 then the output sequence would be "00010". Concatenated to these sequences would be a sequence C5 . . . CO which indicates the terminating value. Thus, the complete sequence C10 . . . CO represents the binary equivalent of the decoded run length and this can be passed to the printing mechanism without further processing.

The circuit also includes an end-of-line (EOL) codeword decoder which comprises a counter 60, NAND gate 61, R-S flip flop 62 and the NAND gate 44 and operates as follows. Just before a new coded line is to be decoded, the Q output of flip-flop 62 is set at level "1" by a pulse CL3. Data from the coded data stream DA is inverted by an inverter 66 and fed, one bit at a time, into the clear and enable inputs of the counter 60. If DA is at level "0", (i.e. DA the output of 66 is at level "1"), the counter is incremented on the next clock pulse CLK. If DA is at level "1", the outputs of the counter are cleared (set to level "0") and are not affected by the next pulse CLK. If the output of the counter attains the state "1011" (decimal value 11), then the output of the NAND gate 61 changes state to level "0".This causes the 0 output of the flip-flop 62 to change to level "0" and the outputs of the counter 23 are loaded with the state "1111". The state of the flip-flop 62 cannot be altered by any subsequent change in the level on DA. At this point all the outputs of the SIPO 24 are at level "0".

The last bit of the EOL codeword (which is a "1") must now be detected by feeding further bits from the coded data stream DA into the decoding circuitry 22, 23 and 24 until a 1 appears on output line OA of the SIPO 24. The ROM 25 is programmed to recognise this condition (i.e. "1111" on the output of counter 23, "1000000" on the output SIPO 24, ROM address All level immaterial) as the end of an EOL codeword. At this point, VDC changes to level "1" and a "1 " appears on the 0 output of flip-flop 40. As a result the output of NAND gate 44 goes to level "0" from its normal level of "1" and causes the Q output of a flip-flop 66 to change to level "1", indicating that an EOL codeword has occurred. In addition, NAND gate 44 clears flip-flop 32 in preparation for the start of decoding for the next line.The EOL codeword is regarded as a terminating codeword by the decoder so that the appropriate clear pulses can be generated in preparation for the next decoding. It is the responsibility of the receiver peripheral to ensure that the appropriate action is taken when an EOL is detected.

Afeature of the EOL detector is that counter 60 is arranged so that it can count sequences of "0's" anywhere in the coded data stream and is cleared by a "1". If a sequence of 11 "0's" is detected then, in effect, an EOL is deemed to have been detected. The decoder itself is then used to determine the exact position of the EOL codeword in the data stream.

This has two important consequences.

First, the EOL codeword detector used in this installation is designed to detect the unique EOL sequence anywhere in the data stream irrespective of the way in which the decoder is breaking up the data stream into codewords. This is an important feature since an error in the coded data stream may cause loss of synchronisation between the coder and decoder and the decoder may begin to produce run-length values which are not the same as those coded at the transmitter. As a result, the decoder may decode part of the EOL codeword as part of some other codeword and the EOL codeword itself will not be detected. This will mean that several subsequent lines of coded data would be incorrectly decoded before the coder and decoder naturally attain resynchronisation.However, this can be avoided by ensuring that resynchronisation occurs as soon as possible, that is on the next EOL codeword, and by making the EOL detection a separate process from the run-length decoder to ensure that the next, undamaged EOLwill always be detected. Thus, the amount of damage caused to a document due to an error is restricted to as small an area as possible.

In addition, the decoder automatically deals with "fill" bits whenever they occur. These bits consist of varying length strings of "0's" which, in some installations, are inserted into the data stream just before the EOL codeword. These padding bits are used to ensure that a scanner and printer, one of which is significantly slower than the other, can maintain line synchronisation (CCITT Recommendation T.4 contains details). As is apparent from the above description, these bits are in effect discarded by the decoder as is required.

Claims (7)

1. A decoder for decoding variable length codes of the type having a first group of n identical bits and a second group of m bits which can be different, the decoder comprising means for counting the number of said n bits in each codeword to provide an output representing said count, shift register means for receiving successive bits of each codeword, said counter output and said shift register means output providing address signals for memory means in which are stored decoded values of said codewords whereby when the address signals represent a recognisable codeword the corresponding decoded value is output from the memory means.

2. A decoder as claimed in claim 1 wherein said counting means comprises a latch having an output connected to a counter, said latch means being arranged to remain in a set state until it receives the first of said m bits and said counter being arranged to count only when said latch is set.

3. A decoder as claimed in claim 2 including means for re-enabling said latch and said counter at the end of a codeword.

4. A decoder as claimed in any preceding claim wherein said memory means comprises a ROM.

5. A decoder as claimed in any preceding claim wherein said shift register means is a serial inparallel out shift register.

6. A decoder as claimed in any preceding claim wherein said decoder includes means for detecting end of line codewords.

7. A decoder for decoding variable length codes substantially as hereinbefore described with reference to and as shown in the accompanying drawings.