GB2146467A - Control networks - Google Patents

Abstract

A control network for simply and inexpensively controlling a large number (up to 600) of peripheral units which in the described embodiment comprise video disc players of a video library, text generators, video switches for switching the signal from a particular video player and/or text generator through to an appropriate transmission link, and keypads associated with the video players whereby an operator can inform the control processor what disc is being mounted. The control processor drives up to twenty buses each having up to thirty peripheral units attached via interface units; each bus having eight data lines, and three lines for command and data strobes and flag, all the lines being differentially driven. Messages pass between the control processor and the interface units by means of a handshake procedure and a message transfer protocol. <IMAGE>

Description

SPECIFICATION Improvements in or relating to control networks This invention relates to control networks for controlling a multiplicity of peripheral units.

It is an object of the invention to provide a simple network for controlling a large number of peripheral units, for example video disc players in a video library, where the number of peripheral units could be in the region of 600.

Commercially available LAN's were considered but none was suitable. One LAN required the use of an expensive tap or interface unit, another LAN could not handle such a large number of peripheral units and would have needed several such LAN's each with a special controller. Another disadvantage is the short bus length of some commercial LAN's.

According to this invention there is provided a network for controlling a multiplicity of peripheral units, comprising a master control unit having a multiplicity of buses, a multiplicity of interface units coupled to each bus for coupling peripheral units thereto, each interface unit being arranged to respond to a command signal on its associated bus to read a command word comprising an address signal and a mode signal and, when addressed, to change from an idle mode to the commanded mode.

Preferably each interface unit comprises mode memory means for maintaining a commanded mode after the end of the command signal.

In order that the master control unit can have some information on the state of an interface unit, each such unit preferably comprises signalling means responsive to the command signal and to the addressed state of the unit to signal to the master control unit via a flag line of the bus.

The signalling means may be also responsive to the state of the mode memory means for putting a signal on the flag line to indicate that the interface unit is maintained in a commanded mode.

Preferably each bus has a number of parallel data lines, and more preferably each bus also has a data strobe line to which the master control unit can apply a data strobe signal for strobing data applied to the data lines by the master control unit into an interface unit which is in a listen mode, and for strobing onto the data lines data from an interface unit which is in a talk mode Each interface unit may comprise talk and listen temporary data stores for holding a data word until strobed by a data strobe signal, the signalling means being responsive to the state of the temporary data stores for sending a corresponding state signal on the flag line.

Preferably the master control unit is arranged to ask an addressed interface unit by means of a poll mode signal whether it has data to be sent to the master control unit, and the signalling means is arranged to apply to the flag line a first signal to indicate an affirmative answer or a second signal to indicate a negative answer.

Where the interface units comprise the temporary data stores, preferablythefirstand second signals correspond respectively to the full and empty states of the talk temporary data store.

Preferably the first and second signals represent logic and logic zero, respectively.

In a preferred arrangement of the present invention the bus comprises only a set of data/address lines, a line for said command signal, a line for a data strobe signal, and a flag line, and each interface unit is arranged to control the flag line such that (a) when a unit is in a talk mode, the flag line indicates that the unit is ready to transmit a byte of a message, (b) when a unit is in a listen mode, the flag line indicates that the unit is ready to accept a byte of a message, (c) when a unit is in a poll mode, the flag line indicates that the wait is waiting to transmit a message, and (d) when a unit is in a verify mode, the flag line indicates that the unit is present. In such a preferred arrangement each interface unit may be arranged to latch into talk mode and listen mode but not latch into poll mode and verify mode.

The invention will now be described by way of example with reference to the accompanying drawings in which Figure 1 is a schematic diagram of a network for controlling a multiplicity of video players in a video library, and Figure 2 is a schematic diagram of an interface unit.

Before describing the network it is appropriate to review the IEEE-488 bus sytem which was the strongest contender of the bus systems considered for the control network of the video library. This bus has several features which make it unsuitable for such an application: (a) although it has a 5 bit address, physical implementations employ a wired OR facility for signals such as NRFD and NDAC, and as a practical matter only about fourteen devices can be wire-ORed, also the noise immunity is not good; (b) the length of bus is only about twenty metres; (c) there are sixteen signal lines and a commensurate amount of logic circuitry but perhaps even more important is the high cost of cable and connectors; and (d) the system is expensive to implement even though there are available proprietary interface chips such as 96LS488.

A modification of the IEEE-488 bus system is known in which an interface on the bus can be addressed using the normal command protocol and one of four devices associated with that interface selected by special decoding of a following data word. Although this increases the number of devices that can be addressed (and chip 96LS488 allows secondary addresses) the short bus length is still a major disadvantage, and furthermore these devices are constrained to talk using nibbles and typically a device is coupled via ten sets of four data lines with the interface. This latter point would lead to an unacceptable number of drivers/receivers if such a modified IEEE-488 system were to be used as the basis for a multiple unit arrangement of the scale of a cable TV system video library.

The video library described below requires of the order of 600 units to be controlled by a master control unit with the furthest units approximately one hundred metres away, and many of the units will be video disc players incorporating inductive loads which are switched on and off.

In a cable TV system providing customers with a variety of video services, one such service is access to the video library referred to above comprising a large number of video disc players situated at a Headend or a Super Headend of a video network.

When a customer wants a particular video programme from the video library he sends a request to the Headend via his local Wideband Switch Point (not shown) and a signalling ink (not shown) back to the Headend. Referring to Figure 1 which shows the basic arrangement of the control network, the message goes via a communication link 10 to a video library control processor 11 (also referred to herein as a master control unit). An operator console 12 is provided for manual control of the video library.

The control processor 11 communicates with the peripheral units of the video library by means of twenty separate buses 13, each bus comprising eleven lines with each line being formed by a pair of wires which are differentially driven. Three of the lines are for control signals, these being a Command strobe signal (C), a Data strobe signal (D) and a flag signal. The remaining eight lines carry the 8-bit message signals and the command signals which latter are in the form of a 2-bit mode signal, a 1-bit reset signal and a 5-bit address signal. The eight message/command lines (commonly called data/ address lines) and the flag line are driven by three-state differential drivers (not shown) so that, as is known in the art, non-transmitting drivers do not adversely affect line conditions for a transmitting driver.The command and data strobe lines may similarly be driven but as they have only one driver per line this is not essential.

The control processor 11 has the capacity to drive a a maximum of thirty peripheral units on each bus, thus up to 600 peripheral units can be controlled.

The number of peripheral units on a bus is determined by the load capacity of the differential line drivers, which in this case is thirty two (two loads are required by the control processor, one being the normal receiver and the other being a test point receiver), and each bus can be up to about 100 metres long. There is no technical difficulty in providing more than twenty buses, although with larger networks the time taken say to poll every peripheral unit may be a significant factor.

In one arrangement, each bus is limited to controlling one type of peripheral unit, for example a group of the buses will control all video disc players 14, one such bus is shown controlling video players 14-1 to 14-30. Video player 14-29 is in fact omitted and represents a peripheral unit removed for technical or operational reasons, for example repair, and the response of the control network to the absence of a peripheral unitwill be described later.

Each video player 14 is coupled to its bus by an interface unit 15 for communication with the control processor 11.

Another group of the buses controls text generators 16, yet another group of the buses controls keypads 17 associated with the video players 14, and a further group of the buses controls the video switches 18.

The video switches 18 receive inputs from the video players 14 and the text generators 16, and also from photographic videotex generators (not shown) which are not under the control of the video library control network.

The mode signal referred to above can define four modes, which are Talk, Listen, Poll and Verify. If the control processor 11 wants to send instructions to video player 14-lit will apply to the data lines a Listen mode signal together with the address of interface unit 15-1, and at the same time put a Command strobe signal (pulse) on the C line. Upon receipt of the Command strobe signal all the interface units check the address signal, but only interface unit 15-1 will recognise its own address and read in the Listen mode signal. Simultaneously, a signal will be put out on the flag line by the interface unit to indicate that it is responding.

When the Listen mode signal is read in, the interface unit will latch into that mode, and maintain the signal put out on the flag line.

Thereafter the control processor 11 will put the message onto the data lines and an appropriate Data strobe signal onto the D line whereupon the interface unit 15-1 will read in the message, at the end of which a reset mode condition will reset the interface unit to idle mode. The control processor 11 can then proceed to address another interface unit to send a control message for its associated video player.

At a suitable time the control processor 11 can ask the video players, or indeed any other peripheral unit, whether it has a message to send, and it does this by means of a Poll mode signal. When an interface unit is polled it checks to see whether there is a message waiting to be sent and puts a signal on the flag line to indicate that a message is waiting.

The flag signal is not maintained and ceases at the end of the Command strobe signal. If there is a message to be sent to the control processor the flag is driven into the logic one state by the polled interface unit. If no message is waiting to be sent the interface unit will drive the flag line into the logic zero state. Should the polled interface device not actually exist on the bus the control processor bus flag line receiverwill default to a logic zero, indicating that no message is waiting.

When the control processor 11 is ready to receive a message from an interface unit which it knows is waiting to send a message, it sends a Talk mode signal and the appropriate address signal, and the relevant interface unit responds by latching into a Talk mode and maintaining a signal on the flag line.

Thereafter, receipt of the Data strobe signal causes the waiting message to be strobed out to the data lines for receipt by the control processor.

The message transfer protocol is described more fully later with reference to Figure 2.

If the control processor 11 wishes to check that a particular video player, or any other peripheral unit, is present it can send a Verify mode signal, and the relevant interface unit will give an affirmative response by putting a logic one signal on the flag line for the duration of the Command strobe signal. If there is no peripheral unit and interface unit present, for example units 14-29 and 15-29, the flag line is not driven into a definite logic state but is indeterminate.

However, this is recognised as a unit not present by virtue of bias applied to the flag line..

Each of the keypads 17 is associated with a respective disc player 14 and is used by the operator to input a code signal corresponding to the disc that he mounts on the disc player. This code signal is now stored as a message waiting to be transmitted to the control processor, and after the control processor receives the code signal it checks that the actual disc mounted on the disc player is the one intended to be mounted.

In Figure 2, a peripheral device or unit 20 sends the first word of a waiting message to Talk Latch 21 where it is stored. A status flip flop 22 becomes set to indicate the state of the Talk Latch 21. Upon receipt of a Command strobe signal by differential receiver 23 from the C line, the interface control unit 24 inspects the command word on the Data lines, if it recognises its address action will take place according to the mode signal recognised by the control unit 24, and stored in a mode memory 32. In the case of Talk and Listen mode signals, the mode memory does not reset at the end of the Command strobe signal.If a Talk mode signal is recognised, control unit 24 responds to an empty state of flip flop 22 to send the next data word to the Talk Latch 21 which responds to receipt of the Data strobe signal via differential line receiver 28 from the D line to transmit the stored word to the data lines. In response to receipt of the Data strobe signal and to the state of flip flop 22, control unit 24 generates a logic one signal for transmission to the flag line via differential line driver 29, and while the interface unit is in the Talk mode, this signal follows the state of flip flop 22 so that the control processor 11 can know when the next word is ready to be strobed to the data lines.

Talk Latch 21 is coupled to eight differential line drivers 30 connected to the data lines, and Listen Latch 25 is coupled to eight differential line receivers 31 also coupled to the data lines.

Control unit 24 and differential line driver 29 are basically arranged to respond to the state of the status flip flops 22 and 26 to put a corresponding signal onto the flag line.

Data present on the data lines is presented via differential line receivers 31 to the interface control continuously. When a Command strobe signal is received via differential line receiver 23, the mode signal is latched into the mode memory 32 if the address is the address of that interface unit. If the address is not the address of the receiving unit then the mode memory is reset to the idle mode state.

When the control processor 11 receives this flag signal it then puts a Data strobe signal on the D line which strobes the data into the Listen Latch 25 from where the data can be read by the peripheral device 20. When Listen Latch 25 is empty, control unit 24 responds to the empty status of flip flop 26 to change the signal on the flag line to logic zero. This is recognised by the control processor 11 which presents a fresh data word onto the data lines and a corresponding Data strobe signal. This message transfer protocol thus ensures that a fresh data word is not presented until the previous word is strobed onto the peripheral device 20, and continues until the end of the message.

If the interface unit has a message to send, control unit 24 presents the first word to Talk Latch 21 where it is stored, and the status flip flop 22 correspondingly indicates that its latch is full. When the interface unit is polled, control unit 24 now responds to the full status of flip flop 22 and puts a logic one onto the flag line to indicate to the control processor 11 that the interface unit has a message to send. Upon recognition of the Poll mode signal by the control unit 24, a logic one is sent on the flag line only during the Command strobe pulse. This enables rapid round robin polling of the interface units by the control unit 24.

When the control processor 11 is ready to receive the message from the interface unit it will send a Talk mode signal, which is recognised by the control unit 24 and stored in the mode memory 32. Control unit 24 will respond to the status flip flop 22 after the Command strobe pulse to indicate that the Talk Latch 21 is full. The control processor 11 now responds to the signal on the flag line for sending the Data strobe pulses in the same manner as for commanding the reading-in of a message.

The control network as described above enables a control processor to send messages to and receive messages from an addressed one of a very large number of peripheral units in an electrically noisy environment using a simple protocol, does not use expensive interface units, can be implemented cheaper than using known general purpose buses, and can have a bus length up to about 100 metres.

Claims (16)

1. A network for controlling a multiplicity of peripheral units, comprising a master control unit having a multiplicity of buses, a multiplicity of interface units coupled to each bus for coupling peripheral units thereto, each interface unit being arranged to respond to a command signal on its associated bus to read a command word comprising an address signal and a mode signal and, when addressed, to change from an idle mode to the commanded mode.

2. A network as claimed in claim 1 wherein each interface unit comprises mode memory means for maintaining a command mode after the end of the command signal.

3. A network as claimed in claim 1 or claim 2 wherein each interface unit comprises signalling means responsive to the command signal and to the addressed state of the unit to signal to the master control unit via a flag line of the bus.

4. A network as claimed in claim 3 when dependent upon claim 2 wherein the signalling means is also responsive to the state of the mode memory means for putting a signal on the flag line to indicate that the interface unit is maintained in a commanded mode.

5. A network as claimed in claim 4wherein each bus has a number of parallel data lines for the communication of data, for example the command word, between the master control unit and the interface units.

6. A network as claimed in claim 5 wherein each bus also has a data strobe line and the master control unit can apply a data strobe signal for strobing data applied to the data lines by the master control unit into an interface unit which is in a listen mode, and for strobing onto the data lines data from an interface unit which is in a talk mode.

7. A network as claimed in claim 6 wherein each interface unit comprises talk and listen temporary data stores for holding a data word until strobe by a data strobe signal, and the signalling means is responsive to the state of the temporary data stores for sending a corresponding state signal on the flag line.

8. A network as claimed in any one of claims 3 to 7 wherein the master control unit is arranged to ask an addressed interface unit by means of a poll mode signal whether it has data to be sent to the master control unit, and the signalling means is arranged to apply to the flag line a first signal to indicate an affirmative answer or a second signal to indicate a negative answer.

9. A network as claimed in claim 8 when dependent upon claim 7 wherein the first and second signals correspond respectively to the full and empty states of the talk temporary data store.

10. A network as claimed in either claim 8 or claim 9 wherein first signal represents logic one and the second signal represents logic zero.

11. A network as claimed in claim 10 wherein in response to a poll mode signal the signalling means is arranged to apply the first signal to the flag line only during the command signal.

12. A network as claimed in claim 1 wherein the bus comprises only a set of data/address lines, a line for said command signal, a line for a data strobe signal, and a flag line, and each interface unit is arranged to control the flag line such that (a) when a unit is in a talk mode, the flag line indicates that the wait is ready to transmit a byte of a message, (b) when a unit is in a listen mode, the flag line indicates that the unit is ready to accept a byte of a message, (c) when a unit is in a poll mode, the flag line indicates that the wait is waiting to transmit a message, and (d) when a unit is in a verify mode, the flag line indicates that the unit is present.

13. A network as claimed in 12 wherein each interface is arranged to latch into talk mode and listen mode but not latch into poll and verify mode.

14. A network as claimed in any one of claims 3 to 13 and comprising means for biassing the flag line to a default state.

15. A network as claimed in any one of claims 1 to 14wherein each line comprises a plurality of lines and each line is in the form of a differential pair.

16. A network for controlling a multiplicity of peripheral units, substantially as herein described with reference to the accompanying drawing.