GB2146190A - Oscillation generator arrangements - Google Patents
Oscillation generator arrangements Download PDFInfo
- Publication number
- GB2146190A GB2146190A GB08421078A GB8421078A GB2146190A GB 2146190 A GB2146190 A GB 2146190A GB 08421078 A GB08421078 A GB 08421078A GB 8421078 A GB8421078 A GB 8421078A GB 2146190 A GB2146190 A GB 2146190A
- Authority
- GB
- United Kingdom
- Prior art keywords
- microprocessor
- oscillator
- voltage
- frequency
- vco
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000010355 oscillation Effects 0.000 title claims description 11
- 230000001419 dependent effect Effects 0.000 abstract 1
- 230000000737 periodic effect Effects 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 2
- 230000002045 lasting effect Effects 0.000 description 1
- 230000003534 oscillatory effect Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
- H03L7/141—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted the phase-locked loop controlling several oscillators in turn
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
A single microprocessor services thirteen VCO's each providing a different channel frequency. A variable counter controlled by the microprocessor is connected to the output of each VCO via a multiplexer in turn. The time period from the o/p of the counter is crosschecked by the timer-counter in the microprocessor. This timing (which is derived from the microprocessor's clock) is accurately determined by a master oscillator. Using a D to A converter connected via another multiplexer to a sample & hold circuit on the control input of each VCO the microprocessor sets the control voltage for each dependent on the result of the count crosscheck. Since the voltage on the sample hold circuit decays with time each VCO voltage is refreshed by the microprocessor at periodic intervals using the voltage figure determined on the last respective frequency check. <IMAGE>
Description
SPECIFICATION
Oscillation Generator Arrangements
The present invention relates to oscillation generator arrangements.
In particular although not exclusively the invention is concerned with oscillation generator arrangements for generating a plurality of oscillatory output signals at respective different predetermined frequencies.
According to one aspect of the present invention an oscillation generator arrangement comprises a voltage controlled oscillator, means to derive a digital signal indicative of the output signal frequency of said oscillator, digital signal processor means to derive from said digital signal a frequency control signal for said oscillator, and means to apply said frequency control signal to said oscillator whereby said oscillator is controlled to generate an output signal of substantially a predetermined frequency.
According to another aspect of the present invention an oscillation generator arrangement comprises a plurality of voltage-controlled oscillators, means to derive a plurality of digital signals respectively indicative of the output signal frequency of each of said oscillators, digital signal processor means to derive from each of said digital signals a respective frequency control signal, and means to apply said frequency control signals to the respective oscillators whereby each oscillator is controlled to generate an output signal of substantially a respective predetermined frequency.
An oscillation generator arrangement in accordance with the present invention will now be described with reference to the accompanying drawings, of which:
Figure 1 shows the arrangement schematically, and
Figure 2 shows part of the arrangement of
Fig. 1 in greater detail.
Referring first to Fig. 1, the generator arrangement comprises a plurality of voltagecontroled oscillators 1 each arranged to provide an output signal at a respective different frequency on a respective output path 2, and a selector 3 by means of which selectively any one of these output signals may be passed to a programmable divider 4. The division ratio of the divider 4 is arranged to be set for each output signal under the control of a microprocessor 5, in dependence upon instructions which may be held in an erasable programmable memory or EPROM 6.
When the output signal from any one of the oscillators 1 is applied to the divider 4 the time taken from the divider 4 to complete a count cycle with the predetermined division ratio in respect of that oscillator 1 is measured by means of a timer/counter in the microprocessor 5 and the outcome is utilised to derive a digitally coded value, in dependence upon instructions held in the EPROM 6, which determines the value of a frequency-controlling voltage for the respective oscillator 1. The digitally coded value may be applied by way of a digital-to-analogue convertor (not shown) and a distributor 7 to the respective oscillator 1.
Referring now to Fig. 2 each oscillator 1 is provided with a sample-and-hold circuit 8 by which the frequency controlling voltage may be made virtually continuously available to the respective oscillator 1, while the microprocessor 5 is updating the digitally coded value for that oscillator 1 or any of the other oscillators 1. The output frequency of each oscillator 1 may be determined by a piezoelectric crystal 9 and a variable capacitance or varactor diode 10 as shown, although an LC tuned circuit may be utilised instead of the crystal 9.
The oscillation generator arrangement may comprise thirteen oscillators 1 arranged to provide one pilot or signalling frequency and twelve carrier signal frequencies spaced at say, 4KHz intervals in a band of frequencies from 60 KHz to 108KHz. The output of each oscillator 1 in turn is applied to the divider 4, and the respective division ratio provided by the microprocessor 5 may be arranged to give a count cycle lasting of the order of ten seconds. The timer-counter of the microprocessor 5 can measure this cycle period to, say, the nearest microsecond, so that the output frequency of the respective oscillator 1 can thereby be measured to an accuracy of one in ten million. The clock signal for the microprocessor 5 may be derived from a system master oscillator (not shown) over a path 11, and the timing of the cycle period may therefore be made very accurate.A masterclock failure circuit 1 2 may be provided to reset the microprocessor 5 and to give an alarm indication if required.
In order to bring the individual oscillators 1 to their required frequencies on start-up the respective division ratios may be made less by, say, an order of ten, so as to provide correspondingly less accurate but more frequently up-dated control voltages. The division ratios may subsequently be increased in several steps to the final ratio. Once the arrangement has stabilised a "new" digitally coded value for each oscillator will be selected or generated every ten seconds or so, and this coded value will thereafter be applied to the digital-to-analogue for decoding every few milliseconds, to "refresh" the sample-and-hold circuit 8 with the corresponding voltage, until the next "new" value is selected or generated.
Under microprocessor control any non-linearity in the control voltage/frequency characteristic can be accommodated in the instructions held in the EPROM 6, and frequencies that do not bear a simple numerical relation ship to the master oscillator frequency may readily be obtained. At the same time a saving in components may be achieved due to the time sharing of the control circuitry.
Self testing information may be written into the instructions in the EPROM 6. while these instructions themselves may be varied, or fault diagnoses read out, using for example a handheld unit (not shown) which may be connected to the microprocessor 5.
Claims (3)
1. An oscillation generator arrangement comprising a voltage controlled oscillator, means to derive a digital signal indicative of the output signal frequency of said oscillator, digital signal processor means to derive from said digital signal a frequency control signal for said oscillator, and means to apply said frequency control signal to said oscillator whereby said oscillator is controlled to generate an output signal of substantially a predetermined frequency.
2. An oscillation generator arrangement comprising a plurality of voltage-controlled oscillators, means to derive a plurality of digital signals respectively indicative of the output signal frequency of each of said oscillators, digital signal processor means to derive from each of said digital signals a respective frequency control signal, and means to apply said frequency control signals to the respective oscillators whereby each oscillator is controlled to generate an output signal of substantially a respective predetermined frequency.
3. An oscillation generator arrangement substantially hereinbefore described with reference to the accompanying drawings.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB838322439A GB8322439D0 (en) | 1983-08-19 | 1983-08-19 | Oscillation generator arrangements |
Publications (2)
Publication Number | Publication Date |
---|---|
GB8421078D0 GB8421078D0 (en) | 1984-09-26 |
GB2146190A true GB2146190A (en) | 1985-04-11 |
Family
ID=10547605
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB838322439A Pending GB8322439D0 (en) | 1983-08-19 | 1983-08-19 | Oscillation generator arrangements |
GB08421078A Withdrawn GB2146190A (en) | 1983-08-19 | 1984-08-20 | Oscillation generator arrangements |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB838322439A Pending GB8322439D0 (en) | 1983-08-19 | 1983-08-19 | Oscillation generator arrangements |
Country Status (1)
Country | Link |
---|---|
GB (2) | GB8322439D0 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3810809A1 (en) * | 1988-03-30 | 1989-10-12 | Fev Motorentech Gmbh & Co Kg | Method for phase-locked frequency conversion |
EP0345940A2 (en) * | 1988-05-31 | 1989-12-13 | Plessey Overseas Limited | A frequency signal synthesiser |
FR2666471A1 (en) * | 1990-08-31 | 1992-03-06 | Erfatec | Precision system for offset control for television networks |
WO1996008083A1 (en) * | 1994-09-10 | 1996-03-14 | Philips Electronics N.V. | Microwave transmitter and communications system |
EP0772359A1 (en) * | 1995-10-31 | 1997-05-07 | Philips Electronique Grand Public | Filtering device for processing a plurality of channels in a cable television distribution system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1581525A (en) * | 1976-08-04 | 1980-12-17 | Plessey Co Ltd | Frequency synthesis control system |
-
1983
- 1983-08-19 GB GB838322439A patent/GB8322439D0/en active Pending
-
1984
- 1984-08-20 GB GB08421078A patent/GB2146190A/en not_active Withdrawn
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1581525A (en) * | 1976-08-04 | 1980-12-17 | Plessey Co Ltd | Frequency synthesis control system |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3810809A1 (en) * | 1988-03-30 | 1989-10-12 | Fev Motorentech Gmbh & Co Kg | Method for phase-locked frequency conversion |
EP0345940A2 (en) * | 1988-05-31 | 1989-12-13 | Plessey Overseas Limited | A frequency signal synthesiser |
EP0345940A3 (en) * | 1988-05-31 | 1990-05-16 | Plessey Overseas Limited | A frequency signal synthesiser |
FR2666471A1 (en) * | 1990-08-31 | 1992-03-06 | Erfatec | Precision system for offset control for television networks |
WO1996008083A1 (en) * | 1994-09-10 | 1996-03-14 | Philips Electronics N.V. | Microwave transmitter and communications system |
EP0772359A1 (en) * | 1995-10-31 | 1997-05-07 | Philips Electronique Grand Public | Filtering device for processing a plurality of channels in a cable television distribution system |
Also Published As
Publication number | Publication date |
---|---|
GB8322439D0 (en) | 1983-09-21 |
GB8421078D0 (en) | 1984-09-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |