GB2144306A

GB2144306A - Interface circuit for telecommunication systems

Info

Publication number: GB2144306A
Application number: GB08417576A
Authority: GB
Inventors: Harald Butter
Original assignee: International Standard Electric Corp
Current assignee: International Standard Electric Corp
Priority date: 1983-07-27
Filing date: 1984-07-10
Publication date: 1985-02-27
Also published as: ATA272783A; GB2144306B; AT381430B; GB8417576D0

Abstract

An interface circuit with an unbalanced input a1, b1, a balancing circuit 5 and balanced output a, b having a capacitive complex impedance. The balanced capacitive complex output network (A) is an H-type circuit with only one capacitor (C3) whose tolerance has no influence on the symmetry and therefore inexpensive components can be used. A compensation network (E) compensates the dependence of frequency. <IMAGE>

Description

SPECIFICATION Interface Circuit for Telecommunication Systems The present invention is directed to an interface circuit for telecommunication systems especially switching systems with an unbalanced input a balancing circuit and a balanced output having a capacitive complex impedance.

In future switching systems it could be necessary to realise the impedance of a two-wire interface circuit as a capacitive complex network, containing a resistor connected in series with a second resistor which is connected in parallel with a capacitor. The values of the components are determined by the Telecommunication Authority. Since this complex network is used as a balanced output network it is necessary to describe it as a four-terminal network (Figure 1), whereby high conditions are made on the symmetry of this network. Especially regarding equality of the capacitances high demands on the tolerances are made and therefore an economical use of this known solution is not given.

The invention seeks to provide a simplified network which is less susceptible to component tolerance variation.

According to the invention there is provided an interface circuit for telecommunication systems more particularly for switching systems, with an unbalanced input a balancing circuit and a balanced output having a capacitive complex impedance, characterised in that the balanced capacitive complex output network is a H-type circuit having series resistances and a shunting capacitor and that the unbalanced input is connected in series with a compensation network which compensates the dependence of frequency of the complex output network.

This invention has the advantage, that it uses only one capacitor in the output network and its tolerance has no influence on the symmetry of the circuit thereby permitting an inexpensive component to be used. The compensation network compensates the dependence of frequency of the complex output network and it is possible to transmit a wider range of frequency, e.g, voice signals.

In a refinement of the invention the above described compensation network contains an operational amplifier with an inverting input controlled via a capacitor and a resistor connected in parallel, and with an output signal which is fed back over a feed-back-resistor to the inverting input, whereby the resistor and the feedback-resistor each have twice the resistance value of the series resistors of the output network and whereby the capacitor has the same capacity as the shunting capacitor of the output network.

This circuit has the advantage that the tolerance of the capacitor has no influence on the function, and the interface circuit can be easily produced as an integrated circuit.

A further development of the invention is characterised in that no compensation circuit is necessary if only a single frequency signal is to be transmitted, e.g. ringing tone supply.

In order that the invention and its various other preferred features may be understood more easily, an embodiment thereof will now be described, by way of example only, with reference to the drawings, in which: Figure 1 is a block schematic illustration of a well known interface circuit and Figure 2 is a block schematic illustration of an interface circuit constructed in accordance with the invention.

Figure 1 shows a well known interface circuit with unbalanced input and balanced output having a capacitive complex impedance which consists of a balancing circuit S and a complex network A'. In this arrangement the balancing circuit S is built up of two operational amplifiers OP 1 and OP2. The input signal is connected via resistor R1 to the inverting input of OP 1 as well as directly to the not inverting input of OP2. The not inverting input of OP 1 is connected to earth.The output signal of OP 1 is connected via a feed-back resistor R2 to the inverting input of OPi. The output signal of OP2 is connected directly to the inverting input of OP2. The outputs of both operational amplifiers OP1 and OP2 are connected with output terminals ao and bo of the balancing circuit whereby the balanced output signal Uo is generated.

For balancing reasons the complex output network A' consists of two fully identical circuits, each of them containing a series arrangement of a resistor R5/R6 and a capacitor C1/C2 which is connected in parallel with a resistor R3/R4. The resistors R3 and R4 each have the same resistance R, resistors R5 and R6 each have the same resistance R', and the capacitors C1 and C2 have the capacitance C. If the output terminals a and b of the network A' are terminated with any balanced load resistor ZL.When a current IL is flowing the output voltage U, at the output terminals a and b is:

With reference to Figure 2 an interface circuit constructed in accordance with the invention contains a balancing circuit S as shown in Figure 1, a complex output network A and a compensation network E. The output network A is realised by using a H-type circuit, containing the series resistors R3, R4, R5 and R6 and the shunting capacitor C3.

The resistors R3 and R4 each have the same resistance R, the resistors R5 and R6 each have the same resistance R' and the capacitor C3 has the capacitance C 2 that is half of the capacitance value of the capacitors C1 and C2 shown in Figure 1.

If this network A at the output terminals a and b is terminated with any symmetric impedance ZL, a current 16 flows and the voltage Uc at the capacitor C3 is: Uc=U,+2R' i, (2) The voltage Uo at the input terminals of the output network A is: C Uo=UcS2R(l,+jo--Uc) (3) 2 substituting (2) in (3) UoU,+2R' I,+2Rl,+lwRC (U,+2R' I,) Uo=U, (I+joRC)+2 I, [R+R' (I+joRC)1 Hence it follows the voltage at the terminals a and b::

It is evident from equations (1) and (4), that both of the output networks A' (Figure 1 ) and A (Figure 2) have the same internal resistance Zi, though the output voltage U, of output network A contains a portion X which is frequency dependent In order to compensate this frequency dependence a compensation network E is connected before the balancing circuit S. This compensation network E contains an operational amplifier OP3, whose inverting input is controlled via a capacitor C4 and a resistor R7 connected in parallel, and whose output signal is fed back to the inverting input via a feed back resistor R8.The resistors R7 and R8 each have the resistance 2R which is twice the value of the frequency dependent resistors R3 and R4, and the capacitor C4 has the same capacitance C 2 as the shunting capacitor C3 of the output network A.

The output voltage U2 of compensation network E can be deduced from the amplifier formula

whereby U1 is the input voltage at the input terminals al and b1 of the compensation network.

Hence it follows

Compared with the output voltage U, (equation 4) of the complex output network A, the output voltage U2 of the compensation network E (equation 5) has therefore the inverse frequency response. This kind of compensation is the best one and needs no further adaptation of the phase response.

As the balancing circuit S and complex output network A is basically frequency dependent because its output network consists of resistors and capacitors the compensating network E is normally employed in order to offset this frequency dependence. However, if only single frequency signals e.g. audio tones are to be transmitted by the interface circuit the compensation network E can be omitted. Such a construction is considered to fall within the scope of this invention.

Claims

1. An interface circuit for telecommunication systems more particularly for switching systems, with an unbalanced input a balancing circuit and a balanced output having a capacitive complex impedance, characterised in that the baianced capacitive complex output network (A) is a H-type circuit having series resistances (R3... R6) and a shunting capacitor (C4) and that the unbalanced input is connected in series with a compensation network (E) which compensates the dependence of frequency of the complex output network (A).

2. An interface circuit as claimed in claim 1, characterised in that the compensation network (E) contains an operational amplifier (OP3) with an inverting input (-) controlled via a capacitor (C4) and a resistor (R7) connected in parallel, and with an output signal which is fed back over a feed-back-resistor (R8) to the inverting input (-), whereby the resistor (R7) and the feed-backresistor (R8) each have twice the resistance value of the series resistors (R3, R4) of the output network (A) and whereby the capacitor (C4) has the same capacity as the shunting capacitor (C3) of the output network (A).

3. An interface circuit as claimed in claim 1 or 2, characterised in that no compensation circuit is used, if only a single frequency signal is transmitted.

4. An interface circuit substantially as described herein with reference to Figure 2 of the drawings.