GB2143082A - Bipolar lateral transistor - Google Patents
Bipolar lateral transistor Download PDFInfo
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- GB2143082A GB2143082A GB08318320A GB8318320A GB2143082A GB 2143082 A GB2143082 A GB 2143082A GB 08318320 A GB08318320 A GB 08318320A GB 8318320 A GB8318320 A GB 8318320A GB 2143082 A GB2143082 A GB 2143082A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
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Abstract
A bipolar lateral transistor having a base-emitter structure 6,7 in which the active base region 7'' in the emitter-collector path is relatively narrow. The bipolar transistor is formed in a CMOS. <IMAGE>
Description
SPECIFICATION
Integrated circuits
This invention relates to integrated circuits and in particular to circuits including a field effect portion and a bipolar portion, and to transistor structures therefor.
Conventional integrated circuits generally employ eitherfield effect or bipolarelements. Field effect circuits are used mainly in digital applications, whereas for analogue applications, such as in radio signal processing, bipolar circuits are more suitable. There is a need in certain applications, e.g. telephony, for processing both digital and analogue signals and this normally requires the provision of two circuit chips each with its associated peripheral circuitry. Clearly it would be advantageous to provide both bipolar and field effect functions on a single chip. Various techniques for combining both field effect and bipolar elements on a single chip have already been suggested. Howeverthe previously proposed techniques suffer from various disadvantages.If, for example,
CMOS (Complementary Metal Oxide Silicon) processing is added to basic SBC (Standard Buried Collector) processing, good bipolar performance is achieved but the CMOS packing density, speed and predictability are compromised.
According to one aspect ofthe present invention there is provided an integrated circuit including a field effect portion and a bipolar portion, wherein the bipolar portion includes a bipolartransistorwhose base-emitter structure is such asto define a narrow active base region whereby to provide optimum lateral operation ofthetransistor.
According to another aspect of the present invention there is provided a bipolar lateral transistor having a base-emitter structure including a narrow active base region such as to provide optimum lateral operation ofthetransistor.
Embodiments of the invention will now be de scribed with reference to the accompanying drawings, in which:~
Fig. 1 illustrates a cross-section through a basic combined CMOS and bipolar integrated circuit, the
CMOS employing n-type wells and a conventional bipolartransistor (npn) being formed in an n-type well.
Fig. 2 illustrates a cross-section through a combined
CMOS and bipolar integrated circuit, the bipolar transistor comprising a lateral transistor;
Figs. 3a and 3bshow respectively the approximate doping profile required for a lateral npn triple diffused transistor in vertical and lateral section;
Figs. 4a and 4b show a section through a lateral bipolartransistorstructure and a conventional bipolar transistor structure, respectively;
Fig. 5 shows an npn lateral bipolartransistor and its equivalent circuit;
Fig. 6 illustrates a cross-section through a basic combined p-type well CMOS and bipolar integrated circuit, a lateral bipolar (npp n) transistor being formed in a p-type well;
Fig. 7 illustratesavariantofthe Fig. 6 arrangement with vertical device suppression;;
Fig. 8 shows a variant of the arrangement of Fig. 6 configured in silicon on an insulator so that no alternative collectors exist;
Figs. 9 to 15 illustrate a processing sequence for fabrication of the arrangement of Fig. 2; and
Fig. 16 illustrates a further arrangement of a lateral bipolartransistorwith low base resistance in an n well of a CMOS device.
The integrated drcuitstructure illustrated in Fig. 1 comprises a p-type substrate 1 in which are formed n-type wells 2 and 3. A P-channel MOS field effect device 4 is formed in n-type well 2, an N-channel MOS field effect device 5 formed directly in the substrate 1 and a conventional npn bipolartransistor 6 isformed in n-type well 3. The transistor 6 employs the well 3for its collector, has a p-type base region 7 formed by diffusion into the well 3 and an emitter 8 and collector contact 9 formed by an n+ diffusion which is employed to form the source and drain of MOS device 5. A base contact 10 is formed by a p+ diffusion which is employed to form the source and drain of MOS device 4.For npn bipolar transistors in this configuration the
CMOS is required to have n-type wells, whereas for pnp bipolartransistorsthe CMOS would need to have p-type wells. Whilst these constructions should not compromise the CMOS devices, the inherent high collector series resistance of the triple diffused bipolar device would not be desirable, neither would the inherent low early voltage.
However, it is possible to minimise the current path to the collector contact by arranging thatthe bipolar device 6 operates predominantly in the sideways direction. That is, by forming the bipolar device as a lateral transistor 6'. This may be achieved by ensuring that, for example, the doping profile is chosen to be the optimum for lateral operation, for example the base region is made deep and highly doped where it lies below the emitter and is made relatively lightly doped at the periphery of the emitter. In the embodi ment of the present invention illustrated in Fig. 2 the base region 7 comprises a deep, highly doped region 7'extending under the emitter 8 and a relatively lightly doped region 7" to the side of the emitter 8.An example of an approximate doping profile for the lateral triple diffused npn transistor is illustrated in
Figs. 3a and 3b. The base region is designed to (a) suppress downward carrier injection and (b) provide a low resistance path to minimise base series resistance to the "active" base region 7". The base diffusion 7' may be approximately 2 micrometre deep, whereas the "active" region is narrow, approximately 0.2 micrometre wide. The "active" region is relatively lightly doped to provide a high gain, high frequency transistor structure in the lateral direction, the predominant emitter-collector path being parallel, and adjacent, to the surface of the substrate 1 (seethe injection path indicated by arrows in Fig. 4a).Because the currentflowwill be predominantly lateral in direction, the current path length will be minimised so that the collector series resistance will be low to the n+ collector contact 9. The spacing thereof from the base
region need only be as great as is required for
adequate voltage handling. The particular configuration shown in Fig. 2 facilitates processing in orderto achieve optimum base impurity profile for lateral operation.
In the conventional npn bipolartransistor structure shown in Fig. 4b the resistance of the base region 7"'
underthe emitter 11 causes injection (indicated by arrows) to be concentrated at the emitter corners, making itnecessaryto providetwo base contacts 12to achieve good performance. In effect Rbb, are increased, and so are Cm and Cob (Fig. 5). Both Rb, and
Rbb, are higher in the conventional structure than in the lateral structure.This directly affects the maximum operating frequencyfmax, which is inversely proportional to the square root of Rb,CC. Also, as the depletion region at the base-collector junction widens, the current path to the emitter 11 narrows in the conventional structure, increasing Rsc, whereas in the lateral structure it shortens, tending to reduce Rsc.
Thusthe lateral structure will notonlyhave an enhanced performance, itwill also take up less area.
An alternative structure to that shown in Fig. 2 is the base isolated 'npn' lateral bipolartransistorshown in
Fig. 6. It employsthe same base emitter structure but in a p-typewell 13 comprising part of the base in an n-type substrate 1'. The construction of the devices of
Figs. 2 and 6 is similar but their operation is somewhat different. The normal operation ofthe bipolartransistor (npp n) would again be lateral with the p-well 13 part of the base, which is more lightly doped than the active base region 14, being depleted between the active base region 14and the collector 15. This then constitutes a drift region for carriers and does not contribute to the collector series resistance.The base doping profile is stepped with a low doped portion provided to accommodate the depletion region at the collector junction. A more highly doped region defines the active base width into which the depletion region will not encroach. The base width is not expected to be significantly modulated by collector voltage variations. However, the operation of the device (as drawn) may be degraded by the substrate acting as an alternative collector unless the downward injection is sufficiently poor. There are various possibilities for suppressing the vertical device that exists if the substrate acts as an alternative collector, such as an implanted oxide layer beneath the emitter.Alterna tively,the emitter 18 and indeed the collector 19 may be isolated by forming them in silicon 20 deposited on oxide 16 into which an opening has been cut to contact a previously diffused base region 17 as indicated in
Fig. 7. The deposited silicon 20, which may be either amorphous or polycystalline, may be regrown epitax iallyfromthe"seed"ofthebaseopening.Such reg rowing may be employed to provide all ofthe deposited layer or only sufficiently to accommodate the pn junctions. Outdiffusion from the substrate could be used to form the base region. The bipolar device of Fig. 7 is nnpn for p-well CMOS and truly lateral with the oxide underlying the emittersuppres- sing downward injection.
In orderto completely overcome the problem of alternative collectors, the lateral bipolar transistor and the CMOS devices of Fig. 6 may be built entirely in respective islands 21 (Fig. 8) of silicon grown on an insulator 22, for example sapphire, the islands being
suitably doped p-type or n-type as appropriate. The
lateral bipolartransistors may be constructed in
p-type or n-type islands, although such an arrange
mentwould be of less benefit for the n-type islands
(wells variety.
Whereas it is generally required to simplify the processing of semiconductor devices as much as
possible, and as will be described hereinafter the
processing required to manufacture the structure of
Fig. 2 involves manual change to a conventional
CMOS process, in certain applications more complex processing may be necessitatedforvarious reasons.
For example, the use of epitaxial layers on low resistivity substrates is currently recommended to minimise latch-up in CMOS. Latch-up occurs when a lateral thyristorwhich exists between the power rails, and is, for example constituted by p+ source, n substrate, p well and n+ source, is turned on by a transient current pulse. A low resistivity layer beneath the active n region will tend to short the p+n junction so holding off the p-n-p transistor in the composite device. Such a structure is most easily obtained in p-well (MOS by using epitaxial nor n+ starting material. Alternatively for n-well CMOS epitaxial p or p+ starting material could be used.Lateral bipolar devices as in Fig. may be provide in the wells comprising doped portions extending completely through an epitaxial layer, and a buried n+ layer could be added to further improve the transistor's performance. Whereas then + regions will improve latch-up tolerance, the added complexity of the processing involved is liable to result in yield disadvantages and may degrade CMOS performance. The latch-up problem is also inherent in the Fig. 6 structure, since the substrate thereof is connected in use to the supply line.
The various processing stages which may be employed to fabricate the structure of Fig. 2 may comprise a sequence of steps which will now be describedwith referenceto Figs.9to 15. Usingafirst mask (not shown} a layer of silicon nitride 30, orsilicon nitride on silicon dioxide, deposited on the surface of a p-type silicon substrate 31 is patterned to distinguish between subsequently-formed wells, other device areas, and areas in which field oxide is to be grown.
Areas of nitride 30 are left on the surface ofthe substrate 31 at positions corresponding to the wells and other device areas, as indicated in Fig. 9. Field dopant (notshown) may be implanted into the surface of substrate 31 throughthewindowsopened in the nitride layer 30, byforexample ion implantation of boron. The substrate is then oxidised in orderto form field oxide 32 in the windows. The areas of nitride 30 are etched away and the substratefurtheroxidised in orderto obtain thin oxide areas 33 between the thick field oxide areas 32 (Fig.10). A second mask (not shown) is employed to define n-type wells, which masking is such as to leave photoresist 34 (Fig.11) over those of the thin oxide areas 33 where n-type wells are notto be formed. N-type regions 35 are ion implantedusing,forexample, phosphorus. There gions 35 are driven in to form n-type well 35a, as indicated in Fig. 12. Athird mask (not shown) is employed to define windows 36 in a photoresist layer 37, through which windows 36 p-type dopant, for example boron, is ion implanted to produce a base region 38 for a lateral bipolartransistor. The base region 38 is driven in, as indicated in Fig. 13, the photoresist 37 removed, and a fourth mask (not shown) employed to pattern a layer of undoped polycrystalline silicon 39. Then p+ dopant, for example boron, is implanted through windows 40 in the polycrystalline silicon 39 to provide a base contact 41 forthe lateral bipolartransistor and a source 42 and a drain 43forthe p-channel MOS device.During the course of this implantation the polycrystalline silicon will become p+ also. If p+ polycrystallinesiliconisto be avoided, the initially undoped polycrystalline silicon layer may be replaced by n+ doped polycrystalline silicon, or alternatively it may be sheet implanted with phosphorus or arsenic, before pattern ing, and the photoresist left on before the p+ dopant implantation. The polycrystalline silicon 39 is then patterned using a fifth mask (not shown) to define the gate 44forthe n-channel MOS device and windows 45 and 46forthe emitter and the collector contact of the lateral bipolartransistor. The photoresist 47 employed forthefifth masking being left on as indicated in Fig.
14. An n+ dopant, for example arsenic, is then ion implantedto provide source and drain regions 48 and 49forthe n-channel MOS device and the emitter 50 and the collector contact 51 forthe lateral bipolar device. Using a sixth mask (not shown) a layer of photoresist 52 is patterned to define a window 53 (Fig.
15)through which p-type dopant is implanted to provide the active base region 54, corresponding to region 7" in Fig.2, atthe edge of the emitter 50 and overlapping base region 38. The photoresist 52 is removed, the then exposed polysilicon oxidised, and the p-type dopantfor region 54 driven in. Using a seventh mask (not shown) windows are opened in the thin oxide regions 33 for the provision of electrical contactstotheunderlying regions. The thus processed substrate isthen metallised and the metal patterned as appropriate using an eighth mask (not shown). Whilst not described above or shown in the drawings, for reasons of clarity thereof, further masking and processing may be employed, as is conventional, forthreshold tailoring ofthe n-channel and p-channel MOS devices.
As will be appreciated from the above process description the special base structure is achieved therein by driving in the deep base region 38 then opening awindowwhich overlaps the edge of this region 38. The active base region 54 and the emitter 50 will then be defined bythe same opening, with the p region being driven sufficiently far to produce the active base region 54, thus providing self-alignment between the base and the emitter. Other methods may however, be employed to produce a base structure with the required doping profile. The simple approach isto diffuse a deep base region and then to carefully align the emitterwithin it and preciselycloseto its edge.However even if sufficient lateral accuracy can be achieved, the active base width needs to be about 0.25 micrometre, it is problematical whether the required vertical and lateral base doping profiles can be achieved simultaneously by a singly masked base doping step. The base doping profile is required to fall off vertically only gently over about 3 micrometre, whilst its lateral edge should be falling steeply at about 0.5 micrometre from the emitter edge (see Figs.
3a and 3b) in order to obtain optimum lateral operation.
The processing sequence described above for forming bipolar and CMOS devices in a single substrate only involves the addition of one mask and two diffusions to the standard n-type well CMOS process and therefore has the advantage that standard processing with only minor perturbation can be employed.
Another CMOS-compatible lateral bipolar transistor structure is shown in Fig. 16, which structure has low base resistance although somewhat greater complex- ity processing is required. The structure is based on n-well CMOS and incorporates an oxide island 60 which together with an edge 61, which may be presented by a polycrystalline silicon, oxide or resist layer 62, provides self-alignment of the emitter 63 and an active base region 64. The n-well 65 comprises the collector ofthe device, there being a collector contact 66 and a base contact 67. The base is comprised of a highly doped region 68 and an adjoining more lightly doped region 69 which includes the active region 64.
The emitter-base structure being chosen for optimum lateral operation. The basic steps required to manufacture this structure comprise etching holes in the n-type wells 65, which holes will be subsequently filled with oxide to provide islands 60; heavily doping the bottom of the holes with a p+ dopant (68); growing silicon dioxide to fill the holes; implanting and driving in boron to form the p-type base region 69 using edge 61 of layer 62 for alignment purposes; implanting an n+ dopant to form the emitter 63 and the collector contact 66; and implanting a p+ dopant to form the base contact 67. During processing the p+ dopant (68) out-diffuses and joins the p base region 69, thus providing a low base resistance path under the island 60.The length ofthe emitter 63 is determined by the oxide island and the edge, which also serve to self-align the emitter and the active base region 64. As with the previously described embodiments the base contact, the collector contact and the emitter may be provided by then n+ orp+ diffusions (as appropriate) employed to form the CMOS source and drain regions. The processing involved forthe embodimentof Fig. 16 is more complexthan that required for other embodiments, but it has the advantage of low base resistance and self-alignment, although with small device depths care must be taken thatthereisnottoomuchout-diffusionfrom p+ dopant (69) and encroachment on the emitter region 63.
For boron doped base regions in n-well CMOS there will be a tendencyforthe boron in the base to segregate to the oxide at the silicon-oxide interface.
This will tend to deplete the base of dopantjust below this interface giving rise to the possibility of inversion and parasitic MOS effects. These will be affected by surface change effects. It may therefore be useful to place a field plate over this region in orderto control the local surface potential and the oxide interface change. The MOS gate material could be employed for
such a field plate.
It is considered that recently proposed processing techniques could be used to advantage in the manufacture ofthe combined bipolar and CMOS circuits. In particular pulsed thermal annealing as disclosed for example in ourco-pending Application No.8203242 (Serial No. ) (J. M. Young etal 8-1x and our co-pending Application No.81 28127 (Serial No.
2106709) (P. D. Scovell 3) could be usefully employed to anneal implantation damage and to reactivate dopants after low temperature processing. For high speed application, low resistivity interconnects mak ing use ofsilicides, as disclosed in ourco-pending Application No. 83 12280 and 8312281 (Serial Nos.
and ) (P. D. Scovell eta 5-3-2 and P.
D. Scovell etal 7-4-3) could be employed.
Claims (15)
1. An integrated circuit including a field effect portion and a bipolar portion, wherein the bipolar portion includes a bipolartransistorwhose baseemitter structure is such as to define a narrow active base region whembyto provide optimum lateral operation of the transistor.
2. An integrated circuit as claimed in claim 1, wherein the field effect portion includes a CMOS (complementary metal oxide silicon) portion employing n-type wells, wherein the bipolartransistor is constructed in a respective n-type well which comprises the collector of the transistor, the base of the transistor being comprised by a p-type region diffused or implanted into a portion ofthe collectorwell and the emitter ofthe transistor being comprised by an n-type region diffused or implanted into a portion ofthe base closely adjacentto a lateral boundary thereofwhereby to define said narrow active base region between the perimater ofthe emitter adjacent to the collector and the colletor,the base impurity profile being selected for optimum lateral operation of the transistor.
3. An integrated circuit as claimed in claim 2, wherein the base is deep and highly doped where it lies below the emitter whereby to suppress downward carrier injection and minimise base series resistance to the narrow active base region, the narrow active base region being relatively lightly doped.
4. An integrated circuit as claimed in claim 1, whereinthefield effect portion includes a CMOS (complementary metal oxide silicon) portion employing p-type wells, wherein the bipolar transistor is constructed in a respective p-type well which comprises partofthe base region ofthetransistor, another partofthe base region ofthetransistor being comprised by a more highydoped p-type region diffused or implanted into a portion ofthe p-type well ofthetransistor, the emitter ofthe transistor being comprised by an n-type region diffused or implanted into the other part of the base region closely adjacent to a lateral boundary thereof, whereby to define said narrow active base region, and the collector of the transistor being comprised by an n-type region diffused or implanted into the p-type well part of the base region, the p-type well being depleted between the narrow active base region and the collector whereby to constitute a drift region for carriers.
5. An integrated circuit as claimed in claim 1, whereinthefield effect portion includes a CMOS
(complementary metal oxide silicon) portion em
ploying p-type wells, wherein the bipolartransistor
employs a respective p-type well in its construction, wherein part ofthe base region ofthe bipolar transistor comprises a more highly doped p-type region diffused or implanted into the well, wherein the emitter and the collector ofthetransistorare formed in
respective n-type doped silicon portions which are arranged on respective spaced apart oxide portions overlaying the respective p-type well, and wherein said narrow active region ofthe base is comprised by a part of a respective silicon portion overlying the p-type well between the n-type doped silicon portions, which part of the respective silicon portion is in contactwith the said base region part and doped p-type by out-diffusion therefrom.
6. An integrated circuit as claimed in claim 1, wherein the field effect portion and the bipolar portion are formed in respective doped silicon islands disposed on an insulating substrate.
7. An integrated circuit as claimed in claim 6, wherein the bipolar portion comprises a p-type doped island, wherein partofthe base region ofthe bipolar transistor comprises a more highly doped p-type region diffused into the p-type doped island, wherein the emitter of the transistor is comprised by an n-type region diffused or implanted into the one part of the base region closely adjacent to a lateral boundary thereofwherebyto define said narrow active base region, and wherein the collector of the transistor is comprised by an n-type region diffused or implanted into the p-type doped island, which comprises another part of the base of the transistor, the p-type island being depleted between the narrow active base region and the collector whereby to constitute a drift region for carriers.
8. An integrated circuit as claimed in claim 1, wherein the field effect portion includes a CMOS (complementary metal oxide silicon) portion employing n-type wells, wherein the bipolar transistor is constructed in a respective n-type well which comprisesthe collector of the transistor, wherein the base of the transistor includes a more highly doped p-type region, disposed witin the well and extending from under a dielectric island extending into the well from a surface ofthe circuit, and a less highly doped p-type region diffused or implanted intothewell at least partially around the island and contiguous with the more highly doped region, wherein the emitter of the transistor comprises an n-type region diffused or implanted into the less highly doped p-type region between the island and an edge of a dielectric layer, which edge is presentforthe diffusion or implantation of the less highly doped p-type region, whereby the emitter and base are self-aligned and said narrow active base region is adjacent the emitter and extends underthedielectriclayerfrom said edgethereof.
9. An integrated circuit including a field effect portion and a bipolar lateral transistor substantially as herein described with reference to and as illustrated in Fig. 2, with or without reference to Figs. 3a, 3b, 4a and 5, Fig. 6, Fig. 7, Fig. 8 or Fig. 16 ofthe accompanying drawings.
10. Amethodofmanufacturingan integrated circuit including a field effect portion and a bipolar lateral transistor substantially as herein described with reference to and as illustrated in Figs. to 15 of the accompanying drawings.
11. A method of manufacturing an integrated circuit including an n-type well CMOS portion and a bipolar lateral transistorsubstantiallyas herein de scribed with reference to Fig. 1 6 of the accompanying drawings.
12. A bipolar lateral transistor having a baseemitter structure including a narrow active base region such asto provide optimum lateral operation of the transistor.
13. A bipolar lateral transistor as claimed in claim 12 comprising a p-type substrate in which is arranged an n-type well constituting the collector of the transistor, a p-type region arranged in the n-type well and constituting the base ofthe transistor and an n-type region, constituting the emitterofthe transistor, arranged in the p-type base region and disposed closely adjacent to a lateral boundary thereof whereby to define said narrow active base region between the perimeter of the emitter and the collector, the base p-type region being deep and highly doped underthe emitter and being narrow and relatively lightly doped atthe active region.
14. A bipolar lateral transistor as claimed in claim 12 comprising an n-type substrate in which is arranged a p-type well comprising partofthe base of the transistor, a more heavily doped p-type region arranged in the p-type well and comprising another part of the base, an n-type region constituting the emitter of the transistor arranged in the p-type region and disposed closely adjacent to a lateral boundary thereofwherebyto define said narrow active base region thereat, and an n-type region constituting the collector of the transistor arranged in the p4ype well, the p-type well being depleted between the narrow active base region and the collectorwherebyto constitute a drift region for carriers.
15. A bipolar lateral transistor as claimed in claim 12 comprising a p-type substrate in which isarranged an n-type well constituting the collector ofthe transistor, wherein the base of the transistor includes a more highly doped p-type region, disposed within the well and extending from under a dielectric island extending into the well from a surface of the substrate, and a less highly doped p-type region disposed in the well, and at least partially surrounding the island and contiguous with the more highly doped region, wherein the emitter of the transistor comprises an n-type region disposed in the less highly doped base region between the island and an edge of a dielectric layer, which edge is presentforformation ofthe less highly doped p-type region, whereby the emitter and base are self-aligned and said narrow active base region is formed adjacent the emitter and extending underthe dielectric layerfrom said edge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08318320A GB2143082B (en) | 1983-07-06 | 1983-07-06 | Bipolar lateral transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08318320A GB2143082B (en) | 1983-07-06 | 1983-07-06 | Bipolar lateral transistor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8318320D0 GB8318320D0 (en) | 1983-08-10 |
| GB2143082A true GB2143082A (en) | 1985-01-30 |
| GB2143082B GB2143082B (en) | 1987-06-17 |
Family
ID=10545330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08318320A Expired GB2143082B (en) | 1983-07-06 | 1983-07-06 | Bipolar lateral transistor |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2143082B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2581248A1 (en) * | 1985-04-26 | 1986-10-31 | Efcis | METHOD FOR MANUFACTURING FIELD EFFECT TRANSISTORS AND SIDE BIPOLAR TRANSISTORS ON THE SAME SUBSTRATE |
| US4727046A (en) * | 1986-07-16 | 1988-02-23 | Fairchild Semiconductor Corporation | Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases |
| US4970174A (en) * | 1987-09-15 | 1990-11-13 | Samsung Electronics Co., Ltd. | Method for making a BiCMOS semiconductor device |
| EP0396948A1 (en) * | 1989-04-21 | 1990-11-14 | Nec Corporation | Bi-cmos integrated circuit |
| DE4137101A1 (en) * | 1991-02-28 | 1992-09-03 | Daimler Benz Ag | LATERAL SEMICONDUCTOR COMPONENT |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1470211A (en) * | 1973-05-07 | 1977-04-14 | Fairchild Camera Instr Co | Semiconductor devices |
| EP0036319A1 (en) * | 1980-03-19 | 1981-09-23 | Hitachi, Ltd. | Semiconductor device |
-
1983
- 1983-07-06 GB GB08318320A patent/GB2143082B/en not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1470211A (en) * | 1973-05-07 | 1977-04-14 | Fairchild Camera Instr Co | Semiconductor devices |
| EP0036319A1 (en) * | 1980-03-19 | 1981-09-23 | Hitachi, Ltd. | Semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2581248A1 (en) * | 1985-04-26 | 1986-10-31 | Efcis | METHOD FOR MANUFACTURING FIELD EFFECT TRANSISTORS AND SIDE BIPOLAR TRANSISTORS ON THE SAME SUBSTRATE |
| EP0203836A1 (en) * | 1985-04-26 | 1986-12-03 | STMicroelectronics S.A. | Method of producing field effect transistors and bipolar lateral transistors in the same substrate |
| US4727046A (en) * | 1986-07-16 | 1988-02-23 | Fairchild Semiconductor Corporation | Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases |
| US4970174A (en) * | 1987-09-15 | 1990-11-13 | Samsung Electronics Co., Ltd. | Method for making a BiCMOS semiconductor device |
| EP0396948A1 (en) * | 1989-04-21 | 1990-11-14 | Nec Corporation | Bi-cmos integrated circuit |
| DE4137101A1 (en) * | 1991-02-28 | 1992-09-03 | Daimler Benz Ag | LATERAL SEMICONDUCTOR COMPONENT |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2143082B (en) | 1987-06-17 |
| GB8318320D0 (en) | 1983-08-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19930706 |