GB2137029A - Switching Control Circuit for DC/AC Inverter - Google Patents

Abstract

The control circuit includes a pair of switching circuits 14, 16 which measure the anode-cathode voltage and the current flowing through respective control thyristors 22, 24 of the inverter thereby to inhibit a gate control signal responsive to an on-off command signal when (i) the anode-cathode voltage falls below a predetermined value, (ii) the current flowing through the thyristor exceeds a predetermined unsafe level, or (iii) upon the occurrence of an inadequate power supply to the gate by circuits. The turn-off and turn-on delay periods of the thyristors may be complementary in duration thereby to assure complete turn-off of one thyristor before a second thyristor conducts in order to decrease the likelihood of short circuits across the poled thyristors. When the gate control triggering signal is inhibited in response to one of the detected unsafe conditions, the gate driver inhibit is preferably sustained for a duration to allow normal turn-off in response to the on-off command signal thereby to permit re- initialization of the power circuits of the gate driver. Also, sustaining of the inhibit condition permits sufficient time for a master control device to recognize the detection of the unsafe condition and to alter its state of operation accordingly. <IMAGE>

Description

SPECIFICATION Switching Control Circuit for DC/AC Inverter Background of the Invention This invention pertains to inverters for a.c.

motors, but more particularly, to a switching control circuit for controlling the switching operations of inverters used for controlling the power supplied to an a.c. motor.

In an inverter circuit, switching devices arranged typically in a poled configuration are used to route current alternately in respective circuit paths in an a.c. motor. A source of direct current power from a converter generally supplies power to the inverter over positive and negative d.c. bus bars or rails. The switching devices, in turn, are alternately switched to pass current in different circuit paths to the respective poles of an a.c. motor. To avoid a short circuit condition across the d.c. rails of the inverter, the switching devices must not simultaneously conduct. This requires appropriate timing of the control signals to the different switching devices.

Further, there is a possibility that the load current flowing through the poled output of the inverter at times may exceed its rated current.

This, too, can have adverse effects on the inverter or the a.c. motor which it controls.

Summary of the Invention Obviating the aforementioned disadvantages, this invention provides a switching control circuit which is useful for regulating the switching operations of an inverter used in a poled configuration, which inverter is adapted to power an a.c. motor.

An additional objective of this invention is to provide a switching control circuit for inhibiting the flow of current through an inverter when the current exceeds a predetermined level. Optionally, the invention provides a switching circuit for an inverter which inhibits switching operations of the switching devices when the gate drive power falls below a predetermined level thereby to prevent further operation of the inverter until power supplies are satisfactory. As another optional feature, the invention provides a switching control circuit for an inverter which ensures sufficient time to reinitialize the gate drive circuit after momentary inhibiting resulting from detection of a fault condition.As a secondary feature, the invention provides appropriate turn-on and turn off delays in the switching control circuit for the switching devices used in a poled configuration so as to avoid simultaneous conduction of the switching devices thereby to reduce the likelihood of short circuits in the inverter.

The invention generally resides in a switching control circuit which is connectable to a power source, for use in an a.c. motor inverter circuit, the control circuit comprising: first and second rectifying means for alternately routing current from said power source through respective first and second current paths of the a.c. motor each said rectifying means including gate means responsive to the occurrence of a triggering signal for effecting conduction thereof and responsive to the absence of said triggering signal to terminate conduction thereof; first and second control means associated respectively with said first and second rectifying means for controlling generating respective triggering signals in response to an on-off command signal, each said control means including voltage sensing means for sensing the voltage across said rectifying means; and timing and control means for not enforcing said triggering signal when the voltage across said rectifying means falls below a predetermined level.

A preferred embodiment described herein provides a switching control circuit connectable to a source of power for use in an inverter, which control circuit comprises first and second gate drivers for alternately controlling conduction of respective first and second switching devices of an inverter pole, in response to an on-off command signal, and wherein each gate driver includes a voltage sensor for monitoring the voltage across the associated switching device and a current sensor for monitoring the current through the switching device being operative for appropriately modifying the output of the gate driver when the voltage across the respective switching device falls below a threshold, or, the current flowing through the respective switching device exceeds a predetermined level.By the foregoing arrangement, the switching controller protects the inverter and load from excessive currents.

Additional aspects of the described embodiment include the use of power source monitors for inhibiting the switching operations when the power supply falls below a certain level.

Also, the control circuits provide for inactive periods during the turn-off and turn-on of the triggering signals to ensure sufficient time to reinitialize the control circuits after momentary inhibiting of the triggering signal, as well as the use of complementary turn-on and turn-off delay periods of the gate drivers to reduce the likelihood of simultaneous conduction of the switching devices thereby to avoid short circuit conditions.

Other features, aspects, and advantages of the invention will become more readily apparent upon review of the succeeding disclosure taken in connection with the accompanying drawings. The invention, however, is pointed out with particularity in the appended claims.

Brief Description of the Drawings A more detailed understanding of the invention may be had from the following description of a preferred embodiment to be studied in conjunction with the accompanying drawing in which: Figure 1 depicts a functional block/circuit diagram of an inverter pole circuit including the switching control circuit of an embodiment of the invention.

Figures 2A and 2B, together depict a detailed circuit diagram of one of the switching control circuits of Figure 1.

Figures 3 and 4 are timing diagrams illustrating the operation of the detailed circuit diagram of Figures 2A and 2B.

Description of the Preferred Embodiment Figure 1 depicts an inverter circuit connected in a poled configuration in which a source of d.c.

power is supplied over conductive d.c. rails 10 and 12. An on-off command signal from a conventional master control device, not forming part of the present invention, alternately activates gate drivers 14 and 1 6 over respective input leads 1 8 and 20. In response to activation, for example, the gate driver 1 4 asserts a triggering signal over conductor 1 9 which is supplied to a control gate of a switching device 22, which may comprise a gate turn-off thyristor (GTO). Likewise, when activated, the gate driver 1 6 supplies a triggering signal over a conductor 21 which couples the control gate of a similar switching device 24.

Depending upon which switching device 22 or 24 is conducting, a poled output conductor 26 either pushes current in one direction or pulls current in an opposite direction thereover. More specifically, when switching device 22 is conducting and switching device 24 is nonconducting, current flows in the direction of the arrow indicated at conductor 26 through a pole of an a.c. motor. On the other hand, when switching device 22 is non-conducting and switching 24 conducts, current flows from the conductor 10 through another pole of an a.c. motor and then in a direction opposite the arrow shown with the conductor 26. In either case, conductor 1 2 provides a current return path during each state of the switching devices 22 and 24. When both switching devices 22 and 24 conduct, then a short circuit condition arises between the conductors 10 and 12.The presence of this condition is to be avoided. Therefore, it is important that the triggering signals for the switching devices 22 and 24 be controlled in a fashion so as to avoid a short circuit condition as well as to control the timing operations of the triggering signals to improve the overall efficiency and performance of the inverter. Other functions as well are provided by the gate drivers 14 and 1 6 and will be understood by the description herein.

To attain the objectives of the invention, each of the gate drivers 1 4 and 1 6 senses anode voltage and load current of the respective switching devices 22 and 24. As shown in Figure 1 , the gate driver circuit 14 senses anode voltage of switching device 22 over a conductor 28 and senses load current flowing through the switching device 22 by way of a current sensor 30 which may, for example, comprise a low-value resistor, in which case, the level of the voltage signal appearing across the conductors 32 and 34 is proportional to the current flowing through switching device 22.Similarly, a conductor 36 carries a voltage signal of the anode of the switching device 24 to the gate driver circuit 1 6 and a current sensor 38 develops a voltage proportional to the current flowing through the device 24 over the conductors 40 and 42 which couples the gate driver circuit 1 6.

Each of the gate drivers 14 and 16 has associated with it turn-on and turn-off delay periods resulting from slight delay of the switching device to instantaneously respond to the triggering signal applied to its control gate.

The turn-off and turn-on delay periods are relatively small, that is, approximately 20-50 nanoseconds, however, these delay periods are significant when considering the rigors of the timing sequence of switching to be performed by the switching devices 22 and 24.

As described herein, the switching devices are selected so that the inherent turn-on delay period exceeds its inherent turn-off delay period. In this fashion, if a turn-on triggering signal is applied to the control gate of one switching device 22 simultaneously with the deassertion of the corresponding switching signal for the other switching device 24, an inherent short-circuit protection feature results therefrom in that one switching device cannot actually conduct before the other switching device turns off. This arrangement is particularly advantageous in an inverter circuit connected in the poled arrangement as shown in Figure 1. The turn-off and turn-on delay periods of switching device 22 also are coordinated with the R-C discharge time provided by a capacitor 44 and resistor 46 coupled across the switching device 22.The capacitor 44 and resistor 46, in conjunction with a diode 48, establishes a high voltage dv/dt suppression network across the device 22 during on-off switching thereof. Similarly, a capacitor 50, resistor 52, and diode 54 establish a corresponding high voltage dv/dt suppression network for the switching device 24 during on-off switching thereof.

Figures 2A and 2B depict a detailed circuit diagram of one of the gate driver circuits 14 and 1 6 shown in Figure 1. As both driver circuits 14 and 1 6 are identical, the circuit of Figures 2A and 2B will be described in connection with the gate driver circuit 14 in Figure 1. With reference to Figures 2A and 2B, an on-off command signal from a conventional master control switching device is applied across terminals 60 and 62, the magnitude signal being limited by resistor 64. The master control device (not shown) is optically isolated from the gate driver circuit by an optical coupler 66 constituted by a light emitting diode (LED) and phototransistor array. To measure anode voltage of switching device 22 (Figure 1), the conductor 28 carries an anode voltage signal to the gate driver circuit. This anode voltage signal also is current-limited by resistor 68. A triggering signal for controlling the control gate of switching device 22 is carried over terminal pair 70 and 72. These terminals correspond to conductors 1 7 and 19, respectively, of Figure 1.

Conductor pair 32 and 34 provide a circuit path for the current sensor 30 of Figure 1. A source of power for the gate driver circuit 1 4 is tapped from the a.c. power source by a transformer 78 having its primary winding connected to an a.c. power source. A center tap secondary winding supplies alternating current to a bridge rectifier 80 which, in combination with capacitors 82 and 84, provide a positive voltage source +V1 and a negative voltage source -V, of d.c. power for the gate driver circuit 14. Further, a pair of terminals 86 and 88 produce a status check signal, which also is isolated from the gate driver circuit 14 by way of an optocoupler 90 constituted by a light emitting diode and a phototransistor.

In the preferred embodiment the voltage regulator 92 establishes a regulated positive voltage +V2 of +5 volts on a conductor 94 and a voltage regulator 96 coupled to the conductor 94 establishes a second regulated d.c. voltage of +V3 of, in the preferred embodiment, approximately +2.5 volts over a conductor 98. A zener diode 100 and a transistor 102 establish a negative regulated d.c. voltage -V4 on conductor 140 of about -8.4 volts. Conductor 108 establishes a floating ground reference level between the regulated voltages supplied on conductors 94, 98, and 140.The level of the regulated voltages over these conductors depend directly upon the level the alternating source tapped by the transformer 78, and as previously explained, when the voltage levels fall below a predetermined level, the circuit of Figure 2 operates to de-assert (e.g., inhibit) a triggering signal supplied to the gate of switching device 22 through the terminals 70 and 72.

In particular, a positive gate triggering signal for the control gate of GTO 22 is produced by both transistors 110 and a Darlington transistor array 112 (Figure 2A). On the other hand, a negative gate triggering signal (e.g., de-asserted) appears across the terminals 70 and 72 when transistors 1 14. 150 and Darlington transistor arrays 11 6 and 118 (Figure 2B) conduct. Voltage comparators 1 60, 1 62, 1 30 and 120 are comprised of a quad comparator array commercially known as an LM339N. Voltage comparators 194, 192, 173 and 182 are similarly an LM339N.The output stage of each of the voltage comparators is an NPN transistor which "connects" its output to the -V4 rail via the collector-emitter of said NPN transistor when the voltage comparator is "on".

In a standby operation, the on-off command signal applied to terminals 60 and 62 is not asserted, thus, rendering the optocoupler 66 nonconductive. In the non-conductive state, a transistor 122 is non-conductive thereby to turn off voltage comparator 1 24. Furthermore, voltage comparator 130 is "off" and consequently transistors 114 and 1 50 are "on". As such, transistors 110 and 112 are "off" and a negative gate signal (for GTO) 22) is developed across terminals 21 and 22. When the voltage comparator 124 turns on, it couples the bus 1 40 to its output as the output of the quad voltage comparator is the collector of an NPN transistor.

Turn-on results from current flow through the transistor 122 and resistor 126 which places an energizing signal on conductor 128. Conductor 128 couples the inverting input of the comparator 1 24. In this standby state, voltage comparator 1 30 also resides in the "off" condition as its noninverting input couples the conductor 132 to receive a deenergizing signal from the bus 94 through a resistor 1 34. During the "off" condition of the voltage comparator 1 30, its output continuously energizes the base of transistor 11 4 by providing current flow through a diode 136 and resistor 1 38. The base of transistor 114 couples a junction between the diode 136 and resistor 138.The other terminal of resistor 1 38 couples a negative power supply bus 1 40 which has applied to it a controlled negative voltage of, preferably, -7.5 volts. When the transistor 114 conducts, a reverse gate triggering signal is produced at terminals 70 and 72 resulting from the conduction of current over conductor 1 42 which interconnects a positive power supply line 144 through a resistor 1 46 and the controlled negative power bus 1 40. Upon saturation of the transistor 114 during its conducting state, transistor 1 50 conducts in response to a negative potential being placed on the base terminal thereof.In response to the conduction of the transistor 150, transistors 11 6 and 118 also saturate thereby to generate the reverse gate triggering signal across the terminals 70 and 72.

The reverse gate triggering signal disables the rectifier 22 (Figure 1). Current limiting resistors 1 52 and 1 54 limit current flow through the transistors 11 6 and 118, respectively, and a resistor 1 56 limits current flow through the transistor 1 50 during its saturation. Further, an inductor 1 58 limits the rate of rise of the reverse gate triggering signal applied across terminals 70 and 72 when the circuit of Figures 2A and 2B is switched to the standby state.

A positive gate triggering signal appears across the terminals 70 and 72 in response to the assertion of an on-off command signal across the terminals 60 and 62. With reference to the timing diagram of Figure 3 together with the circuit diagram of Figures 2A and 2B, it is seen that transistor 1 22 saturates to an "on" condition in response to the assertion of the on-off command signal (Figure 3-A). A short period later, voltage comparator 124 (Figure 3-E) switches from an off state to an on state during a time period shown as tON-delay depicted in Figure 3-C, which in turn causes the voltage comparator 1 30 to also switch to an "on" state (Figure 3-G). When the voltage comparator 130 switches on, it couples its output to the bus 140 which has a regulated voltage potential of -7.5 volts. In response to turn-on of the comparator 130, the transistor 114 turns off (Figure 3-H) thereby to remove the reverse gate triggering signal (Figure 3-l) at terminals 70 and 72 by turning off transistors 1 50, 11 6 and 11 8.

To hold the comparator 124 in an "on" state, a resistor 1 60 connected in the positive feedback path of the voltage comparator 1 24 places a negative signal on the non-inverting input of the voltage comparator 1 24 as depicted in Figure 3-D. A voltage comparator 162 responds to a change in polarity of the anode voltage of the controlled thyristor 22 of Figure 1. The anode voltage of the thyristor 22 is sensed over conductor 28 to generate a current through resistor 68 thereby to turn on the comparator 1 62 by applying an energizing signal over conductor 164 that is coupled to the inverting input of the voltage comparator 1 62. Therefore, the voltage comparator 120 responds to the output of the voltage comparator 162 by turning off.When the comparator 120 is turned off (Figure 3-J), transistors 110 and 112 conduct to produce the positive gate triggering signal (Figure 3-K) at terminals 70 and 72. Saturation of the transistors 110 and 112 result from a positive potential on a conductor 1 66 which couples a junction between resistors 1 68 and 1 70. Resistor 1 70 couples the positive power supply line 144 while resistor 1 68 couples the output of the voltage comparator 120.When the voltage comparator 120 is off and the transistor 114 does not conduct, a positive potential appears on the conductor 1 66 thereby to saturate the transistors 110 and 11 2. When saturated, a resistor 1 72 limits current flow through the transistor 110 while resistor 1 74 limits current through the transistor array 11 2.

As the controlled thyristor 22 (Figure 1) turns on in response to the assertion of a positive gate triggering signal across the terminals 70 and 72, its anode-cathode voltage drops below a prescribed level established by the resistor 68 and resistor 1 76. In response, the voltage comparator 1 62 changes from an "on" state to an "off" state (Figure 3-F) thereby to turn on the comparator 120 (Figure 3-J) after a time delay t, to terminate the conduction of the transistors 110 and 11 2 (Figure 3-K).As a protective feature of the invention, should for some reason the anode cathode voltage of the controlled thyristor 22 appearing on the conductor 28 increase above a predetermined level after the time period t1, the states of voltage comparators 1 62 and 120 quickly reverse to allow the transistors 110 and 112 to saturate thereby to deliver a positive gate controlled current to the terminals 70 and 72.

This technique of producing positive gate control current only when the controlled thyristor 22 is expected to be conducting, as established by the on status of the on-off command signal appearing at terminals 60 and 62, and when its cathode- anode voltage appearing on conductor 28 is above a certain level, greatly reduces the loading on the power supply which drives the gate control signals.

Normal turn-off of the gate control triggering signal occurs when the on-off command signal changes from an "on" to an "off" state. When the on-off command signal is not asserted, transistor 122 stops conducting (Figure 3-B). A-short period later, as indicated by toFF delay of Figure 3;C, voltage comparator 1 24 changes from an "on" to an "off" state (Figure 3-E), voltage comparator 1 30 changes from an "on" to an "off" state (Figure 3-G), and transistor 114 (Figure 3-1) saturates and turns on. In response to the turn-on of transistor 11 4, transistors 1 50, 11 6 and 11 8 also turn on to establish a reverse gate across the terminals 70 and 72 as previously explained.The toFF delay period establishes a minimum on time of conduction for the controlled thyristor 22. This minimum period is coordinated with the R-C discharge time provided by the dv/dt suppression network to assure proper discharge of the capacitor 140 before an attempt is made to turn off the thyristor.

The toFF delay and the toN delay periods greatly reduce the susceptibility of the gate driver circuit to noise and "fault" signalling. Furthermore, the delay periods are arranged so that the tow delay is of longer duration than the toFF delay period. This arrangement permits the pair of on-off control signals applied to both the gate drivers 14 and 1 6 to be complementary to provide sufficient time for the off-going thyristor to turn off and recover before its companion thyristor turns on. In practice, the nominal values of the toN and toFF delay periods are 50 microseconds and 20 microseconds, respectively. The circuit, however, is not necessarily limited to these specific delay periods.

The gate driver circuit of Figures 2A and 2B also inhibits the positive gate triggering signal when the current through the thyristor 22 exceeds a predetermined level. As previously indicated, the signal proportional to the current flow through the controlled thyristor 22 appears across the terminals 32 and 34 of Figure 2B which corresponds to the correspondingly numbered terminals of Figure 1. Voltage comparator 1 72 responds to the sensed current passing through the current sensor 30 (Figure 1) in that it turns on to couple its output to the -7.5 volt bus 1 40 when the voltage signal on terminals 32 and 34 exceed a predetermined level.Coupled to the inputs of the voltage comparator 172 are resistors 1 74 and 1 76 which limit the current to the comparator and resistors 178 and 180 for equalizing the trip level of the current sensors between each of the gate driver circuits 14 and 16. When the voltage comparator 1 72 turns on - as depicted in Figure 4-H, the voltage comparator 182, after a time delay t2, also turns on to -deenergize the voltage comparator 130 and force it to an "off" state (Figure 4-d) if it had previously been on. With the voltage comparator 1 30 in the "off" state, transistor 114 conducts (Figure 4-F) thereby to apply a reverse gate triggering signal (Figure 4-G) across the terminals 70 and 72 as previously explained.

In addition to turning on the voltage comparator 182, the voltage comparator 1 72 also couples a -7.5 volt signal on conductor 184 which in turn causes a transistor 1 86 to become non-conductive a.s its base is coupled through a diode 188 to the conductor 184. As such, an unsafe status check signal is developed across the terminals 86 and 88 which optically are isolated from the gate driver circuit of Figures 2A and 2B by way of optocoupler 90 connected to the emitter of the transistor 186 through a current limiting resistor 1 90.

Voltage comparators 192 and 194 monitor respectively the levels of the negative and positive power supplies appearing over conductors 106 and 144 respectively. In particular, the level of the voltage on power bus 144 is tapped from a pair of resistors 196 and 1 98 coupled to the bus 144, the signal being applied to the non-inverting input of the comparator 194. On the other hand, the comparator 1 92 receives a representation of the voltage appearing on bus 106 through its noninverting input at a junction 200 coupled through a capacitor 202 to the emitter of the voltage control transistor 102.When either of the voltage comparators 1 92 or 1 94 detects undervoltage on the busses 106 or 144, it couples to the conductor 1 84 the voltage reference of a bus 140 thereby to change the states of voltage comparators 172 and 182 which de-assert the gate drive signal appearing across terminals 70 and 72, as previously explained. The voltage comparators 192 and 194 also disable the transistor 1 86 which in turn energizes a status check signal across the terminals 86 and 88 as previously explained.

The comparator 1 82 will only become energized to an "on" state when any of the comparators 172, 192 or 194 remain in an "on" condition for a period of time T2 indicated in Figure 4-í. Further, the reverse gate triggering signal across the terminals 70 and 72 will be sustained as long as the voltage comparator 1 82 remains in an "on" state.After the comparator 1 82 becomes energized, it remains so for a duration at least as long as a period T3 (Figure 4-l) after all of the comparators 1 /2, I Y2 and 1 94 return to their "safe" off states, Preferably, the time period t2 is designed to match the toFF delay period of Figure 3-C so that proper discharge of the R-C suppression network is not compromised.

Further, the time period t3 is designed to allow sufficient time for an "unsafe" status check condition to be recognized by the master control device. Such a time period enables the master control device to turn off the on-off command signal, thereby to establish a normal de-assertion of the gate control triggering signal before the comparator 182 would return to an off condition.

From the above arrangement, it is seen that the gate drive power for producing the triggering signals is minimized, the controlled thyristors are protected from excessive current flowing therethrough, and that the thyristors are shut down when the power supply becomes inadequate. Furthermore, it is seen that certain active time periods during turn-on and turn-off of the gate control signals ensure sufficient time to reinitialize the power circuits before resuming normal on-off switching operations by the on-off command signal. Additionally, providing complementary turn-on and turn-off delay periods, the control thyristors uniquely ensure against short circuits resulting from simultaneous conduction of the controlled thyristors.

It is also apparent that several alternative forms of the invention can be constructed in view of the above teachings. In particular, the values of the circuit components may be selected according to the voltage levels of the power circuits and the frequency of switching to be performed by the controlled thyristors.

Accordingly, it is not the intent to limit the invention to exactly what is shown or described, but to include all such modifications, arrrangements and variations as may come to those skilled in the art to which this invention pertains.

Claims (8)

1. A switching control circuit which is connectable to a power source, for use in an a.c.

motor inverter circuit, the control circuit comprising: first and second rectifying means for alternately routing current from said power source through respective first and second current paths of the a.c. motor, each said rectifying means including gate means responsive to the occurrence of a triggering signal for effecting conduction thereof and responsive to the absence of said triggering signal to terminate conduction thereof; first and second control means associated respectively with said first and second rectifying means for controlling generating respective triggering signals in response to an on-off command signal, each said control means including voltage sensing means for sensing the voltage across said rectifying means; and timing and control means for not enforcing said triggering signal when the voltage across said rectifying means falls below a predetermined level.

2. A switching control circuit as recited in claim 1 wherein each of said first and second control means further includes current sensing means connected to said timing and control means for sensing the current flowing through said associated rectifying means and wherein said timing and control means is further operable for deactivating and inhibiting said triggering signal when the current flowing through said associated rectifying means exceeds a predetermined level.

3. A switching control circuit as recited in claim 1 wherein each control means further includes power source monitoring means connected to said timing and control means for monitoring the level of said source of power and wherein said timing and control means is further operable for deactivating and inhibiting said triggering signal when the voltage of said source of power falls below a predetermined level.

4. A switching control circuit as recited in claim 2 wherein each control means further includes power source monitoring means connected to said timing and control means for monitoring the level of said source of power and wherein said timing and control means is further operable for deactivating and inhibiting said triggering signal when the voltage of said source of power falls below a predetermined level.

5. A switching control circuit as recited in claim 3 further including time delay means for delaying normal switching operations by said on-off command signal after said control means inhibits said triggering signal thereby providing a recovery period for said switching control circuit before resuming further switching operations.

6. A switching control circuit as recited in claim 4 further including time delay means for delaying normal switching operations by said on-off command signal after said control means inhibits said triggering signal thereby providing a recovery period for said switching control circuit before resuming further switching operations.

7. A switching control circuit as recited in claim 5 wherein said first and second rectifying means have complementary turn-off and turn-on delay periods thereby to reduce the likelihood of simultaneous conduction of said first and second rectifying means.

8. A switching control circuit as recited in claim 6 wherein said first and second rectifying means have complementary turn-off and turn-on delay periods thereby to reduce the likelihood of simultaneous conduction of said first and second rectifying means.