GB2135548A - Amplifier arrangement - Google Patents

Abstract

The inputs (3, 4) for a differential amplifier are connected through respective level shift stages (T4, R6, S1 and T5, R7, S2) to the bases of respective transistors (T1, T2). The emitters of these transistors (T1, T2) are connected through respective resistors (R1, R2) to a current source (T3, R5) whilst the collectors are connected to respective collector load resistors (R3, R4). The output (5, 6) is also connected to the said collectors and in order to ensure that the common mode voltage of this output follows the level present at one of the input terminals (4) this terminal is connected to the inverting input of a differential amplifier (A) whose non- inverting input is connected to the junction of equal value resistors (R8, R9) connected between the collectors of the transistors (T1, T2). The output of the differential amplifier (A) is connected to the current source (T3, R5) to control its current and hence the common mode voltage. <IMAGE>

Description

SPECIFICATION Amplifier Arrangement The invention relates to an amplifier arrangement comprising first and second transistors coupled to form a differential amplifier with the emitters of said transistors being connected to a current source, the collectors of said first and second transistors being respectively coupled to first and second collector loads, the currents through said first and second collector loads from said current source being determined by an input signal applied between the bases of said transistors whilst an output is derived from between the collectors of said transistors.

Such amplifier arrangements are well known and are used to amplify an applied difference signal to produce an amplified difference signal at the output. If there is a change in the levels applied to the bases of the transistors whilst the difference between them remains the same the output will not reflect the change in level but will simply be an amplified version of this difference.

It is an object of the invention to provide an amplifier arrangement in which the output also reflects changes in level at the input.

The invention provides an amplifier arrangement comprising first and second transistors coupled to form a differential amplifier with the emitters of said transistors being connected to a current source, the collector of said first and second transistors being respectively coupled to first and second collector loads, the currents through said first and second collector loads from said current source being determined by an input signal applied between the bases of said transistors whilst an output is derived from between the collectors of said transistors, characterised in that a potential divider is connected between the collectors of said transistors a tap on which provides a voltage corresponding or proportional to the common mode voltage of the amplifier output which voltage is compared with a level associated with said applied input signal in comparison means whose output controls the magnitude of the current produced by said current source and hence the currents through said collector loads in such manner that the common mode voltage in said output follows any changes in the said level in the applied input signal.

When the voltage at the tap on the potential divider equals the output common mode voltage, the potential divider may comprise first and second resistors of equal value the junction between which is connected to the non-inverting input of a second differential amplifier forming the comparison means and whose inverting input is connected to one of a pair of input terminals coupled to the base of said transistors, the output of the second differential amplifier being connected to the base of a third transistor which forms the current source. Each input terminal may be connected to the base of its associated transistor through a respective further transistor providing a shift in the levels of the input signal.

The second differential amplifier may comprise fourth and fifth transistors whose bases respectively form its non-inverting and inverting inputs, the collector of the fourth transistor being connected through a sixth transistor forming an inverter to the output of the second differential amplifier.

The above and other features of the invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 is a diagram of an amplifier arrangement according to the invention, and Figure 2 is a diagram of a more detailed version of the arrangement shown in Figure 1.

In Figure 1 a differential amplifier comprises transistors T1 and T2 whose emitters are connected via respective resistors R1 and R2 to the collector of a third transistor T3 which acts as a current source. The collectors of transistors T1 and T2 are connected through respective collector load resistors R3 and R4 to a terminal 1 connected to the positive terminal of a supply whose negative terminal is connected to a terminal 2 which in turn is connected to the emitter of transistor T3 through a resistor R5. An input signal is applied to the bases of transistors T1 and T2 via respective input terminals 3 and 4 and associated level shift stages, the input signal controlling the relative conduction of transistors T1 and T2 and hence the proportion of the current from the current source (transistorT3) which flows through the collector loads (resistors R3 and R4).The level shift stage associated with terminal 3 comprises a further transistor T4 whose collector is connected to terminal 1 and whose base is connected to terminal 3, the emitter of transistor T4 being connected through a resistor R6 to a current source S1 whose junction is connected to the base of transistor T1, the other side of source S1 being connected to terminal 2. A similar level shift stage associated with terminal 4 comprises a transistor for T5, a resistor R7 and a current source S2. The amplifier amplifies the difference in the levels present in the input signal to produce an amplified signal between output terminals 5 and 6 respectively connected to the collectors of transistors T1 and T2. Without further steps the amplifier output would not reflect any change in the levels applied to terminals 3 and 4 if the difference between these levels remained the same.In one application the input to terminal 3 could be the black level reference and that to terminal 4 the zero-level of chrominance reference of a C-MAC television signal as described in the Independent Broadcasting Authority's Experimental and Development Report 11 8/21, "MAC-A Television System for High-Quality Satellite Broadcasting", August 1 982-see especially Figure 11. These two reference levels nominally differ by 0.5 volts and the output between terminals 5 and 6 would then produce an amplified version of this difference for decoding purposes. The proposed direct broadcast by satellite television transmissions will use the C MAC system where the video signal will be frequency modulated, the video signal being additionally modulated by a frame synchronous energy dispersal signal.This will result in the received demodulated C-MAC signal, including the reference levels, being modulated at frame frequency and with the arrangement so far described the output would not change with this modulation.

The above defect can be overcome by the remaining circuitry shown in Figure 1. Between the collectors of transistors T1 and T2 is connected a potential divider comprising two resistors R8 and R9 of equal value. It can be shown that the voltage at the junction of these resistors will correspond with the common mode voltage of the output between the terminals 5 and 6 and will maintain this relationship even if the current from the current source transistor is changed. This voltage is applied to the noninverting (+) input of a differential amplifier A whose inverting (-) input is connected to the input terminal 4. The differential amplifier A compares its two its two inputs and produces an output depending on the relationship at its two inputs.This output is connected to the base of transistorT3 to control the current applied to transistors T1 and T2. Should there be an increase in the level at terminal 4 (and consequently at terminal 3) the output at amplifier A will be reduced to reduce the current from transistor T3. This in turn will produce an increase in the voltage levels at terminals 5 and 6 and hence produce an increase in the common mode voltage between these outputs. The converse will apply as the level at terminal 4 decreases. In this way the voltages at terminals 5 and 6 will change their levels with changes in level at the input whilst retaining the desired difference between the output terminals.

Figure 2 shows a more detailed version of the arrangement shown in Figure 1 and where corresponding components have been given the same references. In Figure 2 the inverting and noninverting inputs of the differential amplifier A are respectively formed by the base of a transistor T6 and the base of a transistor T7. The emitters of these transistors are commoned and connected to a current source S3 whose other side is connected to terminal 2. The collector of transistor T7 is directly connected to terminal 1 whilst that of transistor T6 is connected to terminal 1 through a resistor R10. The collector of transistor T6 is also connected to the base of a pnp transistor T8 (the other transistors being npn) whose emitter is connected through a resistor R1 1 to terminal 1 and whose collector is connected through a resistor R12 to terminal 2.

Transistor T8 acts as an inverter for the signal at the collector of transistor T6 to ensure the output at the collector of transistor T8, which is connected to the base of transistor T3, has the correct phase relationship with respect to the inputs at the bases of transistors T6 and T7.

Claims (5)

1. An amplifier arrangement comprising first and second transistors coupled to form a differential amplifier with the emitters of said transistors being connected to a current source, the collector of said first and second transistors being respectively coupled to first and second collector loads, the currents through said first and second collector loads from said current source being determined by an input signal applied between the bases of said transistors whilst an output is derived from between the collectors of said transistors, characterised in that a potential divider is connected between the collectors of said transistors a tap on which provides a voltage corresponding or proportional to the common mode voltage of the amplifier output which voltage is compared with a level associated with said applied input signal in comparison means whose output controls the magnitude of the current produced by said current source and hence the currents through said collector loads in such manner that the common mode voltage in said output follows any changes in the said level associated with the applied input signal.

2. An amplifier arrangement as claimed in Claim 1, in which the voltage at the tap on said potential divider equals the output common mode voltage, characterised in that said potential divider comprises first and second resistors of equal value the junction between which is connected to the non-inverting input of a second differential amplifier forming said comparison means and whose inverting input is connected to one of a pair of input terminals coupled to the bases of said transistors, the output of said second differential amplifier being connected to the base of a third transistor which forms said current source.

3. An amplifier arrangement as claimed in Claim 2, characterised in that each input terminal is connected to the base of its associated transistor through a respective further transistor providing a shift in the levels of said input signal.

4. An amplifier arrangement as claimed in Claim 2 or 3, characterised in that said second differential amplifier comprises fourth and fifth transistors whose bases respectively form its noninverting and inverting inputs, the collector of said fourth transistor being connected through a sixth transistor forming an inverter to the output of said second differential amplifier.

5. An amplifier arrangement substantially as herein described with reference to the accompanying drawing.