GB2132453A - Frequency hopping code synchroniser - Google Patents

Abstract

A frequency hopping radio system, comprises a synthesised receiver 2, a comparator 5 fed from the synthesised receiver, a code generator 3 arranged also to feed the comparator, a micro-processor 4 responsive to an output from the comparator, a clock pulse generator 6 which provides a frequency standard for the micro-processor which is effective to provide a hopped trigger signal for the synthesised receiver. <IMAGE>

Description

SPECIFICATION Frequency hopping code synchroniser This invention relates to radio communication systems and more especially it relates to frequency hopping radio communication systems.

Frequency hopping systems are quite well known and comprise systems in which the radiated carrier frequency is changed or hopped repeatedly so that transmission is in effect distributed over a wide frequency band although at any instant occupies a narrow band only.

Frequency hopping is used to afford advantages including improved security and improved resistance to jamming but it introduces technical problems one of which is the problem of achieving synchronisation between a frequency hopping transmitter and a receiver with which it seeks to communicate.

Frequency hopping is usually between frequencies selected in accordance with a pseudo random code whereby the transmitter hops at say 100 hops/sec through a predetermined sequence of frequencies.

It is necessary for a receiver to be in possession of information which enables it to generate the same sequence of frequencies as those of the transmitter. It must therefore "know" the pseudo random code that is being used. In this respect it is distinguished from enemy surveillance or jamming equipment which would in general not possesses this knowledge.

Although the receiver "knows" the code it usually is not in possession of accurate time information which would enable it to set itseif to the same part of the code sequence as that used by the transmitter. The provision of such absolute time accuracy in transmitters and receivers is expensive. Maintenance of synchronism for a useful period of time (say 1 or 2 days at a few hundred hops per second) would r,equire atomic clock accuracy.

A feature of the present invention is the provision of a synchronising equipment which requires a much more modest absolute clock accuracy, such as that readily achieved by a quartz crystal clock, and enables a receiver to use this approximate timing information to establish correct hopping synchronism.

A knowledge of the accuracy of its internal clock and that of the transmitter enables the receiver to establish an upper bound on the number of hops the transmitter and receiver could be out of synchronism. If the receiver sets it pseudo random code generator in advance by this number of hop periods it will always be at a point in the hopping sequence ahead of the transmitter.

The receiver waits on this frequency until it detects the presence of a signal. On the assumption that this signal emanates from the transmitter the receiver hops to the next frequency in the sequence expecting to receive a second signal from the transmitter. If one is detected, the receiver proceeds to the next frequency. The number of such tests applied before the receiver decides it is synchronised may be varied dependent on conditions such as the total number of frequencies in use. In a typical case of hopping between any of 256 frequencies, testing a sequence of four frequencies is normally sufficient and results in a false alarm rate of less than one in a thousand.

If during the previous sequence, the receiver at any frequency fails to detect a signal, it assumes that the correct sequence is not yet being transmitted and waits on this frequency, expecting the correct sequence to occur later, restarting the test at this point.

A time-out is included in the arrangement so that should the receiver fail to achieve synchronism within the maximum relative time difference of the transmitter and receiver clocks, the search is halted, the code generator is again set ahead and a fresh synchronising search is initiated.

In the above description the receiver is said to "detect the presence of a signal". This phrase is meant to cover the detection of radiated power at the particular frequency. As a further protection against deception or jamming it can be advantageous to include a special identifier signal such as a pattern of digits in the transmission which is known only to a receiver possessing the correct code. (The identifier could alter in nature and content for every hop). In this case, the above phrase is used in the sense of detecting such a special identifier signal.

In many applications the most convenient way of frequency hopping a receiver is by frequency hopping its local oscillator to frequencies off-set from those of the transmitter by the amount of the intermediate frequency. The present invention is not however restricted to this implementation and may be used for example with receivers employing tuned filter banks.

One embodiment of the invention will now be described solely by way of example with reference to the accompanying drawing which is a somewhat schematic block diagram of a part of the receiver of a frequency hopping radio equipment.

Referring now to the drawing, a frequency hopping receiver comprises an aerial 1, signals received by which are fed to a synthesised receiver 2 which is also supplied with a frequency word from a code generator 3 and a hop trigger signal from a microprocessor 4.

Output signals, normally in digital form, are passed to an output buffer (not shown) for later processing and also to a comparator 5 which is also supplied with an identifier pattern from the code generator 3.

The function of the comparator 5 is to attempt to match the received signal to the identifier pattern and if it detects a sufficiently close match, to send a "signal presence detected" signal to the microprocessor 4.

The microprocessor 4 receives local timing signals from a receiver clock 6 and sends sequence control signals to the code generator 3.

The microprocessor 4 also maintains a status flag which indicates whether or not the receiver is synchronised.

The events by which the receiver achieves hopping synchronism with the transmitter will no be described. For the purpose of illustration let it be assumed that the system uses a regular hopping rate of 100 hops per second and that each station (transmitter or receiver) has a knowledge of time to an accuracy of better than + 0.2 seconds. This means that if a receiver which has a clock which is running slow is attempting to synchronise to a transmitter having a clock which is running fast, its code generator can be, at most, less than 0.4 second or 40 hops late.

The receiver microprocessor 4 has its synchronisation status flag in the cleared position.

It sets the code generator 3 to a position 40 cycles ahead of the position corresponding to its clock and waits on the particular frequency, and is set to detect the particular identifier pattern, given by that code generator cycle. It also clears it synchronization score register (not shown).

If a signal presence is detected (with sufficient integrity) the comparator 5 informs the microprocessor by sending a "signal presence detected" input.

On receipt of this signal, the microprocessor 4 increments its synchronisation score register and, at the correct hopping rate advances the code generator 3 by one cycle to the next hop frequency.

If this also results in the comparator 5 reporting a further signal present, the synchronisation score register is again incremented and the above process repeated until the synchronisation score register reaches a value of 4 (say).

When this happens, the microprocessor 4 stores the number of cycles by which its code generator has been off-set with respect to its local clock, continues to control its code generator 3 at this off-set time and sets its synchronisation status flag.

If at any time during the above procedure the comparator 5 fails to detect signal presence, the microprocessor 4 clears its synchronisation score register and continues to cause the code generator 3 to remain on the current hop cycle, waiting for a later signal on this frequency.

Eventually, if synchronism is not achieved within a total of 0.4 seconds, the whole process is repeated by setting the code generator 40 cycles ahead of the new current receiver local clock time and trying again.

Once synchronisation has been achieved, as a further check a few more hops continue to be detected. If, say, three out of the next four hops indicate signal presence the synchronisation is confirmed.

The use of these checks ensures that the probability of the receiver falsely asserting that it has achieved synchronisation is extremely small.

Claims (Filed on 21/10/83) 1. A frequency hopping radio system, comprising a synthesised receiver, a comparator fed from the synthesised receiver, a code generator arranged also to feed the comparator, a micro-processor responsive to an output from the comparator, a clock pulse generator which provides a frequency standard for the microprocessor which is effective to provide a hopped trigger signal for the synthesised receiver.

2. A frequency hopping radio system substantially as hereinbefore described with reference to the accompanying drawing.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (2)

**WARNING** start of CLMS field may overlap end of DESC **. The microprocessor 4 also maintains a status flag which indicates whether or not the receiver is synchronised. The events by which the receiver achieves hopping synchronism with the transmitter will no be described. For the purpose of illustration let it be assumed that the system uses a regular hopping rate of 100 hops per second and that each station (transmitter or receiver) has a knowledge of time to an accuracy of better than + 0.2 seconds. This means that if a receiver which has a clock which is running slow is attempting to synchronise to a transmitter having a clock which is running fast, its code generator can be, at most, less than 0.4 second or 40 hops late. The receiver microprocessor 4 has its synchronisation status flag in the cleared position. It sets the code generator 3 to a position 40 cycles ahead of the position corresponding to its clock and waits on the particular frequency, and is set to detect the particular identifier pattern, given by that code generator cycle. It also clears it synchronization score register (not shown). If a signal presence is detected (with sufficient integrity) the comparator 5 informs the microprocessor by sending a "signal presence detected" input. On receipt of this signal, the microprocessor 4 increments its synchronisation score register and, at the correct hopping rate advances the code generator 3 by one cycle to the next hop frequency. If this also results in the comparator 5 reporting a further signal present, the synchronisation score register is again incremented and the above process repeated until the synchronisation score register reaches a value of 4 (say). When this happens, the microprocessor 4 stores the number of cycles by which its code generator has been off-set with respect to its local clock, continues to control its code generator 3 at this off-set time and sets its synchronisation status flag. If at any time during the above procedure the comparator 5 fails to detect signal presence, the microprocessor 4 clears its synchronisation score register and continues to cause the code generator 3 to remain on the current hop cycle, waiting for a later signal on this frequency. Eventually, if synchronism is not achieved within a total of 0.4 seconds, the whole process is repeated by setting the code generator 40 cycles ahead of the new current receiver local clock time and trying again. Once synchronisation has been achieved, as a further check a few more hops continue to be detected. If, say, three out of the next four hops indicate signal presence the synchronisation is confirmed. The use of these checks ensures that the probability of the receiver falsely asserting that it has achieved synchronisation is extremely small. Claims (Filed on 21/10/83)

1. A frequency hopping radio system, comprising a synthesised receiver, a comparator fed from the synthesised receiver, a code generator arranged also to feed the comparator, a micro-processor responsive to an output from the comparator, a clock pulse generator which provides a frequency standard for the microprocessor which is effective to provide a hopped trigger signal for the synthesised receiver.

2. A frequency hopping radio system substantially as hereinbefore described with reference to the accompanying drawing.