GB2132450A - Intra-hop synchroniser - Google Patents

Abstract

A radio receiver for receiving a frequency hopping transmission wherein a plurality of data bits including 'n' sync bits are transmitted between hops comprising a sync code generator 2 which defines from hop to hop the expected character (i.e. 0 or 1) of each of the 'n' sync bits, a first data store 4 responsive to the sync code generator for storing during each hop period the 'n' sync bits expected, a second data store 5 through which the received data bits are passed sequentially, comparator means 10 responsive to the first and second data stores for comparing consecutively each set of 'n' data bits with the 'n' sync bits and for providing an output signal in respect of each set indicative of the number of agreements therebetween, agreement signals are routed by a microprocessor 12 to a third data store 17 having a plurality of storage cells in which data apertaining to each set and indicative of the number of agreements in each set is stored and updated from hop to hop following each of 'm' hops. The microprocessor is responsive to data in the cells of the third data store 17 and to a signal on line 15 from the synch code generator 2 indicative of the expected position of the synch, code, for effecting resynchronisation of the code generator via a line 16 in accordance with the address of a cell accommodating stored data indicative of more than a predetermined number of agreements during the 'm' hops, so that received data can be decoded. <IMAGE>

Description

SPECIFICATION Intra-hop synchroniser This invention relates to frequency hopping radio systems.

Frequency hopping radio systems are known and afford advantages of improved security and improved resistance to jamming over continuous single carrier frequency communication systems.

One of the problems associated with frequency hopping is the problem of achieving synchronisation between a frequency hopping transmitter and a receiver with which it seeks to communicate.

The transmitter of a frequency hopping system may be arranged to change carrier frequency 100 times per second (100 hops per second) and to hop through a pseudo random sequence of frequencies. One system for achieving synchronisation between a transmitter and receiver so that the receiver changes frequency synchronously with and to the same frequency as the transmitter is described in our co-pending Patent application No. 8235324.

The system described in the Specification accompanying this Patent Application is concerned exclusively with a system which seeks to achieve hop synchronisation so that the receiver is always tuned to the frequency transmitted, but during each transmission period, which in the case of 100 hop per second system is 10 milliseconds, a plurality of message bits are transmitted having a 1 or a 0 significance and it is necessary also to achieve message bit synchronisation or intra-hop synchronisation between transmitter and receiver before data can intelligibly be received.

In order to facilitate intra-hop synchronisation, a group of sync bits comprising a sync code are transmitted during each message period but in order to make unauthorised reception difficult the character of the sync code is changed from hop to hop and moreover the position of the sync code within the message bit period may also be changed. In order to achieve intra-hop synchronisation, the receiver must of course 'know' what sync code to expect and it must 'know' also when, within the message period, the sync code is to be expected.

It is an object of the present invention to provide in a frequency hopping system a receiver adapted efficiently to achieve intra-hop synchronisation.

According to the present invention a radio receiver for receiving a frequency hopping transmission wherein a plurality of data bits including n sync bits are transmitted between hops, comprises a sync code generator which defines from hop to hop the expected character (i.e. O or 1) of each of the n sync code bits, a first data store responsive to the sync code generator for storing during each hop period the n sync code bits expected, a second data store through which the received data bits are passed sequentially, comparator means responsive to the first and second data stores for comparing consecutively each set of n data bits with the n sync code bits and for providing an output signal in respect of each set indicative of the number of agreements therebetween, a third data store having a plurality of storage cells in which data apertaining to each set and indicative of the number of agreements in each set is stored and updated from hop to hop following each of m hops, and a microprocessor responsive to data in the cells of the third data store for effecting resynchronisation of the code generator in accordance with the address of a cell accommodating stored data indicative of more than a predetermined number of agreements during the m hops, so that received data can be decoded.

Since the microprocessor 'knows' from the code generator the expected position within the data bits of the sync code bits, and the true position of the sync code bits as indicated in accordance with the address of the third store in which more than a predetermined number of agreements is stored, the code generator can be controlled so as to bring it into synchronisation with the received data so that received data can be decoded.

If the position within the data bits of the sync code bits is always the same, the radio receiver as thus far defined will operate satisfactorily, but if in accordance with a more complex embodiment of the invention, the position within the data bits of the sync bits is changed from hop to hop, then the microprocessor must be arranged to be responsive to data derived from the code generator indicative of the expected sync code position, for selecting the address of the third store from which data indicative of the number of agreements is advanced progressively into the store, in accordance with the said expected sync code position as indicated by the code generator, whereby the sync bit address within the store is constrained to be the same during the whole of the m hop period.

One embodiment of the invention will now be described by way of example with reference to the accompanying drawing which is a block schematic diagram of a part of the receiver of a frequency hopping communication system.

Referring now the drawing, a frequency hopping radio communication system comprises a radio receiver in which radio signals are received and detected in a conventional manner and the resulting received data applied to an input line 1.

Since the receiver forms part of a frequency hopping system wherein the carrier frequency is changed or hopped at say 100 times per second through a pseudo random sequence of frequencies, it is necessary to initially achieve synchronisation between the transmitter and the receiver. The manner in which hopping synchronisation between the transmitter and receiver is achieved so that the receiver changes frequency synchronously with and to the same frequency as the transmitter is described in the specification accompanying our co-pending Patent Application No. 8235324 to which attention is hereby directed.

Having once achieved hopping synchronisation so that the receiver is adapted to be synchronised with the transmitter intra-hop synchronisation must be achieved so that message bits transmitted after each frequency hop can be intelligibly received.

In the case of a frequency hopping system which changes frequency 100 times per second so that the transmission period for each frequency is 10 milliseconds, a 1 millisecond dead space is provided within each 10 millisecond period followed by the transmission of 1 64 data bits in the remaining 9 milliseconds. Four of the 164 data bits are sync bits which comprise a sync code and the remaining 1 60 data bits comprise message bits. The 4 bits comprising the sync code are transmitted consecutively and the character of each bit i.e. 1 or O is arranged to vary in a pseudo random manner from hop to hop. Also the position of the sync code in the data transmission may be varied.

The receiver includes a code generator 2, which, once hopping synchronisation has been achieved, 'knows' what the 4 sync bits should be and where they should occur in the message bits.

In order to achieve intra-hop synchronisation the expected sync code bits are transferred from the code generator via lines 3 to a sync code store 4.

Incoming data is fed to a data store 5 having storage positions 6, 7, 8 and 9 through which incoming data is passed. A comparator 10 is provided responsive to the sync code store 4 and the data store 5 for comparing the contents of the data store from bit to bit with the contents of the sync code store and for providing after each comparison a signal on a line 11 indicative in respect of each set of data bits, the number of agreements. Thus, if for example the data store were to be filled with the precise sync code, a maximum of 4 agreements would be registered and an appropriate signal would be applied to the line 11 and fed to a microprocessor 12.The microprocessor routes the agreement signals on line 11 via an output line 13 to a third store 17. in the present example the store 1 7 is arranged to have 256 addresses so that after each hop, data can be stored apertaining to the number of agreements in each set. In this example the agreements are totalled in the store 17 for 14 hops and after the 1 4th hop the address of the 3rd store 1 7 in which most agreements have been stored is taken as an indicative of the position in the data of the sync code.The microprocessor examines the contents of each location in turn of store 1 7 to obtain the location in which most agreements have occurred and compares this with a signal fed on a line 1 5 from the code generator 2 indicative of the expected position of the sync code. A signal is then applied via a line 1 6 to the code generator 2 to resynchronise it so that the code generator 2 is synchronised with the incoming data.

The system thus far described will operate perfectly satisfactorily provided the sync code always occurs at the same position within each messag.e If however in accordance with one embodiment of the invention the position in the message. If however in accordance with one microprocessor must control the address at which data is fed to the store 14 initially at the start of each hop in accordance with the sync code position as indicated by a signal fed to the microprocessor from the code generator 2 via the line 1 5. By changing the address to which data is initially fed to the store 14 it is arranged that the sync code always occurs in the same address within the store 14.When the code generator 2 has been synchronised with the incoming message, the microprocessor (in conjunction with a signal from the code generator 2) controls a buffer 18 whereby the sync codes can be removed from the signal which is then fed to an output line 19.

In the present example the sync code which is included in the data during each hop period comprises 4 synchronising bits. These bits are inserted into the message bits at a pseudo random position which is 64 bits wide and centres on the centre of the hop period. The bit position changes every hop period. The bits also change every hop period in a pseudo random manner. During hop synchronisation as described in our co-pending Patent Application No. 8235324 the receiver timing has been set to that of the transmitter to within about a quarter of a hop period and the receiver processor therefore knows the expected synchronisation bits and their positions. The receiver processor thus compares successive groups of 4 incoming bits with the expected synchronising bits and loads the number of agreements into the store 17.As hereinbefore explained, this process is repeated for 14 hop periods altogether which means that for each address of the store 1 7 56 bits are checked. After this the processor searches the store 1 7 for a location which has at least 43 bit agreements. If 43 bit agreements occur, the location at which they occur indicates how early or how late the receiver is with respect to the transmitter. The receiver timing is then adjusted accordingly by means of a signal applied to the code generator on the line 1 6. If 43 or more agreements do not occur however the system reverts to a waiting state.

Various modifications may be made to the arrangement hereinbefore described without departing from the scope of the invention and for example it will be appreciated that any convenient number of sync code bits may be utilized and that the number of addresses in the stores 4 and 5 would be altered accordingly. The manner in which the pseudo random code is selected by the code generator 2 is not central to the present invention and will not be described herein in any detail especially since various methods of obtaining pseudo random codes are well known.

Operation of the microprocessor 12 and the buffer 1 8 is also regarded as standard practice and not central to the present invention and it is believed therefore that a special description of these parts of the apparatus is also not required.

Claims (2)

1. A radio receiver for receiving a frequency hopping transmission wherein a plurality of data bits including 'n' sync bits are transmitted between hops comprising a sync code generator which defines from hop to hop the expected character (i.e. O or 1 ) of each of the 'n' sync bits, a first data store responsive to the sync code generator for storing during each hop period the 'n' sync bits expected, a second data store through which the received data bits are passed sequentially, comparator means responsive to the first and second data stores for comparing consecutively each set of 'n' data bits with the 'n' sync bits and for providing an output signal in respect of each set indicative of the number of agreements therebetween, a third data store having a plurality of storage cells in which data apertaining to each set and indicative of the number of agreements in each set is stored and updated from hop to hop following each of 'm' hops, and a microprocessor responsive to data in the cells of the third data store for effecting resynchronisation of the code generator in accordance with the address of a cell accommodating stored data indicative of more than a predetermined number of agreements during the 'm' hops, so that received data can be decoded.

2. A radio receiver substantially as hereinbefore described with reference to the accompanying drawing.