GB2132427A - An on-off arrangement in a digital controller - Google Patents
An on-off arrangement in a digital controller Download PDFInfo
- Publication number
- GB2132427A GB2132427A GB08334062A GB8334062A GB2132427A GB 2132427 A GB2132427 A GB 2132427A GB 08334062 A GB08334062 A GB 08334062A GB 8334062 A GB8334062 A GB 8334062A GB 2132427 A GB2132427 A GB 2132427A
- Authority
- GB
- United Kingdom
- Prior art keywords
- switch
- coupled
- latch
- transistor
- arrangement according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/282—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator astable
- H03K3/2826—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator astable using two active transistors of the complementary type
Abstract
In a battery operated, remote transmitter for a consumer instrument, such as a television or a video disc or tape player, a microprocessor 25 controls operation of the transmitter. The collector current path of an on-off transistor Q3 is (TR1, Fig. 2) coupled between the battery 23 and a voltage supply terminal Vcc of the microprocessor. To power up the microprocessor, a keyboard switch 21 in the transmitter is depressed in order to ground the base of the on-off transistor Q3 and turn on the transistor. To maintain the on-off transistor conductive, another transistor (TR2), (Fig. 2), forms a regenerative loop latch with the on-off transistor (TR1), or a pair of transistors (Q4, Q5 in a regenerative loop form a latch 27, responsive to the base current of the on-off transistor. After completion of the transmitter signaling, the microprocessor switches an output port D3, to the ground state. The output port is coupled to the regenerative loop and bypasses current therefrom to initiate the regenerative deactivation of the latch. With the latch deactivated, conduction of the on-off transistor (Q3) is cut off and the voltage supply terminal of the microprocessor is thereby disconnected from the battery to power down the transmitter. <IMAGE>
Description
' SPECIFICATION
An on-off arrangement in a microprocessor
controlled remote transmitter for a consumer
instrument
This invention relates to an on-off arrangement
for a digital controller, such as a microprocessor,
that, e.g., controls operation of a remote
transmitter in a consumer instrument.
The remote transmitter of a consumer
instrument, such as a color television receiver or a
video disc player, is battery operated and
controlled in operation by a microprocessor. To
conserve battery power, the remote transmitter is
powered up only during those intervals when a
command signal for the instrument remote
receiver circuitry is being generated by the
transmitter.
In a typical keyboard transmitter arrangement
an electrically conductive contact sheet is
connected to electrical ground. Each of the
keyboard switches is positioned over the contact
sheet and spaced apart from it. Signal lines from
input ports of the microprocessor are connected
to the keyboard switches.
When a keyboard switch corresponding to a
given function or command to be transmitted is
depressed, the switch makes electrical
connection to the grounded contact sheet thereby
grounding the signal line or lines connected to
that switch. The input port or ports of the
microprocessor that are connected to the signal
lines become grounded to provide an indication to
the microprocessor that the particular command
is to be transmitted.
To power up the microprocessor when any of
the keyboard switches are depressed, each of the
signal lines connected to the switches is also
connected to the control terminal of an on-off
transistor switch. The collector to emitter path of
the transistor is connected between the battery
that generates, illustratively, 6.3 volts of
operating voltage and the voltage supply terminal
of the microprocessor. When a signal line is
grounded to the contact sheet, the control
terminal of the on-off transistor switch is also
grounded, turning on the transistor and enabling
main power to be supplied from the battery to the
voltage supply terminal of the microprocessor.
After the command has been transmitted by
the remote transmitter, it is desirable to power
down the microprocessor and associated
transmitter circuitry to conserve battery power.
The microprocessor itself provides a power down
command signal by, for example, internally
grounding an output port. The operating
characteristics of the microprocessor, such as the
ability of an output port to sink current, may
become unpredictable when the voltage at the
supply terminal decays below a given value, such
as below 4.5 volts.
A feature of the invention is a latching arrangement that ensures reliable microprocessor turn-off, by reliably maintaining an on-off transistor in cutoff during the entire interval that the supply voltage is decaying to zero volts.
The off-command of the microprocessor is applied to a control terminal of the latch. The keyboard switch input signal lines are connected to another control terminal of the latch, and a main current terminal of the latch is coupled to the control terminal of the on-off transistor switch.
Grounding an input signal line activates the latch and also enables base current to flow to turn on the on-off transistor switch. An off-command signal from the microprocessor deactivates the latch, preventing base current from flowing in the on-off transistor switch to power down the microprocessor. With this on-off latch control arrangement, battery power is conserved because the battery is connected to the voltage supply terminal of the microprocessor only during the generation of a command signal. Also, reliable self-turnoff or self-powering down of the microprocessor is assured once the off-command signal is generated.
The accompanying Figs. 1 and 2 illustrate two examples of a remote control transmitter for a consumer instrument, including on-off circuitry embodying the invention.
In the battery operated, microprocessor controlled, remote transmitter 10, illustrated in each Figure each contact switch 21 of a keybaord assembly 20 is coupled to one or more of a plurality of signal lines SI connecting the contact switches to a plurality of input ports IN of a digital controller, microprocessor 25. By way of example, only four signal lines and input ports are illustrated in the Figures. In practice, between ten and twenty signal lines and input ports may be provided. Microprocessor 25 may be selected as
COP420L, manufactured by National
Semiconductor Corporation, Santa Clara,
California.
Keyboard assembly 20 includes an electrically conductive contact sheet 22 electrically connected to the ground terminal of the remote transmitter circuitry. Alternatively, contact sheet 22 may be constructed as a plastic, nonconductive sheet with electrically conductive conductor lines printed thereon and electrically connected to ground. Conctact sheet 22 is located below and spaced apart from each contact switch 21. Depressing a contact switch grounds the associated signal line or lines and therefore grounds the corresponding input port or ports.
To transmit a particular command signal, such as a "CHANNEL SCAN" command signal for sequentially selecting channels, when the remote transmitter is part of a remote controlled television receiver, or such us a "PLAY" or "PAUSE" command signal to play back, to stop and start, respectively, when the remote transmitter is part of a remote controlled video disc or tape player, the operator depresses the appropiate one of the contact switches 21 that represents the command signal to be transmitted.
The corresponding signal line or lines SI are grounded, thereby grounding the corresponding input port or ports IN.
Microprocessor 25 interrogates the switching states of the input ports IN. Upon determining that a particular combination of input ports are in the low or ground state, microprocessor 25 generates at an output port SK a serial flow of coded pulses corresponding to the command selected by the operator. These pulses are applied to the transmitting portion 26 of remote transmitter 1 0. When output pert SK is in the low state, the port is grounded through the conducting source-drain path of an MOS transistor of the output interface circuitry associated with the port and not otherwise illustrated. Accordingly, transistors Q1 and Q2 are cut off, preventing current from flowing in light emitting diodes CR.When output port SK is in the high state, transistor Q1 turns on, turning on transistor Q2 to enable current to flow in light emitting diodes CR. In this manner, coded signal pulses at terminal SK, representing a given command, are converted by the light emitting diode transducers into coded light pulses for reception by the remote receiver.
Main power for remote transmitter 10 is obtained from a battery 23 (Fig. 1) 58 (Fig. 2).
The power is supplied through the main current conduction, collector-to-emitter path of an on-off,
PNP, switching transistor Q3 (Fig. 1) or Trl (Fig.
2), the collector of which is coupled to the base of transistor Ol to control the energization of transmitting portion 26, and is also coupled to the
Vcc voltage supply terminal that provides power to microprocessor 25.
In the powered down state of remote transmitter 10, transistor Q3 or TR 1 is nonconductive, disconnecting the battery from the microprocessor 25 and from the control terminal of transmitting portion 26. No significant power is drained from battery in the powered down state.
Remote transmitter 10 is powered up when a keyboard contact switch 21 is depressed. In Fig.
1, signal lines S1 are coupled through respective resistors RI to a signal line 28 to a control terminal of an on-off control latch 27. Depressing any contact switch 21 generates an on-command signal 24 along signal line 28 during the time that the contact switch is depressed. Base currents begin to flow in a PNP transistor Q4 of latch 27 and in on-off transistor 03. The base current from transistor Q3 flows in the collector-to-emitter path of transistor Q4 and then into the base of an
NPN transistor OS of latch 27, which transistor has its collector connected to the base of transistor Q4 to regeneratively turn on or activate the latch. The base current from transistor Q3 functions as the sustaining or holding current of latch 27.
With latch 27 maintaining transistor Q3 forward biased into conduction, the battery voltage V5 is applied to the Vcc terminal to power up microprocessor 25. The Vcc terminal is coupled to a capacitor 29 and to a RESET-BAR input port
R of microprocessor 25. After microprocessor 25 is powered up, the programming of the microprocessor is such that an output port D3 is switched to the high state by the open-drain interface circuitry OF. Output port D3 is coupled to a control terminal of latch 27 at the base of transistor 05.
Upon completion of the command signal transmission, microprocessor 25 switches the output state of port D3 to the low state by means of the conduction of the enhancement-mode
MOS transistor in the output interface circuitry
OF, thereby grounding output port D3. With output port D3 grounded, the main portion of the latch sustaining current that flows in the collector-to-emitter path of transistor Q4 is diverted from the base of transistor Q5 through port D3 and the MOS transistor of interface circuitry OF.
The creation of this alternate current path for the latch holding current that bypasses the base of transistor Os initates the regenerative deactivation of the latch, turning off transistors
Q4 and 05. The path to ground for base current in transistor Q3 is disabled by the deactivation of latch 27 to cut off conduction of on-off switching transistor 03. Battery 23 is disconnected from the
Vcc voltage supply terminal of microprocessor 25.
Capacitor 29 discharges into the Vcc terminal, and the R input port. Microprocessor 25 powers down as the voltage at the Vcc terminal decays.
In the arrangement just described, the magnitude of the latch holding current is merely that of the relatively small magnitude base current of transistor 03. Output port D3 of microprocessor 25 therefore must sink only a relatively small magnitude current in order to initiate the sequence of events that disconnects battery 23 from the Vcc voltage supply terminal.
Once latch 27 is deactivated and Q3 becomes non-conductive, the relatively slow decay of the supply voltage at the Vcc terminal has no adverse effects on reliably maintaining battery 23 disconnected from the Vcc supply terminal during the decay interval. Although the characteristics of output port D3, such as the capability of sinking current to ground, cannot be assured when the voltage at terminal Vcc decreases below a certain minimum value, any change of state in output port D3 as the voltage at supply terminal Vcc decays, such as a change of state of the MOS interface transistor from the conductive state to the open-drain state, cannot erroneously turn transistor Q3 back on. This result follows because latch 27 has already been regeneratively turned off.
Fig. 2 shows an alternative arrangement in which the latch transistors Q4 and Q5 are replaced by a single transistor TR2 and the switching transistorTR1 forms partly the regenerative feedback loop 60 in the latch configuration 27 formed this time by transistors
TR1 and TR2 jointly. The collector output electrode of on-off switching transistor Tr1 is coupled through a resistor R2 to the base control electrode of transistor Tr2. The collector output electrode of transistor Tr2 is coupled through resistor R1 to the base control electrode of transistor Tr1 thereby forming the regenerative latching loop 60. The emitter of transistor Tr2 is coupled to a tap terminal 59 of battery pack 58 for purposes hereinafter to be described.
Upon initial power-up of microprocessor 25, the initialization hardware logic of the microprocessor, such as the initialization logic found in the aformentioned COP420L, switches output port D3 to the ground state. The programming of the microprocessor is such that immediately after initialization, output port D3 is switched to the open drain MOS, logical high, switching state. Latch 27 becomes activated by the collector current from the transistor Tr1 flowing to the base of transistor Tr2 through resistor R2. Thus resistor Trl remains conductive after on-command signal 24 has been completed and signal lines S1 are no longer grounded. The tap voltage Vt, nominally 3.0 volts, at battery terminal 59, is sufficiently lower than the voltage at the collector of transistor Tr1 to enable transistor Tr2 to be maintained in a forward biased condition.
Upon completion of the command signal transmission, when the microprocessor switches the output state of port D3 to the low, ground, state by means of the conduction of the enhancement mode MOS transistor in output interface circuitry OF, latch current from the collector of transistor Tr1 is diverted from the base of transistor Tr2 to ground through port D3.
Transistor Tr2 begins to turn off, turning off transistorTrl in a regenerative manner. Thus when port D3 is switched to ground, loop 60 becomes deactivated and the supply rail V5 is disconnected, by the non-conduction of transistor
Tri, from the Ccc supply terminal of microprocessor 25.
The voltage at the Vcc terminal begins to decay as capacitor 29 discharges into that terminal and the R input port. After the voltage at the Vcc terminal has decayed from its onstate value of around 6.3 volts to a value near the tap voltage Vt of 3.0 volts, deactivation of loop 60 is assured for the entire interval that the voltage at the Vcc terminal decays to zero volts. This result follows because after the voltage at the Vcc terminal decays to near the threshold voltage Vt, transistor
Tr2 cannot become forward biased even after port
D3 has lost its capability of sinking current.Thus, when the voltage at the Vcc terminal has decayed below the minimum voltage that enables microprocessor 25 to reliably maintain the MOS transistor of interface circuitry OF conductive, latch 27 cannot be erroneously reactivated by the residual voltage at the Vcc terminal: that residual voltage is not great enough relative to the voltage at battery tap terminal 59 to turn tra nsistor Tr2 back on.
The arrangement in Fig. 2, of an on-off switching transistor configured with a second transistor in a latching arrangement provides for turn-on of the microprocessor by activation of the on-off switching transistor, the maintaining of the on-off transistor in the conductive mode by continuous latch energization, and the self turnoff of the microprocessor when the microprocesor deactivates the latch.
An additional feature of the arrangement of
Fig. 2 is the biasing of the emitter of transistor Tr2 at an intermediate voltage between zero volts and the battery voltage V5. An advantage of such an arrangement is that latch cannot erroneously turn itself back on when the supply voltage decreases below the minimum necessary to maintain the
MOS transistor of interface circuitry OF fully conductive.
Had the emitter of transistor Tr2 been connected to ground rather than to battery pack tap terminal 59, then, when the voltage at the Vcc supply terminal decayed to some low value, port
D3 would be unable to sink current. The residual voltage at the Vcc terminal could make transistor
Tr2 conductive. TransistorTrl could become conductive to begin bringing the voltage at the
Vcc terminal back up to the battery voltage V5. The initialization hardware with in the microprocessor could then be activated to bring port D3 to ground to again deactivate the latch. Thus an undesirable partial off-mode ooperation could result that draws some current. By coupling a source of bias voltage Vt to the emitter of transistor Tr2, such quasistable mode of operation is avoided. The application of the bias voltage Vt to the emitter of transistor Tr2 also reduces the off-state leakage current in the collector and base circuits of transistor Tr2.
Claims (20)
1. An on-off arrangement for a digital controller, comprising:
a voltage supply terminal of said digital
controller for providing main power thereto;
a source of supply voltage,
a first switch having a main current path
coupled between said voltage supply
terminal and said source of supply voltage,
conduction in said main current path being
controlled by a control terminal of said
switch;
means for forming a regenerative latch and
coupled to said first switch control terminal
to maintain said main current path
conductive once said latch is activated;
means for applying a turn-on signal to said first
switch control terminal to initiate the
conduction of current in said main current
path to power-up said digital controller, said
latch being activated upon application of
said turn-on signal; and
an output port of said digital controller coupled
to said latch for providing an alternate path
for current that bypasses at least a portion
of said latch to initiate the regenerative
deactivation thereof for cutting off
conduction in said main current path to
power-down said digital controller.
2. An arrangement according to claim 1
wherein said latch forming means comprises a
second switch having a main current path
coupled to the first switch control terminal, and a
control terminal to control the conduction of said
second switch.
3. An arrangement according to Claim 2 wherein said output port is coupled to the control terminal of said second switch and interface
circuitry of said digital controller is coupled to said output port for bypassing current from said
control terminal of said second switch to deactivate said latch.
4. An arrangement according to Claim 3 wherein said interface circuitry includes an open drain configured MOS transistor coupled to said
output port and a point of reference potential.
5. An arrangement according to Claim 2, 3 or 4 wherein said first switch comprises a PNP transistor and said second switch comprises an
NPN transistor, the emitter of said PNP transistor
being coupled to said source of supply voltage, the collector of said PNP transistor being coupled to said voltage supply terminal and to the base of said NPN transistor, the base of said NPN transistor being coupled to said output port, the collector of said NPN transistor being coupled to the base of said PNP transistor, the emitter of said
NPN transistor being coupled to said source of bias voltage.
6. An arrangement according to Claim 6 wherein the control terminal of said first switch comprises the base of said PNP transistor and wherein said activating means comprises a turnon switch that couples the base of said PNP transistor to a point of reference potential.
7. An arrangement according to claim 1 wherein the first switch has a control current path controlling conduction in its main current path, said regenerative latch is exlusive of said first switch and coupled to receive said control current for initiating conduction in the main current path of said switch, and said turn-on signal applying means comprises means for activating said latch to receive said control current for initiating conduction in said main current path.
8. An arrangement according to claim 7 wherein said activating means comprises a turnon switch coupled between a source of reference potential and said latching arrangement, said turn-on switch, when made conductive, applying said reference potential to said latching arrangement to activate it.
9. An arrangement according to claim 7 or 8 wherein said output port is coupled to interface circuitry that provides said alternate path when said digital controller switches the state of said output port.
10. An arrangement according to claim 7, 8 or 9 wherein said latch comprises two switches each having an output coupled to a control terminal of the other to provide regenerative switching of these switches, the control terminal of one of these switches being coupled to said output port of the controller.
11. An arrangement according to claim 10 wherein said digital controller includes interface circuitry that has an MOS transistor arranged in an open drain configuration and coupled between said output port and a point of reference potential for bypassing current from the control terminal of said one latch switch.
12. An arrangement according to claim 11 wherein said latch activating means is coupled to the control terminal of the other latch switch for applying a turn-on signal thereto to activate said latch.
13. An arrangement according to claim 12 wherein said first switch comprises a first PNP transistor and wherein said latch switches comprise an NPN transistor and a second PNP transistor, respectively, the base of said first PNP switch being coupled to the emitter of said second PNP switch.
14. An arrangement according to any preceding claim wherein said turn-on signal applying means comprises, as a turn-on switch, a keyboard contact switch coupled between a source of reference potential and said latch.
1 5. An arrangement according to claim 14 wherein said source of reference potential comprises electrical ground and said keyboard contact switch represents a given command operation, and wherein said keyboard contact switch is coupled to an input of said digital controller in order to ground said input port when said contact switch is activated and thereby to enable said digital controller to identify said given command operation.
1 6. An arrangement according to claim 1 5 including a signal port of said digital controller for developing thereat a coded output signal representative of said given command operation when said contact switch makes contact.
1 7. An arrangement according to claim 1 6 wherein said digital controller switches the state of said output port to bring the output port to ground after completion of the generation of said coded output signal.
1 8. An arrangement according to claim 17 including a signal transducer responsive to said coded output signal for transmitting to a receiving unit a signal representative of said command operation.
19. An arrangement according to any preceding claim wherein said output port of the controller is coupled to the interface circuitry thereof that sinks latch current to deactivate said latching arrangement when said digital controller changes the state of said output port.
20. An on-off arrangement for a digital controller, substantially as hereinbefore described with reference to Figure 1 or Figure 2 of the accompanying drawings.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/452,114 US4544923A (en) | 1982-12-22 | 1982-12-22 | Microprocessor self-turn-off arrangement for a consumer instrument |
| US06/452,115 US4544924A (en) | 1982-12-22 | 1982-12-22 | On-off arrangement in a microprocessor controlled remote transmitter for a consumer instrument |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8334062D0 GB8334062D0 (en) | 1984-02-01 |
| GB2132427A true GB2132427A (en) | 1984-07-04 |
| GB2132427B GB2132427B (en) | 1986-06-04 |
Family
ID=27036651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08334062A Expired GB2132427B (en) | 1982-12-22 | 1983-12-21 | An on-off arrangement in a digital controller |
Country Status (7)
| Country | Link |
|---|---|
| KR (1) | KR920009208B1 (en) |
| AU (1) | AU575793B2 (en) |
| DE (1) | DE3346509C3 (en) |
| ES (1) | ES8500528A1 (en) |
| FR (1) | FR2538574B1 (en) |
| GB (1) | GB2132427B (en) |
| IT (1) | IT1212803B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2210217A (en) * | 1987-09-23 | 1989-06-01 | David Alexander Rippon Wallace | Computer software controlled power supply switch |
| GB2306237A (en) * | 1995-10-10 | 1997-04-30 | Standard Microsyst Smc | Controlling the power supply to processor-related devices |
| EP2849343A1 (en) * | 2013-09-16 | 2015-03-18 | Hep Tech Co. Ltd. | Switch |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NZ214078A (en) * | 1984-11-10 | 1988-08-30 | Int Computers Ltd | Keyboard subset powered by standby source during mains failure |
| DE4406395C1 (en) * | 1994-02-26 | 1995-03-02 | Professional Computing Gmbh | Signal processing method for the multiplication of input signals by parameters and for subsequent accumulation |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53120158A (en) * | 1977-03-29 | 1978-10-20 | Sharp Corp | Power source control system |
| US4279020A (en) * | 1978-08-18 | 1981-07-14 | Bell Telephone Laboratories, Incorporated | Power supply circuit for a data processor |
| FR2443718A1 (en) * | 1978-12-06 | 1980-07-04 | Sit Intel | Automatic switching of non volatile memory data receiver - by using bistable circuit controlling electronic switch for updating timing data |
| DE2911998C2 (en) * | 1979-03-27 | 1985-11-07 | Robert Bosch Gmbh, 7000 Stuttgart | Power supply for a microprocessor that controls electrical devices, in particular a motor vehicle |
| JPS58205395A (en) * | 1982-05-25 | 1983-11-30 | Sony Corp | Remote control device |
| US4544924A (en) * | 1982-12-22 | 1985-10-01 | Rca Corporation | On-off arrangement in a microprocessor controlled remote transmitter for a consumer instrument |
-
1983
- 1983-12-16 ES ES528100A patent/ES8500528A1/en not_active Expired
- 1983-12-16 AU AU22489/83A patent/AU575793B2/en not_active Ceased
- 1983-12-19 KR KR1019830006004A patent/KR920009208B1/en not_active IP Right Cessation
- 1983-12-21 GB GB08334062A patent/GB2132427B/en not_active Expired
- 1983-12-21 IT IT8324309A patent/IT1212803B/en active
- 1983-12-22 DE DE3346509A patent/DE3346509C3/en not_active Expired - Fee Related
- 1983-12-22 FR FR8320603A patent/FR2538574B1/en not_active Expired
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2210217A (en) * | 1987-09-23 | 1989-06-01 | David Alexander Rippon Wallace | Computer software controlled power supply switch |
| GB2306237A (en) * | 1995-10-10 | 1997-04-30 | Standard Microsyst Smc | Controlling the power supply to processor-related devices |
| GB2306237B (en) * | 1995-10-10 | 1997-11-12 | Standard Microsyst Smc | Apparatus for reducing power consumption in a processor-based system |
| US5708819A (en) * | 1995-10-10 | 1998-01-13 | Standard Microsystems Corporation | Process and apparatus for generating power management events in a computer system |
| EP2849343A1 (en) * | 2013-09-16 | 2015-03-18 | Hep Tech Co. Ltd. | Switch |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3346509A1 (en) | 1984-06-28 |
| FR2538574A1 (en) | 1984-06-29 |
| KR920009208B1 (en) | 1992-10-14 |
| AU2248983A (en) | 1984-06-28 |
| ES528100A0 (en) | 1984-10-01 |
| DE3346509C3 (en) | 1994-07-28 |
| KR840007328A (en) | 1984-12-06 |
| FR2538574B1 (en) | 1988-08-26 |
| GB8334062D0 (en) | 1984-02-01 |
| DE3346509C2 (en) | 1994-07-28 |
| IT1212803B (en) | 1989-11-30 |
| IT8324309A0 (en) | 1983-12-21 |
| GB2132427B (en) | 1986-06-04 |
| AU575793B2 (en) | 1988-08-11 |
| ES8500528A1 (en) | 1984-10-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19971221 |