GB2129545A - Parallel digital signal processing - Google Patents

Abstract

Processing of information obtained at a high rate is carried out in parallel to enable presentation of such information substantially in real time. Digital electronic circuit means is adapted to receive and process information from a linear array of photo diodes scanning a succession of objects and producing a raster of given width but of indefinitely extended length. The information is fed to the processor serially by a multiplexer 32 and likewise is output serially by a demultiplexer 62. Processing of information derived from any given scan, or by comparison of scans stored in a memory, is carried out in a parallel manner by interconnected circuits 40/1 to 40/n in order to provide speed of operation. Principal uses are in the inspection of objects carried past a said array of diodes; and in processing satellite photographs, and images resulting from medical X-ray and ultrasound scans. <IMAGE>

Description

SPECIFICATION Improvements in or relating to processors This invention relates to processors, in particularto linear array processors Industrial processes may involve the machine observation of articles for inspection purposes, and articles maybe moved on a conveyor belt past an inspection head for this purpose. An array of photo sensitive elements, most commonly a linear array of photo diodes, can be used for observing articles in the manner mentioned. Arrays are commercially available which provide a resolution of several thousand picture units (or pixels). For observing (scanning) articles passing on a conveyor belt a linear array of photo diodes is arranged at right angles to the direction of movement of the articles, and the articles are imaged by an optical system onto the array.The signal output from the array can provide a raster which corresponds in width to the array but is of indefinite length, ie in the direction of motion of articles with the conveyor belt. Automatic inspection usually involves a number of processing operations to be performed on the information derived from the array, which may be regarded as defining a moving picture of the passing articles. For rapid correction of any defects in articles discovered by inspection it is necessary that the inspection results be made available in real time. In general, micro-processors alone are too slow to provide real time operation. Purpose-built hardware has been produced, which is capable of rapid enough action, but has been electrically hardwired, with the consequence that it has been inflexible; any modifications to hardwiring have been expensive, since they involve the use of skilled operatives.Two dimensional array processors have been developed, but have been bulky and expensive, and also have been of limited capacity for operating on pixels. Moreover, being two dimensional, they are not ideally suited to dealing with a raster of indefinite length, which is associated with inspection of continuously moving articles.

Relevant art is contained, for example, in the following publications: Parkinson, D. "An intoduction to array processors;" Systems International November 1977 Duff, M J B "Special computer architectures for pattern processing " C R C Press Inc 1982 0-8493 6100-1 The present invention provides a processor which permits inspection of moving articles in real time, employing items of hardware which individually are readily obtainable, and programmable so that it can be adapted rapidly and at relatively little cost to changes in requirement.

According to the invention a processor arranged to process a series of input signals, each from one of a anumber of predetermined sources, has processing circuits arranged in layers or cells, corresponding to said sources, which can simultaneously process input signals derived from scanning each of the said sources; and programming means arranged to program said processing means to produce parallel output signals in real time, said output signals combining in predeterminable manner information from signals from different preselected ones of said sources.

In one embodiment the processor is arranged to accept serially the signals from sources which are elements of a linear array of photo sensitive elements.

Desirably the signals from the photo sensitive elements are accepted serially through a multiplexer and fed serially to said processing circuits.

Preferably the serially sampled signals are fed into a shift register means comprising a number of input/output (I/O) registers, each in one of said layers or cells, until the whole of the linear array has been scanned; when the respective contents of all said I/O registers are trasferred simultaneously to working registers each in the same layer with the correspond- ing I/O register; whereby said working registers operate on the sampled signals in parallel.

The processor may be arranged so that processed items of information already contained in the said working registers are exchanged individually with the contents of the corresponding I/O registers and are then discharged serially from the shift register means as processed signals relating to an earlier scan of the said linear array.

The processed signals may advantageously be discharged through a demultiplexer.

It may be noted that the circuits associated primarily with one particular source of input signal, eg element of a linear array of photo diodes, are conveniently referred to as a layer; or cell; so that there is one layer for each element, all the layers being substantially, or completely, identical.

The invention will be further described, by way of example only, with reference to the accompanying drawing, in which Figure 1 is a diagrammatic view of an arrangement, including a linear array processor, for the inspection of articles being transported on a conveyor, Figure 2 is a block circuit diagram of a linear array processor.

Referring to Figure 1, 10 indicates the processor generally; in this embodiment a linear array processor. Reference 12 indicates diagrammatically articles being transported on a conveyor belt 14. The articles are transported past optical means 16 which focuses an image on a linear array of photo diodes 18, illumination of the articles being provided by a lamp 20. Signals from the array are transmitted through leads 22 to the processor 10, which gives a processed output through leads 24 to utilisation means 26.

The utilisation means may include display means and control means which may affect the production of articles 12 and/or the segregation of defective articles. Reference 28 indicates input of information to the processor from a host computer (not illustrated) and leads 30 provide control from the host computer.

Referring to Figure 2, analogue signals from the photo diode array 18 reach an analogue to digital converter 32. Digitised signals then pass to a multiplexer 34, by which they are transmitted in series through leads 36 to a first layer of circuits 38/1, 38/2 up to 38/n, where is the number of elements in the linear array. 18 of photo diodes. Each layer has a fast single bit Boolean logic device associated with which, and indicated in the same box 40/1 are (in this embodiment of the invention) sixteen single bit working registers. In each layer there is a random access memorey (RAM) indicated by 42/1, in this embodiment a 256 bit memory, and an input/output (I/O) register 44/1. All the layers are interconnected, as indicated at 46/1 for the transfer of information from one layer to either adjacent one.This facility is in addition to that for transfer of information within a layer. Typically a processor comprises 512 such layers (ie n = 512), for a photo diode array having that number of diodes.

All the circuit layers are operable in parallel under the control of a master control unit 48 through a common control bus 50. The control unit 48 is micro-programmed (ie programmed at the lowest level) to execute instructions held in a program memory 52. In the present embodiment the program memory is a RAM arranged to be down-loaded from a host computer (not illustrated), to provide flexibility of programming. An alternative to the RAM is a PROM (programmable read only memory) which has an advantage of independence from a host computer. A further featu re of the processor in a program counter 54 which coordinates the operation of the controller 48 in relation to the program memory 52.

The circuits in the circuit layers 38 are controlled bythe controller 48 to exchange and process information through the inter-connections 46 according to the program held in memory 52, and such processing proceeds in parallel and therefore relatively rapidly. At any one time the information being processed in the layers 38 relates to an individual scan of the linear array. By storing several previous line scans in the RAM a given window from the original input picture may be maintained. In this way the appearance of an article 12 at one point may be compared with that at a neighbouring point for example to detect edges of an object, in accordance with the program in use.The degree of detail in which an article maybe inspected can be controlled, if required, by the magnification provided by optical system 16; although, of course, this may mean restricting inspection to one part only of an article.

However, information signals from the linear array 18 are transmitted to the circuits 38 serially. The signals arrive from the multiplexer 34 at the first layer 110 register 44g1. In this part of a cycle of operation (relating to a single scan of array 18) the i 110 registers of all the layers are arranged as a long shift register, being connected together through interconnections indicated by 56/1 to 56/n-1.Thus the signal from the first diode to be scanned in array 18 passes through the shift register to I/O register 44#n, and so on, until the signal from the last diode to be scanned is held in l;O register 44it. When the 1,0 registers, arranged as a long shift register, are filled, their contents are transferred to the working regis ters in 40 1 and so on, through connections indicated by 581 to 58, n. At the same time, any processed information already contained in the working registers is exchanged individually with the contents of the corresponding I/O registers, as implied by the opposite pointing arrows on connection 58.That is to say, at a particular instant new information is in registers 44 and processed information is in registers 40. At a subsequent instant, say one clock period later, the new information is in the registers 40, ready for processing, and the already processed information is in the registers 44. The exchange takes place simultaneously in all layers, hence the operation is a parallel operation. A predetermined number of clock periods later, a further scan of the linear array 18 commences. The further items of new information are fed into 110 register 44/1 and at the same time the already processed information is progressively removed, item by item down the shift register, and output through leads 60 to a demuliplexer 62. From there the processed information is passed through leads 24 to utilisation means 26, as already mentioned.The output from the processor is a processed version of the input information delayed by a given number of lines.

The Boolean processor in section 40 of each circuit layer is conveniently one commercially available under the code AM2901 (Advanced Micro Devices Inc.). AM2901 is a four bit wide mocroprocessor slice containing an arithmetic unit and a logic unit and sixteen general purpose registers (the working registers) each capable of holding a four bit binary number. The AM 2901 is primarily intended to be cascaded to provide longer word lengths eg for mini computers. However, in this invention it is not used in its conventional configuration. Instead of arranging each chip as a four bit wide processor, to deal with four bit binary numbers, each chip is used as fou-r single bit processors.There will thus be sixteen single bit registers associated with each of these processors, which registers may be used as accumulators to store (for example) two eight-bit binary numbers. Arithmetic operations on these numbers are performed bit-serially; that is, to add two eight bit numbers, first the two least significant bits of the two are added to yield a sum and carry. Then the two bits of next higher significance are added and so on until all eight bits have been added. In fact 36 single bit operations are needed to add two eight bit numbers, but as the AM2901 can operate at 10 MHz the total time for an eight bit addition is only 3.6 micro-second, which compares favourably with commonly used eight bit microprocessors. The advantage of operating bit-serially in this way, with the AM2901 is that a high packing density of components is obtained, with four processing elements to each integrated circuit package. Interconnections are kept to a minimum since all data pathways are only a single bit wide.

The invention has been described in relation to a linear array processor, primarily for inspection of moving articles. However, there are other uses to which the invention may be put. The invention is intended for processing information derived from a raster scan. It is capable of implementing a sequence of one or more 3 x 3 window functions and can implement some larger functions. A 3 x 3 window function provides, in effect, for a given pixel to be compared with any one, or all, of its immediately neighbouring pixels. Typical industrial applications may include location, identification, measurement and counting of discrete objects, and examination for defects; the examination of continuous materials eg in sheet form, for texture analysis, assessment of faults, blemishes or the like.Use is also possible in the processing of satellite pictures, electron micrographs, and medical ultrasonic and X-ray pictures.

CLAIMS (Filed on 28th October 1983) 1. A processor arranged to process a series of input signals, each from one of a number of predetermined sources, having processing circuits arranged in layers, or cells, corresponding to said sources, which can simultaneously process input signals derived from scanning each of the said sources; and programming means arranged to program said processing circuits to produce parallel output signals in real time, said output signals combining, in predeterminable manner, information from signals from different preselected ones of said sources.

2. A processor according to Claim 1 arranged to accept serially the signals from sources which are elements of a linear array of photo sensitive elements.

3. A processor according to Claim 1 or Claim 2 in which the signals from the photo sensitive elements are accepted serially through a multiplexer and fed serially to said processing circuits.

4. A processor according to any one of the preceding claims in which serially sampled signals are fed into a shift register means comprising a number of input/output registers, each in one of said layers or cells, until the whole of the linear array has been scanned; when the respective contents of all said input/output registers are transferred simultaneously to working registers each in the same layer with the corresponding input/output register; whereby said working registers operate on the sampled signals in parallel.

5. A processor according to any one of the preceding claims arranged so that processed items of information already contained in the said working registers are exchanged individually with the contents of the corresponding input/output registers and are then discharged serially from the shift register means as processed signals relating to an earlier scan of the said linear array.

6. A processor according to any one of the preceding claims in which processed signals are discharged through a demultiplexer.

7. A processor substantially as hereinbefore described with reference to any one of the accompany- ing drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (7)

**WARNING** start of CLMS field may overlap end of DESC **. function provides, in effect, for a given pixel to be compared with any one, or all, of its immediately neighbouring pixels. Typical industrial applications may include location, identification, measurement and counting of discrete objects, and examination for defects; the examination of continuous materials eg in sheet form, for texture analysis, assessment of faults, blemishes or the like. Use is also possible in the processing of satellite pictures, electron micrographs, and medical ultrasonic and X-ray pictures. CLAIMS (Filed on 28th October 1983)

1. A processor arranged to process a series of input signals, each from one of a number of predetermined sources, having processing circuits arranged in layers, or cells, corresponding to said sources, which can simultaneously process input signals derived from scanning each of the said sources; and programming means arranged to program said processing circuits to produce parallel output signals in real time, said output signals combining, in predeterminable manner, information from signals from different preselected ones of said sources.

2. A processor according to Claim 1 arranged to accept serially the signals from sources which are elements of a linear array of photo sensitive elements.

3. A processor according to Claim 1 or Claim 2 in which the signals from the photo sensitive elements are accepted serially through a multiplexer and fed serially to said processing circuits.

4. A processor according to any one of the preceding claims in which serially sampled signals are fed into a shift register means comprising a number of input/output registers, each in one of said layers or cells, until the whole of the linear array has been scanned; when the respective contents of all said input/output registers are transferred simultaneously to working registers each in the same layer with the corresponding input/output register; whereby said working registers operate on the sampled signals in parallel.

5. A processor according to any one of the preceding claims arranged so that processed items of information already contained in the said working registers are exchanged individually with the contents of the corresponding input/output registers and are then discharged serially from the shift register means as processed signals relating to an earlier scan of the said linear array.

6. A processor according to any one of the preceding claims in which processed signals are discharged through a demultiplexer.

7. A processor substantially as hereinbefore described with reference to any one of the accompany- ing drawings.