GB2127599A - Decoding digital data - Google Patents

Abstract

Distanced codes are highly- redundant codes where the coded states all differ from each other in several different bits. Six input states can be coded by 16 bits such that each code differs from all the others in at least nine bits. At a receiver, any receive code differing from one of the correct codes in less than five positions can thus be assumed to be that code. A read-only memory (ROM) with a 16 bit address input could be used, were such practically available. Instead, some, e.g. thirteen, of the 16 input bits are applied to a first ROM A. Of the total 8192 combinations of these bits all those having five or more disagreements with all the correct codes can be identified by a single 'uncertain' state. The ROM A has then only 62 relevant output states, which can be encoded by six intermediate bits. These are applied to a second 9- input ROM B with the three remaining input bits. ROM B provides six outputs for the six individual correct codes, and a further output for the 'uncertain' condition. Other embodiments use 3 ROMs. <IMAGE>

Description

SPECIFICATION Decoding digital data This invention relates to the decoding of socalled 'distanced" digital data codes.

A distanced code is a highly-redundant code which is used in digital data transmission where the data requires particularly good protection against corruption by errors. The term transmission is here used in a broad sense to include recording and signal processing generally as well as transmission or broadcasting over large distances. One example of a distanced code is given by the following: A 0000 0000 0000 0000 B 0000 0001 1111 1111 C 0011 1110 0000 1111 D 0101 1110 1111 0000 E 1110 0111 0011 0011 F 1110 1011 1100 1100 Here six different data states, which require only three bits in a perfect transmission system, are transmitted by 1 6-bit codes. A bit-by-bit comparison of any pair of these codes shows that they differ in at least 9 of the 16 bits.In particular, a pair of codes within either of the two groups AEF and BCD differ in 10 places, while a pair with one is each group differ by 9 places.

Thus, if one of these codes is corrupted by one, two, three or four errors, each changing a O to 1 or vice versa, the received code still differs from any of the other codes in five or more places, so it.

can be correctly identified.

For a further discussion of digital codes in general, including this type of code, reference may be made to a review article "Binary codes for error protection" by Prof. D. A. Bell in Wireless World, May 1980 pages 71 to 74, and to the standard textbook "Error Correcting Codes" by W.

W. Peterson and E. J. Weldon published by M.I.T.

Press.

A decoder for distanced codes such as that described above takes the received codes and produces an output signifying the most probable transmitted code, that is assuming the least number of errors. It may also signal when there is no likely transmitted code, and possibly the degree of uncertainty attached to the most probable transmitted code. The choice of output depends on the particular application for which the system is being used, but the output can always be defined as a function of the input.

Specifically in the above example, all 65535 (or 216) possible received 1 6-bit codes can in principle be listed and the corresponding ouptut code tabulated against them.

A decoder for such a system operating in parallel format could in principle take the form of a Read-Only Memory (ROM) which converts the received bits to the appropriate output bits. This is diagrammatically shown in Figure 1 of the drawings. Here the 1 6-bit input would be used to address one of 65536 three-bit locations, and to apply the three stored bits as output bits. These identify eight possible states, six of which represent the codes A to F and the other two of which represent two levels of confusion.

Alternatively, seven individual output lines might be provided given individual output lines for the six codes and one 'uncertain' state.

In practice, however, the arrangement shown in Figure 1 is not currently practicable. It can be achieved with codes of length of eight bits, where an eight-bit address accesses 256 locations in the ROM. ROMs with 1 6 bit address inputs would be 256 times larger, while the largest convenient ROM at present available has a 1 3-bit address.

Another possibility would be to compare the 1 6-bit received code in a bit-by-bit comparison with each of the six correct codes A to F and count in each case the number of disagreements.

Where 12 or more digits are the same it can be assumed that the correct code has been found.

This approach would require six 1 6-bit adder circuits, together with the necessary decision logic. The number of operations required to be performed by such circuitry makes it slow or at least relatively complex to implement.

The present invention, which is defined in the appended claims, enables the provision of a practicable and efficient implementation of the decoder using available read-only memory devices.

The invention will be described by way of example with reference to the drawing, in which: Figure 1 (described above) is a theoretical diagram of a decoder for distanced codes using a ROM with a 1 6-bit input address; Figure 2 is a diagram of a decoder for distanced codes embodying the invention and using currentlk-available technology; and Figures 3 and4 are block diagrams of further decoders embodying the invention.

Figure 2 illustrates a preferred embodiment of the invention designed for decoding the 1 6-bit distanced codes representing 6 input states which we have described above. The decoder illustrated in this figure employs two read-only memories. The first, ROM A, is designed for a 13bit input address, and thirteen of the sixteen bits of the received codes are applied to this ROM.

This ROM A provides six outputs.

If all possible 13-bit combinations are compared empirically against 13 bits of each of the six codes, say the right-hand 1 3 bits are given above, a large-number of the 8192 theoretical possibilities are found to have at least five disagreements with all the six codes. In fact, if all the instances of more than four disagreements are counted as a single 'uncertain' state, it is found that there are only 62 possible states, these including those states where there are no, one, two, three or four disagreements with one of the codes. It will be recalled that all received combinations with five or more disagreements out of the whole 1 6 bits are unidentifiable, so clearly if this number of disagreements exists in any 1 3 of the bits the received combination will not be identifiable and can properly be represented as uncertain.

The 62 possible states can be coded by 6 bits.

These intermediate codes are then applied to a second read-only memory, ROM B, which has 9 inputs for receiving a 9-bit address. The first three bits of the received codes constitute the other three inputs of this ROM. This ROM provides a one-of-seven output where one of seven individual output lines is activated indicating the likely presence of one of the six input codes or an uncertain state. Of course, if ROM A provides an 'uncertain' output code, then ROM B automatically provides an 'uncertain' output. For the other intermediate codes ROM B stores respective outputs for the 488 possibilities, many of which will also provide an 'uncertain' output, but the others of which will indicate the likely presence of one of the received codes.

In one implementation of the circuit of Figure 2, the ROM A can be a type 2764 ROM and the ROM B can be a type 2708 ROM, both manufactured by Inter Corporation, Santa Clara, CA 95051, United States of America.

In a modification of the system of Figure 2, ROM A could take the form of a 12-bit ROM.

There are 88 possible states in this instance which can be coded by 7 intermediate bits, so that an 11-bit ROM B would be required. If ROM A is an 11bit ROM, there are 117 possible intermediate states which can still be coded by 7 intermediate bits, so that a 12-bit ROM B can be used.

It will be appreciated that the allocation of codes to the intermediate possibilities is entirely arbitrary.

While the above description has been given using a 1 6 bit code identifying 6 states, it will be appreciated that it is of course applicable to other distanced code formats.

Thus, as described, the operations are broken down in a particularly neat manner into operations of practicable complexity. We have appreciated that when only some of the received bits are considered, although it is not possible to determine the final outcome of the decoding, nevertheless the number of relevant possibilities can be reduced to a number very much smaller than the number of possible input states. These intermediate possibilities can be coded and combined with some or all of the remaining input bits to give the final result.

The system can be expanded in principle to the use of more than two ROMs. Two possible arrangements are diagrammatically shown in Figures 3 and 4. In each instance the outputs of an intermediate ROM go as inputs to a subsequent ROM.

In Figure 3, the input bits are broken into three groups of which two mght typically be of equal size and be applied to respective ROMs E and F, while the third, smaller group is applied to a third ROM G together with intermediate codes from the ROMs E and F. In Figure 4 the three ROMs H, J and K are connected in cascade so that there are two successive sets of intermediate codes.

The techniques described are well suited to very large scale integration (VLSI) techniques, where the intermediate codes would exist only within the circuit chips.

Claims (3)

Claims

1. Apparatus for decoding distanced digital data codes, comprising input means for receiving m bit received codes, first read-only memory (ROM) means connected to the input means to receive n only of the bits of the received codes (where n is less than m) and to provide an output of p intermediate bits (where p is less than n) identifying all the relevant states of the n bits, and further read-only memory means connected to the first ROM means to receive the p intermediate bits and to the input means to receive the others of the received bits and providing the output of the apparatus.

2. Apparatus according to claim 1, in which the said further ROM means itself comprises at least two individual ROM means the output of one of which is applied as an input to the other.

3. Apparatus for decoding distanced digital data codes, substantially as herein described with reference to the drawing.