GB2125172A - Multicylinder engine analysis apparatus - Google Patents

Abstract

A multi-cylinder engine analysis apparatus includes a presettable synchronising counter (21), first circuit means (IF1, R1C1) for connecting a clock input of said counter to a switch means (11) of the ignition system of the engine under test, so that, in use, the counter is clocked each time said switch means becomes conductive, second circuit means (IF2) connecting a reset terminal of the counter to a probe (25) for attachment to a selected one of the spark plug leads of the engine under test, first means (27) sensitive to the count state of the counter for providing an output signal when the counter is in its reset state, and second means (22) sensitive to the count state of the counter for setting the counter to a pre-selected count state on a receipt of the clock signal following that which clocked the counter to its reset state. <IMAGE>

Description

SPECIFICATION Multicylinder engine analysis apparatus This invention relates to a multicylinder engine analysis apparatus for testing of an engine function.

It is known in engine testing to utilise the engine contact breaker (or transistor switch where one is used) to clock a ring counter which keeps track of which cylinder of the engine is being fired at any given time. A probe attached to one of the spark plug leads to indicate when that spark plug is energised, is connected to the ring counter to reset it periodically. One of the tests which is carried out conventionally in engine analysis is a so-called power test, in which energisation of one of the spark plugs is inhibited in each engine cycle and the effect on engine performance is measured. This test is carried out on each cylinder in turn and clearly this gives rise to the problem of ensuring resetting of the ring counter when the cylinder, to the spark plug lead of which the aforementioned probe is attached is under test.

In prior U.S. Specification No. Re 29810 the ring counter has a number of stage outputs and switches connected to these are actuated to determine which cylinder has its spark suppressed. Further switches are used to route a resetting pulse from a selected one of the counter stages to the reset input. Thus signals from the stage outputs have to pass through a relatively complex switch network.

According to the present invention there is provided a multi-cylinder engine analysis apparatus which includes a presettable synchronising counter, first circuit means for connecting a clock input of said counter to a switch means of the ignition system of the engine under test, so that, in use, the counter is clocked each time said switch means becomes conductive, second circuit means connecting a reset terminal of the counter to a probe for attachment to a selected one of the spark plug leads of the engine under test, first means sensitive to the count state of the counter for providing an output signal when the counter is in its reset state, and second means sensitive to the count state of the counter for setting the counter to a pre-selected count state on a receipt of the clock signal following that which clocked the counter to its reset state.

With this arrangement a reset pulse from the probe normally arrives when the counter has already been clocked to its reset state, and thus has no effect. The reset pulse is only effective at the commencement of testing or at any other time if the synchronising counter has become out of phase with engine operation. Proper synchronous cyclic operation continues even if no reset pulses are generated during a phase of the testing, without requiring complex pulse-routing switch circuits.

The preset data for the synchronising counter may be derived from a micro-computer or from a simple selector switch. Where the counter is a down counter, the preset data is chosen to preset the count tb a number one less than the number of cylinders of the engine under test.

The apparatus preferably also includes a pattern generator circuit for use in the power test mentioned above and including a shift register the load input of which is connected to a triggering circuit enabled by the output signal of said first means sensitive to the count state of the counter so that data presented to the parallel inputs of the shift register is loaded into it each time said output signal is produced and the clock terminal of which is connected to said first circuit means, the shift register providing a serial output which is used for inhibiting spart production when required.

An example of the invention is shown in the accompanying drawings in which: Figure 1 is a diagram showing the example of the invention; and Figure 2 is a waveform diagram showing waveforms at various points in Figure 1 during operation of the apparatus.

The apparatus is shown in Figure 1 connected to the spark ignition system of an engine which is under test. As shown the ignition system includes an ignition transformer 10 with its primary winding connected in series with the contact breaker 11 between a supply rail 12, connected by the vehicle ignition switch 1 3 to the vehicle battery 14, and earth. The secondary winding of the transformer 10 is connected by a distributor 1 5 to the engine spark plugs.

The apparatus includes a first interface circuit IF 1 with its input connected to the non-earthed side of the contact breaker 11. The circuit IF 1 is of generally known form including resistor-capacitor noise suppression circuits and a Schmitt trigger or similar circuit so as to provide a "clean" voltage signal indicating whether the contact breaker is closed or open. This voltage signal is shown in Figure 2(a), the signal being high when the contact breaker is closed, and low when the contact breaker is open.

There is also a second interface circuit IF 2 which has a probe 20 connected to its input, such probe being inductivity coupled to one of the distributor output leads. The circuit IF 2 is again of known form to provide a "clean" pulse indicative of energisation of the appropriate spark plug. This pulse is shown in Figure 2(h).

The output of circuit IF 1 is connected by an R-C delay circuit R1, C1 to the CLOCK input of a CMOS integrated circuit presettable up/down counter 21 (Type 4516) so that this counter is clocked each time the circuit breaker 11 closes.

The counter has its U/D terminal grounded so that it operates as a down counter. The preset data inputs P1 to P4 of the counter are connected to a source of a 4-bit signal (not shown) which may be a switch array, a micro-computer or any other suitable input circuit, to provide a four bit binary input selected in accordance with the number of cylinders of the engine under test. In fact the binary input is one less than the number of cylinders, i.e. 0011 for a four cylinder engine, 0101 for a six cylinder engine, 0111 for an eight cylinder engine and so on.

The P.E. (preset enable) input terminal of the counter 21 is connected to the output of a NOR gate 22 which has its inputs connected to the respective outputs of four inverters 23 to 26 which have their inputs connected to the Q1 to Q4 outputs of the counter. With this arrangement, whenever the count state of counter 21 changes from 0000 to 1111 the gate 22 provides an output signal which causes the count state of counter 21 to be set to the preset data. At other times the signal at the PE terminal is low so that the counter 21 counts the signals from circuit IF 1.

The output of the circuit IF 2 is connected to the RESET input of the counter 21. The effect of this is that, whenever the count state of counter 21 is other than 0000 when the pulse from circuit IF 2 arrives, the count state is changed to 0000.

This can occur when the apparatus is first connected, but may also occur during testing if the counter 21 gets out of step with the engine for any reason.

A further NOR gate 27 has its inputs connected directly to the Q, to Q4 outputs of counter 21 and provides a high output for as long as the count state of counter 21 is 0000 in each cycle of operation.

As shown in Figure 1 the output of gate 27 is used (inter alia) to control the loading of a 12-bit shift register made up of two Type 4021 CMOS integrated circuits 28, 29. To this end the load (P/S) terminal of each circuit 28, 29 is connected to the output of a NOR gate 30 which has one input connected to the output of an inverter 31, the input of which is connected to the output of the gate 27. The other input of gate 30 is connected to the output of a NAND gate 32.One input of NAND gate 32 is connected via an R-C delay circuit R2, C2 to the output of circuit IF 1 and the other input of gate 32 is connected to the output of a NAND gate 33 which has one input connected to a supply and the other connected via another R-C delay circuit R3, C3 which has a longer time constant than delay circuit R2,C2 which, in turn, has a significantly longer time constant than delay circuit Rr, C,. The gates 32, 33 and the associated delay circuits form a monostable circuit the output of which goes low briefly following each closing of the contact breaker, as shown in Figure 3(e).The output of inverter 31 is low when the count state of counter 21 is 0000 (Figure 2(d)), so that gate 30 produces a positive going pulse (Figure 2(f)) following the downward transition of the output of inverter 31.

The parallel data inputs of circuits 28, 29 are presented with a 12-bit word, from a microcomputer, a switch array on some other suitable circuit, so as to load a '0' into the register for each cylinder to be fired and a '1' for each cylinder in respect of which the spark is to be suppressed during the power test. This 12-bit word is shifted out of the serial output Q8 by successive closings of the contact breaker. Thus a serial signal is produced at the Q8 output of circuit 28 which is high when spark suppression is required.

This Q8 terminal is connected to a switch circuit 34 of known form which, when conductive provides a sufficiently low impedance in parallel with the contact breaker 11 to permit current flow in the primary winding to continue after opening of the contact breaker so as to prevent sparking.

Such impedance is, however, high enough to ensure that when this continuing current is flowing, opening and closing of the contact breaker can still be detected by circuit 34.

It will be appreciated that when, during the power test, the switch 34 is operated to suppress the spark on the lead to which probe 20 is attached, the counter 21 and the shift register 28, 29 remain in synchronism with the engine. The shift register is loaded in each cycle at an instant following the contact breaker closing prior to opening to fire the plug to which the reference probe is attached and, where the immediately following spark is to be suppressed no problem is created.

No logic signals, the timing of which may be critical, are routed through multiple switch contacts as in the prior art, the setting of the number of cylinders and the selection of the cylinder in which sparking is to be inhibited being effected by setting the 4-bit word and the 12-bit word applied to the counter 21 and the shift register 28, 29.

Claims (4)

1. A multi-cylinder engine analysis apparatus which includes a presettable synchronising counter, first circuit means for connecting a clock input of said counter to a switch means of the ignition system of the engine under test, so that, in use, the counter is clocked each time said switch means becomes conductive, second circuit means connecting a reset terminal of the counter to a probe for attachment to a selected one of the spark plug leads of the engine under test, first means sensitive to the count state of the counter for providing an output signal when the counter is in its reset state, and second means sensitive to the count state of the counter for setting the counter to a pre-selected count state on a receipt of the clock signal following that which clocked the counter to its reset state.

2. Apparatus as claimed in claim 1 in which said counter is a down-counter, preset data being presented to the counter so that said preselected count state represents a number one less than the number of cylinders of the engine under test.

3. Apparatus as claimed in claim 1 or claim 2 further comprising a pattern generator circuit which includes a shift register the load input of which is connected to a triggering circuit enabled by the output signal of said first means sensitive to the count state of the counter so that data presented to the parallel inputs of the shift register is loaded into it each time said output signal is produced and the clock terminal of which is connected to said first circuit means, the shift register providing a serial output which is used for inhibiting spark production when required.

4. A multi-cylinder engine analysis apparatus substantially as hereinbefore described with reference to the accompanying drawings.