GB2120485A - Transient data recorder systems - Google Patents

Abstract

Apparatus for sampling an analogue signal includes a CCD having a plurality of multiphase charge transfer electrode arrays; a corresponding number of drivers each driving a respective array at a frequency of at least 150MH2; and means for stopping the drivers at peak output within one cycle time with an undershoot of less than 20% of the peak-to-peak waveform voltage.

Description

1 GB 2 120 485 A 1

SPECIFICATION

Transient data recorder systems The present invention is directed to methods and apparatus for transient data recording, and more particularly, is directed to such methods and apparatus utilizing high speed charge coupled device 5 systems.

The recording of bandwidth transient data by compute r-compati ble instruments has presented a significant challenge to instrumentation developers. Transient data (i.e., any high-bandwidth data in a lowbandwidth background) has been recorded with cameras mounted on oscilloscopes. The resulting photographs are then digitized with manual or semi-automatic equipment. A variation of the traditional 10 oscilloscopes, the scan converter, replaced the scope face with an electronically read storage matrix.

Conventional direct digital transient data recorders are also known in which filtered, continuous analog data is sampled, digitized, and stored digitally in real-time.

Transient data recorders have also used high speed charge-coupled devices (CCD) to provide a dual-speed analog buffer. Full-rate, sampled analog data (i.e., discrete-in-time, continuous-in-amplitude 15 15 data) are shifted into the CCD in a charge-equivalent-to-signal form at the full sampling rate, typically five times the bandwidth. Data are continuously shifted in until a trigger stops the process. The trigger can occur before, during or after the event of interest. Once the event is captured, the data may be shifted out of the CCD at a slower rate [Y. J. Chan, et aL, "Extremely High Speed CCD Analog Delay Line", Proceedings of 1975 International Conference on the Application of Charge-Coupled Devices, 20 San Diego, California, October 29-31, 1975, pp. 389-398; D. A. Gradl, et al., "High Speed Operations of CCDs", ibid, pp. 399--412; T. E. Linnenbrink, et al., "A CCD-Based Transient Data Recorder", ibld, pp. 443-453; and J. W. Balch, et al., "A CCD Integrated Circuit for Transient Data Recorders", Proceedings of Conference on Charge-Coupled Device Technology and Applications, Washington, D.C., November 30 - December 2, 1976, pp. 115-119]. However, such conventional 25 25 transient data recording systems have undesirable performance limitations, particularly in respect of operation at very high frequencies such as sampling frequencies greater than 100 MHz.

In this connection, there is a need for signal sampling systems and CCD transport driving systems which operate at very high frequencies, and the development of such systems has presented substantial difficulty in the art. For example, charge transport drivers which are capable of driving the relatively high 30 capacitance load (e.g., 40 picofarads) of CCD transport electrodes over a broad range of frequencies (e.g.,,DC to 200 MHz) at relatively high voltage swings, while retaining the capability of stopping charge transport without sampled signal loss, are not conventionally available.

Accordingly, it is an object of the present invention to provide an improved circuit for coupling the transport electrode array of a charge coupled device to a high frequency driver. 35 35 The nature of the invention will become more apparent from the following detailed description and the accompanying drawings of which:

FIGURE 1 is a block diagram of a transient data recorder comprising a charge coupled device and an exerciser for the device; FIGURE 2 is a circuit schematic of the M1 -CCD interface of the recorder of FIGURE 1; 40 40 FIGURE 3 is a circuit schematic of the M2-DC Bias circuit for the recorder of FIGURE 1; FIGURE 4 is a circuit schematic of the M3-fast ECL circuitry of the recorder of FIGURE 1; FIGURE 5 is a circuit schematic of the M4-slow ECL circuitry of the recorder of FIGURE 1; FIGURE 6 is a circuit schematic of the M5-output driver circuitry of the recorder of FIGURE 1; FIGURE 7 is a circuit schematic of the M6 signal distribution circuitry of the recorder of FIGURE 1; 4E 45 FIGURE 8 is a circuit schematic of the SM4 output amplifier submodule of the CCD interface module of the recorder of FIGURE 1; FIGURE 9 is a top schematic view of the CCD of the recorder of FIGURE 1; FIGURE 10 is a cross sectional side view of one channel of the CCD of FIGURE 9 with a schematic representation of the multiplexing output channel and output structure; 50 50 FIGURE 11 is a circuit schematic of the dual input gate driver for the CCD of FIGURE 9; FIGURE 12 is a circuit schematic of the high frequency drivers for the transport electrodes of the CCD of FIGURE 9; FIGURE 14 is a reproduction of oscilloscope traces of the. output of the driver of FIGURE 12 showing its abrupt turn-off capability; 55 55 FIGURE 15 is a circuit schematic of the coupling circuitry for coupling the drivers of FIGURE 12 to the CCD of FIGURE 9; and FIGURE 16 is a graph of coupling performance for the circuit of FIGURE 15.

Generally, the present invention is directed to transient data recording methods and apparatus utilizing high speed charge coupled devices comprising a plurality of channels each including a sample 60 section and a charge storage and transport section. The methods and apparatus further utilize means for parallel distribution of the sample signal to the respective plurality of sampling means of the CCD, with predetermined signal delay increments, as will be more fully described hereinafter.

The signal sampling means of the charge coupled device may comprise an input diffusion disposed in a buried charge transport channel, and an isolation gate, a cutter gate, a signal gate and a 65 2 GB 2 120 485 A 2 buffer gate structure disposed adjacent such channel. The CCD will further comprise a signal transport and storage section utilizing a multiphase electrode system for signal transport therein of the signal charge packets provided by the sampling means. Suitable means for driving the cutter gate and the buffer gate, and for driving the transport electrode system are also provided.

5 The buffer gate is independent of electrical connection to the multiphase transport electrode 5 system, and means for driving the buffer gate is provided which produces a duty cycle different from (i.e.

larger than) and with a faster nse time than the duty cycle and rise time of the transport electrode driving means.

The multiphase transport electrode driving means provided herein, in turn, form an important part of the present disclosure. In accordance with the present invention, such driving meansare provided 10 which generate multiphase driving signals at a frequency of at least 150 MHz, and preferably at least MHz, and a peak to peak output voltage of at least about 6 volts, and preferably at least about 8 volts to drive a CCD transport electrode capacitive load of at least about 40 picofarads and preferably at least about 50 picofarads. The driving means should also be adapted to immediately stop generating the output signal, within one cycle time period, while substantially continuously maintaining the peak 15 output voltage to maintain charge storage in the transfer channel of the CCD. - The invention will now be more particularly described with respect to the embodiment 10 of a transient data recorder illustrated in FIGURE 1 of the drawings. The illustrated recorder 10 comprises a charge coupled device 12. The CCD 12 itself comprises a plurality of individual signal samplers and 20 associated charge transport channels, as shown in FIGURES 9 and 10. The CCD 12 is of buried channel, 20 high speed peristaltic design, utilizing a parallel structure which minimizes the clock and sampling requirements to one each, respectively. A common sampler driver accordingly drives all channels, simultaneously to provide good sampler matching. In order to provide a plurality of (e.g., five) samples per clock cycle, the input signal is split into a corresponding plurality of segments, uniquely delayed to 25 I/n cycle intervals (where n is the number of samples to be taken per cycle and I is a cycle period) and 25 separately brought to the CCD's n input ports. Other configurations are possible, such as accommodating multiple signal inputs at slower sampling rate and shorter record length.

As shown in the illustrations of FIGURES 2, 9 and 10, the pin connections at the CCD interface module M 1, and their various functions may be set forth as follows:

30 IN 1 -IN5 - Input Gates 1-5. The analog signal input gate of the 5 samplers. Signals provided 30 from signal splitting module M6 via appropriate delay cables.

ID1-ID5 - Input Diffusion 1-5. The sampler input diffusions are dc biased to provide the source of charge which is quantized by the sampler.

CHS - Channel Stop. Heavily doped diffusion lines which define each CCD channel perimeter and 35 isolate it. The CHS is biased with respect to the substrate in a manner which provides a potential barrier 35 to signal charge in the CCD structure in accordance with conventional practice.

cPBG -Buffer Gate. The first clocked electrode to the right of the sampler signal gate, It isolates the samplerfrorn the rest of the channel during the charge quantizing period. It later provides a potential well to remove charge from under the signal gate, after the charge quantization is completed. (This 40 electrode extends across all 5 signal channels, which are clocked simultaneously). 40 011 -fl4 -The four transport gates of input channels. These electrodes receive four phased, driving waveforms which propagate charge packets received from the sampler, down the input channel to the output multiplexing channel, in a controlled manner. These gates are driven at high speeds when acquiring data, then at low speeds during data readout.

45 SUB -Substrate. The lowermost semiconductor layer of the CCD. Receives a dc bias voltage and 45 serves as a reference electrode when biasing all other electrodes.

cPP SG -Parallel Series Gate. The last transfer gate of the input registers (channels). It is driven with a synchronous waveform which controls charge transfer during data readout, from the 5 input registers into the multiplexing output register.

50 O 1-W4 - The four transport gates of the output register. The electrodes are driving with 50 synchronized low speed waveforms which control charge transfer along the output register (output register is 10 cells in length) during the data readout mode.

NM - N Mout Diffusion, A heavily doped diffusion ring surrounding the active CCD structure which isolates the active region from external thermally generated charge carriers. It is dc biased.

55 OUT - Output FET source electrode. Connects to the external portion of the output amplifier 55 circuit.

OD - Output FET drain electrode. Connects to the external portion of the output amplifier circuit.

SK - Output charge sink. The electrode which removes the signal charge from the output structure, after the data has been read out. Receives a dc bias voltage only.

60 RG - Reset FET Gate electrode. Receives a synchronous waveform which controls signal charge 60 removal from the output diffusion, after data readout.

TG - Tetrode Gate (of Reset FET). Acts to reduce clock noise on the output signal by reducing RG to output diffusion capacitance. It is dc biased "on" at all times.

OTG - Output Transfer Gate. The last gate of the output register. Provides isolation between the final transport gate and the output diffusion. It is dc biased (no AC waveform). 65 3 GB 2 120 485 A 3 ISM -Isolation MOUT. Same Description as NM.

OCG - Cutter Gate. The sampler gate which permits or blocks charge flow between the ID and IN, thus controlling the charge quantizing process. (This gate extends across all 5 input structures and thus provides simultaneous sampling at all 5 channels.

5 When the cutter gate potential is positive, such that charge flows freely between IN and Id, the 5 charge existing under IN is determined by the signal voltage applied to IN. When the cutter gate potential is shifted negatively, the charge under IN at that moment is isolated, and then becomes independent of the signal voltage.

ISG - Input isolation gate. The first input channel gate, adjacent to the input diffusions (01-5).

The gate is dc biased very positively to permit free charge flow under it at all times. (This gate extends 10 across all 5 input channels). It provides isolation between ID and OCG.

The exerciser 14 is an array of modules which may be housed in a conventional, rack-mountable chassis and which provides all the timing, drive waveforms, biasing and signal interfacing the CCD requires to function as a transient recorder.

15 The major exerciser modules, and key submodules are diagrammed in FIGURE 1. As shown in 15 FIGURE 1, CCD interface module M1 is the principle module of the exerciser 14 because it links all signals with the CCD 12. The CCD 12 is mounted on the exerciser 14 by means of a pressure plate (not shown) which applies force to the O-ring to distribute it directly to the CCD leads, forming a pressure contact with mating, gold-plated traces on the M 1 circuit board. Chip resistors and capacitors are used 20 close to the CCD to optimize high frequency signal handling. Critical submodules are mounted directly 20 to the CCD interface M 1. In this regard, two, dual transport drivers SM3 provide charge propagation in the five parallel input registers of the CCD 12. The transport drivers SM3 provide relatively constant rise and fall times (1.6 ns) and amplitude (11 OVp-p) over their full DC to 250 MHz operating range. They are driven directly from relatively low voltage ECL logic. Similarly, input driver SM1 operates the on-chip 25 signal sampler. It, too, operates from ECL logic provided by ECL logic circuitry of module M3 over a 25 DC-250 MHz range. The off-chip portion of the output amplifier is provided by submodule SM4 of the CCD interface module M 1, which, in combination with on-chip circuitry, converts signal in charge equivalent form to a conventional voltage-equ iva lent form.

Incoming signal to be recorded is brought to the signal distribution module M6, which is a 5:1, 50 30 ohm power divider. Signal delay between CCD channels is accomplished by precisely varying the 30 lengths of coaxial cables linking: signal distribution module M6 with CCD interface module M 1.

The various DC biases required to operate the CCD are generated on the CCD Bias module M2. All biases used are developed from sources regulated on DC Bias module M2 and set by potentiometers on DC Bias module M2. The biases are brought to CCD interface module M 1 via two, twisted-pair flat 35 cables. 35 Charge propagation in the single, serial, output channel is provided by the output drivers M5.

Adjustment of both the high and low levels of each individual driver is provided. As in M2, these levels are derived from locally regulated voltages. All drivers are driven directly from ECL logic having an output voltage level of 0.8 volts peak to peak.

40 Timing among the various drivers is partitioned between fast ECL control module M3 and slow 40 ECL control module M4. The faster circuitry (M3) operates from a fast clock (FC) at rates from DC to 500 MHz with sub-nanosecond edges. The slower circuitry (M4) operates simultaneously from one tenth FC (DC-500 MHz) and from an asynchronous slow clock (SC), or DC to 2MHz, all with two nanosecond edges. Logic is Minimized on fast ECL module M3 because of the extra care required in 45 handling sub-nanosecond edges and 500 MHz clocking via microstrip, wire-over-ground-plane, and 45 coaxial transmission lines. To the greatest extent practical, control is handled by module M4, leaving only the signal sampler timing, input register timing, and triggers to external equipment on module M3.

All programmable control functions reside on module M4 which employs wireover-ground-plane and twisted pair transmission lines. Module M3 is linked to module M4 via twisted pair transmission lines.

50 The control timing required is indicated by the exerciser timing diagram presented as FIGURE 13. 50 Three major states are provided. During READIN, the fast clock (FC) controls signal sampling and the input registers at FC/2. This period in the illustrated embodiment 14 is 9,990 input transfers per channel.

However, only the portion selected by the FAST switches (on M4) causes clocking at the CCD. Using the FAST BCD rotary switches, 0 to 9980 actual input transfers per channel are selected. When the fast 55 transferring begins, the fast trigger (FT) is generated. During READIN, a delayed trigger (DT) is also 55 generated in a manner analogous to that just described for FT. Setting the DCB DELAY switches causes a DT of 0 to 9980 input transfers per channel from the end of READIN. After completing READIN, the exerciser moves into HOLD state during which all circuitry is initialized and M3's input is switched from FC to SC/1 0, a one-tenth slow clock generated by M4. As READOUT mode commences, a slow trigger (ST) is generated. The BCD SLOW switches select 0-990 input transfers per channel at SC/20. 60 Three major modes of operation composed of sequences of the above states are selected either manually, via a rocker switch on MF (not shown), or remotely, via the remote control interface. The standby mode is slow only. It is a sequence of HOLD/READOUT/HOLD/READOUT/HOLD, etc. Repetitive mode is a sequence of HOLD/READIN/HOLD/READOUT/HOLD/READIN, etc. Single shot calls for a single READIN, followed by a HOLD/READOUT/HOLD/READOUT, etc. sequence. Access to these mode 65 4 GB 2 120 485 A 4 controls plus key synchronizing signals permits control of the exerciser from remote circuitry (e.g., computer).

As indicated, the transient recorder 10 utilizes a plurality of interleaved data channels, as illustrated in FIGURE 9, which is a top semi-schematic view of a CCD 12 of the type contemplated for 5 use with the exerciser 14. As indicated on the drawing, the CCD 12 has five substantially identical data 5 channels defined by adjoining impurity diffused or ion implanted channel stop zone in accordance with buried channel CCD design techniques. The sampling and charge transport functions of all channels are closed simultaneously and each channel has a substantially identical signal sampler, which will be more fully described in connection with FIGURE 10. All gate fingers and transport electrodes are extended 10 directly across all channels, with the exception of the signal gates which are brought out separately. 10 Interleaved sampling is achieved by providing delayed signal waveforms to each of the channels. The reference channel is operationally identical to each signal channel, and 1, 2 or 4 phase drive is compatible with this signal sampling system.

As shown in FIGURES 9 and 10, the CCD has input diffusions ID1-5 for the four channel 15 samplers and the reference channel sampler, respectively, and appropriate input connections to ID1-5 15 thereto. The respective input signals to the five data channels, IN1-5 are applied to the respective signal gates, as illustrated. Unlike the other electrode gates, the signal gate, as illustrated only overlay their respective data channels. Appropriate connections are also provided to the isolation gate (OBG), the cutter gate (OCG), the buffer gate (BG), the four phase transport electrodes (01 --4) and the various 20 other CCD chip structures. 20 As shown in more detail in FIGURE 10, which is a cross sectional view of the sampler section of the first data channel of the CCD of FIGURE 9. The CCD structure is seen to be of the buried channel CCD type having an input diffusion ID1 to which a de bias voltage is applied. The samplerfurther has an isolation gate ISG which is also dc biased. The bias voltages are supplied to the CCD 12 by the module 25 M2. In operation, and which serves to control and make uniform the charge transport from the input 25 diffusion adjacent the isolation gate is a cutter gate which functions to"cut off- the amount of signal charge transported to the signal gate as a signal sample. The cutter gate is driven by the submodule SM 1 dual input gate driver of the interface module M2. Accordingly, the gate next adjacent the cutter gate is the signal gate to which the continuously varying analog signal is applied. The final gate of the 30 input structure is the buffer gate 13G which is also driven by the submodule SM 'I dual input gate driver 30 of the CCD interface module M2. The buffer gate is an important aspect of the sampler and sampling methods relating thereto. Through the provisions of the buffer gate following the signal gate, rather than a conventional electrode which is a part of the transport electrode system, sampler operating parameters may be substantially improved, as will be more fully described hereinafter.

35 The transport electrode system follows the buffer gate, and may be a conventional form phase 35 transport electrode system, but beginning with the phase 2 electrode, as shown. These transport electrodes are bussed to many suceeding electrodes, and function to transfer charge packets, which have been generated by the sampler, down the CCD structure.

The nominal gate size is 5 microns along the channel for all the sampler and transport gates, with 40 the exception of the first transport gate as illustrated, which may be longer (e.g., twice as long) to 40 improve charge flow from the buffer gate.

In operation, each electrode generates a potential in the CCD channel region which is a function of the voltage applied to the respective electrode. When the signal voltage is applied to the respective signal gate, it creates a continuously varying potential therebelow in the CCD channel. Charge is flooded 45 from the input diffusion under the dc biased isolation gate and the cutter gate to the signal gate region 45 of the CCD channel. The amount of charge which resides under the signal gate is determined by the signal voltage on the signal gate, so as the voltage varies on the signal gate, the amount of charge residing under the signal gate varies proportionately. Sampling is carried out by periodically cutting off the charge flow between signal gate and the source of charge by means of a negative voltage charge pulse applied to the cutter gate to pinch off the charge flow and isolate the quantity of charge under the 50 signal gate. The isolated charge is generally proportional to the signal voltage at the time the cutter gate voltage goes negative. The isolated signal charge is transferred from the channel zone under the signal gate to the zone under the buffer gate at the clock frequency. As indicated, the provision of the buffer gate is a desirable feature of the sampler system. By providing a separate buffer gate, and by applying a 55 separate waveform to the buffer gate, the time period during which the charge flows from the input 55 diffusion into the CCD zone under the signal gate may be extended, and better equilibration of the signal charge may be provided thereby to produce a more accurate relation between the signal voltage and the isolated signal charge produced by the sampler.

By providing a relatively low capacitance---extra-buffer gate, which would otherwise be a (511 60 electrode of the relatively high capacitance transport electrode system, improved waveform control may 60 be provided to the buffer gate.

In this connection, controlling the waveform in a propagation gate for a charge coupled device is difficult at operating frequencies greater than 100 MHz, and the transport waveform for drawing the transport electrode system may be of sinewave or sawtooth shape not particularly well adapted for 65 control of signal sampling. 65 5 GB 2 120 485 A 5 The advantage of the buffer gate is that the very low capacitance (which may be less than about 2 pf, e.g., about 1 pf in the illustrated embodiment 12) facilitates drive and control of a waveform which minimizes fringing and related adverse signal sampling effects between the buffer gate and the signal gate.

5 The charge transport electrodes of the CCD 12 present a capacitance of about 50 pf, and may be 5 charged to about 10 volts in less than or about 2 nanoseconds, in order to provide 250 MHz operation.

However, the rise time on the low capacitance buffer gate is about one nanosecond (90% peak to peak rise time) which permits a "squarer" wave above 100 MHz operation, which is beneficial to signal sampling. Further, while the duty cycle of the transport electrode waveform is substantially 50%, the 10 duty cycle of the separate buffer gate maybe extended to substantially more than 50% (e.g., 60-70% 10 or more) to facilitate charge sample equilibration and transport. Desirably, the signal applied to the buffer gate will be substantially in phase with the i 1 transport electrode waveform from the propagation drivers at the beginning of the positive voltage duty cycle, but will have a faster rise time and fall time, and will extend longer in time, such as about 10-50% longer than the positive duty cycle 15 time of the 01 transport electrode waveform. 15 The driver submodules SM1 and SM3 for supplying the CCD sampler and transport electrode propagation signals will now be more specifically discussed in respect of the CCD interface module M 1.

The CCD interface module M 1, the circuit components of which are as shown in FIGURE 2 and the following component list tables, interfaces all drive waveforms, signals and DC bias to and from the CCD 20 12. It further provides a socket which eliminates the need for permanent CCD attachment. 20 6 GB 2 120 485 A 6 EXERCISER PARTS LIST Module M 1 - CCD Interface Designation Description Value Qty Same Parts

R31 Resistor 1% 93.19 2 R35 R1 11 11 100 9 R2, 5,6,8-12 R3 1 K 13 R4 R33 10K 7 R7,29,26,23, 20,17,14 R34 11 5%1/4w 100 6 R38,44,30,41, 47 R1 5,18,21 Chip Res. 42% 50.0 5 (MS1 Mfgr) 24,27 C5 CAP, Ceramic.001 jo 3 C7,2 cl 1, 11.1 Af 16 See Schematic C88,, Tant 20V - 15 juf 2 C87 C10,, Chip 5OV.12 juf 15 C8,11,18,21, 27,24,30,33, 45,55,59,61, 54,49 C60.001 22 See Schematic C52 1 Oopf 2 C47 26 Pin Header Ansley 5 J6,7,8, 5,4 Textronix Probe 6 Socket Coax Connector SMA 5 IN1-IN5 Spacer 3/W 1 ng 16 Machine Screws 4/40 x 11/4 16 Lockwashers #4 16 Ll, L2 - Wire Jumper Replaces Component C69, 73, 77, 81, 85 7_ GB 2 120 485 A 7 Module M2 CCD-Bias Designation Description Value Qty

R4 Resistor 5% 6.8 l 1/4 Watt R9 11 11 11 11 11 11 R16 It 11 8.2 t, 11 11 R14 11 11 27 It 11 11 R19 11 1%MF 100 11 11 11 R24 11 11 11 11 11 11 R6 11 5% 270 11 t, 11 R1 R137 R11 11 1% 453 11 11 R2 11 - 11 11 11 11 R31 11 R35 00 R7 11 11 11 11 0# 11 R39 It 1 %MF 619 11 11 11 R43 #l 11 11 11 11 11 1 R47 It 01 11 11 1, 11 R51 R136 R59 10 1% 825 11 11 11 R85 10 11 1K 01 11 11 R77 11 01 1.33K 11 11 tt R73 R69 R65 01 11 01 11 11 10 R61 11 R128 1%MF 1.78K R132 11 R15 #1 2.43K 8 GB 2 120 485 A 8 Module M2 - CCD-Bias (Continued) Designation Description Value Qty

R80 Resistor 1%MF 3.48K 1 1/4 Watt R129 11 11 R133 It 11 R5 11 11 11 11 $1 11 R105 11 11 11 11 11 11.

R101 11 R97 01 R93 11 R89 It R84 11 11 11 10 01 01 R104 10 4.42K R100 10 11 R96 to It R92 It It to It It R88 R36 to 4.99K It R32 #1 0, 11 1, #1 11 R10 11 1 %MF 5.90K 11 11 11 R23 11 11 6.19K 11 11 It R28 11 01 11 11 10 R13 11 11 11 or 11 p R76 % 6.65K R72 11 R68 01 R64 '1 11 to 11 11 '1 R60 11 0, 11 R34 5% 8.2K R30 11 R18 % 8.25K 9 GB 2 120 485 A 9 Module M2 CC1)-Blas (Cont'd) Designatio n Description Value ' Qty Same Parts

R138 Resistor 5% 10K 1/4 Watt R139 of 10 11 11 11 R81 0, 1 %MF 1.OK 01 11 11 R20 11. 11 1 OOK 11 11 11 R25 11 It 00 0# 10 11 R3 POT 100 It Cermet M-T Trim R8 11 11 ot 11 11 R12 11 500 11 1, 11 R17 POT 2 K If 11 11 R38 to 2.5K 19 11 11 R42 to It 1, 01 11 - fi54 10 01 11 11 11 1150 to R46 01 R57 5K R33 R2b R82 10K R86 R90 of It 11 11 11 R94 R98 R102 R106 R130 ot 11 11 11 11 R134 R62 R70 R74 R78 10 GB 2 120 485 A 10 Module M2 CCD-Bias_ (Cont'd) Designation Description Value Oty Same Parts

R22,27 POT 20K lea Cermet M-T Trim C19 CAP, Ceramic lyf 9 C20,23,27,24, 26, 28,25,29 C47.011tf 31 C 18, 21, 25, 22, 31, 33,35,37,39, 41,42,43,44,45, 46,6,2, 9,4,16, 12,60,59,53,52, 51,50,49,48,3 Cl,,Tantalum 4.7,uf 1 C5 Ceramic 330pf 3 Cl 1, 8 C17 Tantalum 47pf 9 C 13, 30, 7, 32, 36, 38,34,10 D 1 Diode IN914A 2 D3 D5 It IN914B 6 D6,7,8,9, 10 Dil IN40012 D12 D4 IN5298 2 D2 Ql Transistor 2N2219A 2 02 Q3 2N2905A 1 U5 IC LH0042 2 U6 (National) U3 LA5723B 3 U2, 1 (Lambda) U4 LM304H -1 (National) J9 Connectors 26 PIN 3 J 10, 11 (Ansley) R21 JumperWlre 28 R26,37,41,45, Replaces 49t53,56,63t Component 67,71,75t79, 40,44,48,52, 55,58,135,131, 107,103,99,95, 91,87,83 Rlll Res. Not Used 15 Rl 15,119,123, (Devices on PC 127,108,109, Board but not 112,113,116, used in embodi- 117,120,121, ment 14) 124,125 R110 Pot not used 5 Rpll4,118,122, 126 C14 Cap not used 7 C40,54,55,56, 57,58 11 GB 2 120 485 A 11 Module M3 FAST ECL Designation Description Value Oty

See Resistor 5%1/8w 51 27 Schematic 11 11 11 75 48 (for mul- 11 11 of 100 6 tiple 220 8 circuit 470 9 elements) Holtite CAP Ceramic 0.001 68 0.01 28 33pf 2 f, 11 1 00pf 31 331pf 1 IC (Fairchild) 10101 1 10116 2 1 1C70 11 95101 1 100102 2 Specials, U-#3 1 Functionally J-W4 1 like 11 C01, 1-#5 1 but faster S-#6 1 BNC, CONN 74868 6 Connector Ansley 2 Press-Fit Selectro 9 WC1 Coax Jumper 12.93in UNI-T 95 ohm coax WC2 11.28in WC3 7.93ln WC4 Wire Jumper.2in #24ga. wire over ground plane WC5 Microstrip, Part of Printed Circuit Board 12 GB 2 120 485 A 12 Module M3 - FAST ECL Designation Description Value Oty Same Parts

WC6 Coax Jumper 8.0 in UNI-T 75 ohm coax WC7 Wire Jumper.3 in #24 ga. wire over groundplane WC8 Coax Jumper 1.90 in 75 ohm coax Module M4 -COMPONENT Designation Description Value Oty

See Res Netwk 8PIN 100 26 Schematic SIP (for Res 6Pin SIP 100 2 Multiple 470 6 circuit Resistor M/8w 220 1 elements) Diode 914 6 IC F95010 10 11 F95016 1 00 F951 01 2 F95105 12 F95107 3 F951 10 1 F951 11 1 F95116 2 F95130 2 F95231 6 230002 8 SM 1 3-Debounce 1 OK, 4.7 K resistors, 1 pf CAP, 1 ea Aux Switch 1 Cap, Bypassing 33,uf 1 OV 2 0. 114 AW CER 8 0.0 1 pt cer 20 SC input BNC + 519 5% 1/8w 2209 5% 1/8w SM 1 2-SC in- 10052 5% 1/8w terface 4709 5% 1/8w 0.01 11f 13 GB 2 120 485 A 13 Module M5 Output-Drivers Designation Description Value Qty

R3-AB (R 1 -AB) Resistor 5%1/5w 43 4 SM9 R2-AB 11 11 11 12 2 SM9 Rl 11 1% 274 1 SM1 1 Cl CAP 104M 0. 1 Af 1 11 D1, 2 Diode IN914 2 01 R 1-6 Resistor 1 % 2.87K 6 Dr. Cur. Limiter R 1 Res 1.4K 6 R 1 Pot Cermet 2K Il R 2 10K R 3 25K R 4 200 4 R 5 250 1 Cl, 2 Cap, Ceramic.0 1 luf 6 IC, Dual, Line LM31 91) 3 National I.C.

Receiver Rl Resistor 1% 243 1 SM + 23 Regula R2 Pot 1/2w 500 1 11 11 R3 11 1% 3.92K 1 11 11 Cl Cap(Cl\120C1 04M).01Af C2 Capjant 1 Af U 1 I.C. National LM317T Heat Sink R3 Resistor W/8w 2.2K SW:-12V Reg Cl Cap (Tant) 2.2 iuf C4 11 01 1 1.1f - U 1 LM320T-1 2 -12V National I.C.

Heat Sink 11 6045B, Therm alloy Rl Pot 1/2w 200 SM8-16V Reg R2 Resistor 1%1/2w 1 K R3 Resistor 5%1/8w 3.3K 14 GB 2 120 485 A 14 Module M5 Output-Drivers (Cont'd) Designation Description Value QtY

C1 Cap (Tant) 2.2,uf 1 SM8-.- 16V Reg C2, (CW20C I 04M). 1,Uf 11 01 11 C3, (Tant) Sprague 1 5,uf 10 It 11 C 4 11 11 lpf U 1 LM320T-1 5 - 1 7.5V Heat Sink 11 Thermal loy-6045 B R 1 Resistor 1%1/4w 243 SM6:17.5V Reg R2 Pot, 1/2w 500 11 R3 Resistor 1%1/4w 2.87K R4 Resistor 5%1/8w 3.3K C1 Cap (CW20104M) 1jUf C2, (Tant) 1)Uf U1 LM317T (I.C.) 17.5V National Reg Heat Sink Thermal loy-604513 Module M6 - Signal Distr Designation Description Value Oty

Sl,S1-5 SMA Coax Conn. 6 Selectro 134-8 5 MSI 33 ohm chip res.

131-3 3 100 ohm chip res.

Module M7 - Power Distr Designation Description Value Oty

A1-7 26 Pin Header Con Ansley Part 609-2652M D1-7 15 GB 2 120 485 A 15 Module SM 1 - Input-Driver Designation Description Value Qty

R1 Resistor 5%1/8w 51 1 SM1-WO513 R2 11 11 11 01 11 R3 1. 1 11 11 75 R4 It 51 R5 51 R6 51 R7 $1 of 11 75 11 RS or 19 10 51 11 R9 FP 51 R10 51 R11 75 R12 11 1# P, 51 11 R13 01 01 It 11 FP R14 1 to 11 11 11 11 R15 11 R16 R17 R18 01 11 11 11 11 R19 11 11 11 33 11 R20 It 11 11 11 11 R21 FP, 11/4w 18 FP R22 10 11 It 22 of R23 11 R24 P# 200 R25 of FP to 330 $1 R26 #I FP 00 51 It R27 P, 11 1/8w 11 11 R28 to 11 11 33 11 R29 It P, 10 0 It R30 to, 1/4w 18 to 16 GB 2 120 485 A 16 Module SM 1 - Input-Driver (Cont'd) Designation Description Value Oty

R31 Resistor 5%1/4 W 22 1 R32 11 11 11 R33 1/8w 1 K R34 R35 R36 Pot 1 K R37 p, 10 11 R38 11 11 #1 R39 t# It It R40 Resistor 5% 3.3K or R41 11 01 1/8w 1 K 11 R42 11 11 11 11 11 17 GB 2 120 485 A 17 Module SM1 (Cont'd) Designation Descripti. on Value Qty Same Parts R43 Pot 1 K 1 R44 R45 R46 R47 Resistor 5% 3.3K 11 R48 11 11 11 11 cl Cap 1.5-4pf 11 C2 C3 C4 Chip.1 2,uf C5 11 Oljuf 11 C6 C7 C8 C9 C10 C11 11 11 11 C12 C13 Open 0 0 C14 C15 Cap, Chip.1 2pf 1 C16 1 Ooopf C17.1 2Af C18 1 00opf C19 11 C20 11.12 lif 11 C21 11 11 11 11 C22 11 0, 11 11 C23 11 11 1000 pf 11 18 GB 2 120 485 A 18 Module SM 1 (Confd) - Designation Description Value Oty Same Parts

C24 Cap, Chip 0 0 C25 C26 1 00Opf C27 11 11.1 2pf 11 C28,,Tantalum 33juf C29 Chip 1 00Opf C30 01 10.1 2Af 01 C31 11 01 1 Ooopf 11 R C32 11 C33 Tantalum 33 pf C34 Chip 1 00Opf C35 #1 11.1 2,uf 11 C36 11 01 1 Ooopf 11Q1 Transistor BFR96 02 Q3 Q4 Q5 Q6 [cl 100114 - 1C2 I3G Input Con SMA CG ', SMA 01 19 GB 2 120 485 A 19 Module SM3 - Dual Transport Designation Description Value Qty Same-Parts

R1 Resistor 1 % 49.9 1 Gate Driver A-B R2 R3 R4 11 5% 75 1/8w 11 11 R5 11 11 11 11 11 11 R6 It 1% 49.9 11 11 R7 11 11 75 1/8w 11 11 R8 11 5% 11 11 11 11 R9A 2.7 1/8w 2 R10A R11A 1% 33.2 R12A p R13A - 11 11 60.4 11 11 R14A 1 11 11 11 11 R1 5A 11 11 33.2 11 11 R1 6A 11 5% - 6.8 11 11 R17A 1% 33.2 R18A 5% 10 R19 Pot 1 K 1 11 R20 Resistor 5% 1 K 11 11 C27A Cap-14F1271 Upf 2 C28A, 9410-25 5-25 2 C29A 11 1 Ooopf 2 t, c 1 CAP-GKU4R000 1.5Apf C2 11 C3 If C4 If 1 1 Ooopf C5 lo ol.1 2juf 11 11 20 GB 2 120 485 A 20 Module SM3 (Cont'd) Designation Description Value Qty Same Parts

C6 CAP-GKU4R000 1 Ooopf Gate Driver A-B C7 - 11.1 2pf 11 11 C8A 11 - 1 Ooopf 2 11 C9A 11 11.1 2,uf 11 C10 1 11 1 Ooopf 1 11 C11 11 11.1 2Af 11 11.

C12A 1 00opf 2 C13A 11 11.1 2Af 11 11 C14 Not used Open 0 C15 CAP-GKU4R000 1 Ooopf 1 C16 - 11.1 2Af 1 #1 C17 33juf Cl 8A CAP-GKU4R000 1 Ooopf 2 C19A 11.1 2gf 11 11 -C20A - 11 1 Isjuf 11 11 C21A 11 11.1 2juf 11 00 C22A 1 00opf C23 C24.1 2Af C25 None Open 0 C26 Y, 11 LIA COIL 57-0181 00 2 L2A #22 wire 2 L3A 11 11.051 - ph 0, 11 L4A #22 wire L5A.1 ph L6 20/413 21 GB 2 120 485 A 21 Module SM3 (Cont'd) Designation Description Value Qty Same Parts

L7A COIL 57-3425 Fer Bead 2 Mfg Stackpole L8A 57-0180 D1A IN914B 2 D2A 11 5082-2810 2810 2 H.P.

D3A D4A 01A Transistor BFR96 2 Q2A 2 Q3A MM8009 2 Q4A MRF227 2 IC F 100 1 14FC (24 Pin) F1001 14FC 1 Fairchild Module M4 Output-Amplifier Designation Description Value Oty Same Parts

R5 Resistor 5%1/4w 680 1 SM4-Output-Amp R4 If 1 % " 10K 1 11 11 C1 Cap (CW1 5C1 02M) 0.0 1 pf 1 11 If C4 0.01pf 1 C2 CapSPRAGUE 4.7K C3 CapSPRAGUE 4.7K D 1 IN914B - D2 IN5286 - D3 IN5310 - Q 1 2N2905A BNC-Conn - Textronic Probe - Socket Wire Jumper - As further shown in FIGURE 1, the input signal S1 to be sampled is applied to signal distribution modules M6, schematic component details of which are shown in FIGURE 7.

22 GB 2 120 485 A 22 The module M6 is a matched resistive 5 port splitter which may be used to provide input signals S1, S2, S3, S4, S5 to each of the five channels of the CCID 12. Alternatively, a dc reference voltage may be applied to a reference channel of the CCD, and a plurality of four (or less) input signals from module M6 may be provided to respective CCD data channels. Because the CCID samples each inputs signal 5 substantially simultaneously, differential time delay for the various signals S 1, S2, S3, S4, S5 is 5 provided by appropriate variation of the coaxial cables conducting the signals 1-5 from module M6 to module M 1. In this regard, for example, at a sampling rate of 250 MHz for reference channel and from data channel sampling, 8 inch increments of coaxial cable length (with the S3 cable being W longer than the S2 cable, S4 being W longer than S3, and S5 W longer than S4) produce a 1 nanosecond 10 delay between signals S2-S5 to provide for a GHz sampling of theinput signal by the CCD 12. The 10 coaxial cable incremental length may be varied for different sampling speeds and configurations.

The parallel sample architecture of the CCID in turn is driven by the dual input gate driver submodule SM 1 of the CCID interface module M 1.

As shown in more detail in FIGURE 11, the submodule SM 1 of module M 1 generates two output 15 waveforms to drive the cutter gates and the buffer gate of the CCD 12. The input to submodule SM 1 is 15 a single ECL clock signal 1-411 from module M3, which is directed to two generally similar drivers (operating at different phase) for the cutter and buffer gates, respectively. These two drivers, together with a string of ECL comparators with variable RC circuits coupling them, and various voltage dividers for biasing inputs to these comparators, to provide means for controlling and varying duty cycle of the 20 output signals, and to vary the delay of the respective waveforms to provide for adjustment in respective 20 time delay from input to the respective output signals OCG (cutter gate) and (bBG (buffer gate).

While the relatively low capacitance cutter gate and buffer gate structure of the CCID is driven by sub-module SM 1, the relatively high capacitance four phase transport electrodes of the CCID are driven by two submodules SM3 of module M 1, as shown in FIGURES 1 and 12, which are appropriately driven 25 by fast ECL signal L4)11 and Lfi2, which bear a phase relationship to produce four phase output signals. 25 The basic design of transport driver submodule SM3 comprise an ECL element driving discrete circuitry comprising a differential amplifier stage Q1 A and Q2A, which are driven differentially from final ECL comparator output. In this differential amplifier stage, the collector from each of the two differential transistors then drives the output stage, which is a totem pole output configuration comprising 30 elements Q3A and 04A, where Q4A is a ground emitter stage and Q3A is an emitter follower or 30 grounded collector stage, each of which is driven by a different collector from the differential pair Q1 A, Q2A. The driver uses conventional silicon devices and has very low power dissipation (it only dissipates about 2 watts when operating at low frequency). The drivers are adapted to provide wide range operation, and to permit the stopping of charge transport by abruptly stopping the output waveform.

35 Thus, the CCD dual gate driver sulamodule SM 1 and the transport driver submodules SM3 may be 35 clocked for a limited number, such as 100 or 1000 cycles at high frequency (e.g., 150 MHz or more) and may then be stopped to hold the sampled signal information in the CCID to be shifted out at a relatively very slow rate. In order to stop the transfer of data at high frequency, it is important that the drivers SM3 stop abruptly, within one cycle, and such performance of a. submodule SM3 driver is 40 illustrated in FIGURE 14, where it is noted that stopping the driver (by stopping the ECL input signals) is 40 accomplished in one cycle at the peak output without the output wave-form being reduced by more! than 20% of the peak to peak voltage.

The transport driver interface between the CCID 12 and the driver submodules SM3 is also important, and in this regard, two modules-SM3 are disposed at opposite sides of the CCID 12 and are 45 each connected thereto via two coaxial conductors (one for each output phase) which should desirably 45 be about an inch or less in length. However, simple direct connection of the driver to the CCD because of an admittance multiplier effect produces an undesirable impedance transformation, particularly at high frequency.

In order to alleviate this coupling problem, a resistively compensated coupling circuit is provided 50 as shown in FIGURE 15. 50 Ideally, a characteristically terminated transmission line is preferred, because it would provide maximum frequency bandwidth with minimum waveform distortion, regardless of its length. The high transport gate capacitance of the CCD, however, renders this approach quite difficult. A resistive line termination of value Zo shunting the CCID gate capacitance does reduce the reflection coefficients, 55 especially at lower frequencies, but it also puts an undesirable constraint on the driver. Such a resistive 55 termination would require significant additional output power from the drivers, even at low frequencies.

The extensive driver heatsinking and system heating resulting would be very undesirable. Furthermore, the resistive termination would be overwhelmed by the low gate reactance and provide little benefit at the higher frequencies. For these reasons, the non-resistive terminated line approach is preferred.

60 A short segment of (coupling) transmission line terminated with a pure capacitance representative 60 of the CCD electrode capacitance results in a capacitive input impedance of lower value than the termination itself. The input impedance of the line Zi may be represented by:

23 GB 2 120 485 A 23 Xc - Zo tan. BL zi=-j Xc 1 ±tan BL Zo where Xc is the capacitive reactance of the termination.

5 Zo is the line characteristic impedance. 5 B is the line phase constant L is the line length.

Given Xc, Zo and B, it can be seen that Zi is maximized when BL is minimized. This corresponds to minimum input admittance, the desired condition. The degree of impedance transformation provided by the line can be measured in terms of the admittance multiplier which is defined as Yi/Yc which equals XC/01. 10 The optimum value (Zo') of Zo can be determined by partial differentiation of Equation I with respect to Zo. Setting this expression equal to zero and solving for Zo yields the following:

Zo'= Xc [tan BL + V-1 + -tan BLI (2) This value of Zo minimizes the admittance multiplier, given Xc, B and L.

15 The added series source resistance Ro as shown in FIGURE 15 acts to flatten the amplitude 15 response of the transfer function significantly, as shown in FIGURE 16. In addition, the driver load impedance is increased significantly at the higher frequencies. Desirably, the coaxial cable connecting the driver output to the CCD lead will be less than 1.5 inches in length, and in the illustrated embodiment 10 is 1.0 inch in length. Further, the impedance value Zo of the coaxial cable may desirably 20 be in a range of from about 0.5 to about 2.0 times the optimum impedance value Zol given by equation 20 2 hereinabove. Similarly, the series coupling resistance R in the coupling circuit as shown in FIGURE 15, which represents the sum of driver output resistance and the series added Resistor RO, should have a numerical value in ohms, in the range of from about O.5Zol to about 2. OZol.

As indicated, the fast ECL module M3 drives the driver submodules SM 1 and SM3, and is 25 described in detail in FIGURE 4. The module M3 further has a fast clock (FC) input (DC to 500 MHz) and 25 slow trigger (ST), fast trigger (FT) and delayed trigger (DT) outputs, as well as signal connection to slow ECL module M4.

The slow ECL logic module M4, as shown in FIGURE 5, is intimately associated with the fast ECL module M3 and provides the various counters and programming for the exerciser 14. By means of 30 rotary switches on module M4, the number of fast sampling cycles before switching to slow clocking, 30 and the number of slow cycles may be selected. Module M4 also includes a counter for a programmable delay trigger output, which may be used for triggering an external generator with predetermined delay.

The CCD transport electrode driver for the serial slow output of the "parallel" fast-sampled data stored in the CCD channels is contained in the output driver module M5. Module M5 is a low frequency 35 clock driver which drives the multiplexing register (the short register in the CCD that multiplexes the 5 35 channel outputs). It is a low frequency board of relatively conventional design. It generates five phase output W1 -004 and ORG for the CCD data channels 1-5 as well as I)PS.

The serially clocked CCD output is directed to output amplifier submodule SM4 of CCD interface module M 1, to provide output signal SO. The output amplifier submodule SM4 comprises a source 40 follower amplifier stage combined with a transistor stage in a follower configuration. The field effect 40 transistor is on the CCD itself, and the bipolar transistor is on the SM4 module.

All of the bias voltages and currents necessary to operate the CCD 12 and exerciser 14 are provided by the module M2. As shown in more detail in FIGURE 3, the module M2 itself is of relatively conventional analog circuit design.

45 Accordingly, it will be appreciated that the present disclosure has provided improved transient 45 data recorder systems for driving such systems.

While the present invention has been described with regard to a particular embodiment, it will further be appreciated that various modifications, adaptations and variations may be made based on the present disclosure and are intended to be within the spirit and scope of the present invention.

50 Various of the features of the invention are set forth in the following claims. 50

Claims (2)

1. A CCD system comprising a charge coupled device having a plurality of multiphase charge transport electrode arrays each having a capacitance of at least 50 pf and a corresponding plurality of multiphase drivers for driving said transport electrode arrays, said drivers each comprising means for 55 driving a respective one of each of the transport electrode arrays at a frequency of at least 150 MHz 55 with a peak to peak waveform voltage of at least 6 volts, and means for abruptly stopping the driver 24 GB 2 120 485 A 24 output waveform at a peak output value within one cycle time and with less than 20% undershoot based on said peak to peak waveform voltage.

2. A CCD system in accordance with claim 1 wherein said driver has an average power dissipation of less than 3 watts, is adapted to operate at ambient temperature and further comprises means for stopping said driving waveform at a numerically predetermined cycle peak. 5 Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1983. Published by the Patent Office.

Southampton Buildings, London, WC2A lAY, from which copies may be obtained.

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