GB2120058A - Control arrangement for information signals - Google Patents

Abstract

Control arrangement for audio or video apparatus for controlling, for example, colour saturation, brightness, contrast, volume or tone and comprising, provided on an IC, a control circuit 4 which is connected to a connection pin 5 via a control input 4. Outside the IC a control signal source 6 is also connected to this pin. Depending on the choice, such a control signal source produces either an analogue control signal or a digital control signal. To make the applicability of the IC independent of the control signal source opted for, a detection circuit 20 which produces an indication signal which is representative of the form (analogue or digital) of the control signal is connected to the pin. This indication signal controls a switching arrangement 21 the input of which is connected to the said pin and which has first and second outputs. The first output 23 is connected directly and the second output 24 via an interface circuit 25 to the control input of the control circuit. The interface circuit may be a D to A converter. <IMAGE>

Description

SPECIFICATION Control arrangement for information signals The invention relates a control arrangement for controlling at least one adjustable quantity of an information signal, comprising at least one control circuit having an information signal input for receiving an information signal and a control input; means for receiving a control signal; and first means for coupling the control input of the control circuitto the control signal receiving means; Control arrangements for controlling an adjustable quantity of an information signal; for example the colour saturation, the brightness orthe contrast of a colourTVsignal have been used for many years already. A large number of such control arrangements are at present in the form of integrated circuits having a given number of connecting pins.Atypical example of an integrated circuitfor use in a control arrange mentor a TV receiver is, for example, Applicant's IC TDA 3560. This integrated circuit which has 28 pins includes three control circuits; more specifically, a coloursaturation control circuit, a contrast control circuit and a brightness control circuit. An analogue information signal is applied to each of these control circuits via an information signal input and each control circuit produces an analogue output signal.

In addition, each control circuit has a control input which is coupled via a control signal connecting pin to the output of a control signal source producing a control signal. In contempory control arrangements this control signal is available in analogue form and the control signal source is usually in the form of a potentiometer.

Partly due to the introduction of the microprocessor, the aim is where possible to digitize signals such as theabove-mentionedcontrol signals which have been available so far in the analogue form, or still better to generate them directly in the digital form. If control signals are digital signals then the control arrangement as a whole and more specifically also the portion thereofwhich is in the form of an integrated circuit is to have a different construction than when the colour signals are available in the analogue form. In practice this would meanthatforthesamepurposetwo distinct integrated circuits (IC's) should be produced, namelyonesuitableforreceiving analogue control signals and one suitable for receiving digital control signals.This is, however, very uneconomical.

The invention has for its object to provide a control arrangement which may be predominantly in the form of an integrated circuit, it being possible to apply optionally either analogue control signals or digital control signals to this integrated circuit, there being no need to increase the number of connecting pins of the integrated circuit compared with the original number of pins.

The invention provides a control arrangement ofthe type described in the opening paragraph which is characterized in that:~ - a detection circuit is provided which is connected to the control signal connecting pin and which supplies an indication signal which is representative of the form (analogue ordigital)ofthecontrnlsignal; -said first coupling means comprises first switching means controlled bythe indication signal and has: ~ an input connected to the control signal receiving means; I ~a first output connected to the control input of the control circuit for applying said control signal to the control input when the control signal is in a first of its forms; a a second output; ; ~second means for coupling the second output of the first switching means to the control input of the control circuit for applying said control signal to the control inputwhen the control signal is in a second of its forms.

Fig. 1 shows schematicallythe construction of a prior artcontrol arrangementfor use in a colourTV receiver; Fig. 2 shows a first embodiment of a control arrangement in accordance with the invention; Fig. 3 shows a control signal source for generating a digital control signal foruse inthe control arrangement shown in Fig. 2; Fig. 4 shows a detection ci rcuit for use in the control arrangement shown in Fig. 2; Fig. 5 shows an interface circuit for use in the control arrangement shown in Fig. 2; Fig.6 shows a second embodiment of a control arrangement in accordance with the invention; Fig. 7 shows an address decoder for use in the control arrangement shown in Fig. 6.

Fig. 1 showsschematicallya prior art control arrangement in which the measures in accordance with the invention can be advantageously used and which is partly formed by an integrated circuit 1. By way of example, let it be assumed that this integrated circuit is Applicant's IC TDA 3560 such as it is described in the Philips Data Handbook No. IC2 05-80, May 1980 and whose construction is only shown partlyforthe sake of clarity in Fig. 1.

This control arrangement has a pin 2 to which a luminance signal Y can be applied which is applied to the information signal-input 4(1, ) of a contrast control circuit4(1) via an amplifier 3. This contrast control circuit also has a control input 4(1,2) and a signal output 4(1,3). The control input4(1,2) is connected to a pin 5(1 ) to which an analogue contrast control signal CAwhich is generated by a contrast control signal source 6(1 )A is applied.

The control arrangement also has a pin 7 to which a chrominance information signal CHR can be applied which is thereafter applied to the information signal input4(2,1) of a coloursaturation-control circuit4(2) via an amplifier 51. The colour saturation control circuit has also a first control input 4(2,2), a second control input4(2,3) and a signal output4(2,4). The first control input 4(2,2) is connected to a pin 5(2) to which an analogue colour saturation control signal SA (= Saturation) which is generated by a colour saturation control signal source 6(2)A is applied. The second control input 4(2,3) is connected to the pin 5(1 ) and thus also receives the contrast control signal CA.

In addition to the connecting pins already mentioned there is another pin 5(3)to which an analogue brightness control signal BRA (= Brig htness), which is generated by a brightness control signal source 6(31A is applied, which brightness control signal is applied to a control input4(3,2) of a brightness control circuit 4(3).

The control arrangement shown in Fig. 1 further comprises a demodulatorcircuit8the input8(0) of which is connected to the signal output 4(2,4) of the control circuit 4(2) via a pin 9, a delay line 10 and a pin 11. This demodulator circuit 8 has three outputs 8(1), 8(2) and 8(3) at which the respective difference signals #Y,G-Yand R-Y occur. Each difference signal is applied to an addder 12 ( . ) of an adder arrangement 12 to which also the luminance signal Y is applied, which occurs at the signal output 4(1,3) of the contrast controlcircuit4(1).In responsetheretoadderarrangement 12 produces the blue colour signal B, the green coloursignal G and the red coloursignal R.These colour signals are each applied to a clamping circuit 13( . ) ofthe brightness control circuit4(3), in which the signal level occurring during the line blanking period (the blanking level) is clamped on a fixed value.

This fixed value is determined by the level of the brightness control signal BRAwhich is applied to the pin 5(3). The signals produced bythese clamping circuits 13( . )can be applied to the picture tube ofthe TVreceiverviapins 14,15,16.

As is shown in Fig. 1, in this control arrangement a capacitor 17 is connected to the pin 5(1) in parallel with the contrast control signal source 6(1)A. The voltage on the pin 5(1) is equal to the voltage across this capacitor 17 andthe lattervoltage is determined by the setting of source 6(1 )A. In practice it may happen thatthe contrast control signal source 6(1 )A is set such thatthe instantaneous value of one ofthethree signals B, G or R is so high,thatthis may result in excessive voltage being applied to the picture tu be. To counter actthis each clamping circuit 13( . ) has an additional output which is connected to the input of a peak-value detector 18.This detector produces an output current as soon as at the additional output of at least one of the clamping circuits there is a voltage which is higher than a predetermined threshold value. In practice this threshold value is 9 volts. The current produced bythis detector is applied via the pin 5(1) to the capacitor 17, which is discharged as a result thereof. This causes the voltage on the pin 5(1 ) to decrease and conse quently also the instantaneous value of each ofthe signals B, G and R.

So asto make the integrated portion 1 ofthe prior art control arrangementshown in Fig. 1 suitable for receiving optionally either analogue control signals or digital control signals this priorartcontrol arrangement can be modified in the manner shown in Fig. 2.

Then each pin 5( . ) is not directly connected to the control input4( . , 2) of the associated control circuit j ),butviaacommutationcircuitl9( . ).This commutation circuit incorporates a detection circuit 20( . ) the input of which is connected to the associated pin and produces an indication signal which is representative of the nature of the control signal applied tothe relevant pin. Let it be assumed that this indication signal is a two-level signal which has a value VO whenthe control signal is an analogue signal and a value when the control signal is a digital signal. This indication signal controls a switching arrangement21(.) which is shown only symbolically.

This switching arrangement has an information signal input 22( . ) which is also connected to the pin 5( . ); it furtherhastwooutputs23( . )and24( . )whichare connected directly and via an interface circuit 25( ), respectively, to the control input4( . ,2)ofthe associated control circuit4( . ).

As is shown schematically in the Figure, either a control signal source 6( . )Awhich produces an analogue control signal SA, BRA or CA, or a control signal source 6( . )D which produces a digital control signal SD, BRD or CD can be connected to the pin 5( . ).If now more specificallythe control signal source 6( . )A is connected to the pin 5( ) then the indication signal assumes the value as a result of which the analogue control signal is directlyapplied to the control input 4(.,2)of the control circuit4(.).via output 23(.) of the switching arrangement 6( . )D is connected to the pin 5( . ) then the indication signal assumes the value and the digital control signal is applied to the interface circuit 25( . ) via the output 24( . ) of the switching arrangement 21 ( . ).In the interface circuit this digital control signal is converted into an analogue control signal which can be processed bythe associated control circuit4( . ).

It should be noted thatthe interface circuit 25(1) cannot process the currentwhich may be produced by the peak-value detector 18 if a digital control signal is applied to the pin 5(1). In that case this peak value detector 18 will have to be put out of operation. This is symbolically shown in Fig. 2 by the switch 26 which is connected to the output of the peak-value detector 18 and is also controlled bythe indication signal produced bythe detection circuit 20(1). Then switch 26 is made conductive if the indication signal has the value VO and consequentlythe control signal source 6(1 )A is connected to the pin 5(1). Also nowthe capacitor 17, which is discharged bythe current produced by the peak-value detector 18 is arranged in parallel with this control signal source 6(1)A.If the indication signal has the value V1 then this signifies thatthe control signal source 6(1 )D is connected to the pin 5(1) and switch 26 is addjusted to the non-conducting state.

As in the case ofthe control circuit shown in Fig. 1, letitalso now be assumed forthe control circuit shown in Fig. 2 thatthe control signal source 6( .

which produces an analogue control signal (SA, BRA or Ca) is intheform of a potentiometer arrangement. For an adequate operation ofthe control circuit shown in Fig. this potentiometer arrangement is dimensioned such that its output voltage is located in afirstvoltage rangefrom, for example, 8 volts to approximately 11 volts. (In the known control circuitthis voltage range is from approximately 1 volt to approximately 4 volts).

The control signal source 6( . )D,which produces a digital control signal may be constructed in the manner shown in Fig. 3. It incorporates a clock pulse generator 27 which produces clock pulses at a rate of 5 to 10 Hz. Via a switch 28 these clock pulses are now applied to the output ofthe control signal source.

Switch 28 is operated by a control push-button 29 and conductswhen this control push-button 29 is oper ated. Switch 28 then allowsa number of clock pulses to pass,which number is proportional tothe period of time inwhichitconducts. If control push-button 29 is not operated, then switch 28 is non-conducting and no clock pulses appear at the output of said control signal source. The clock pulse generator 27 is dimensioned such thatthe clock pulses have a 0-and a 1-level which correspond to voltage values located in a second voltage range. The 0-level corresponds, for example, to a voltage of 0 volt and a 1-level to a voltage of 5 volts.

By ensuring thatthe output voltage of the (analogue) control signal source 6( . )A is located in a different voltage range then the output voltage of the (digital) control signal source 6( . )D, the detection circuit20( . ) which produces the indication signal may be in the form of a level detector. An embodiment thereof is shown in Fig. 4. It comprises two transistors 30 and 31, whose emitters are connected togetherto ground potential via a current source circuit 32. The collector of each of these two transistors is connected via a collector resistor33, 34to a battery 35, which produces a voitage of, for example, +12 volts. A voltage dividerformed bythetwo resistors 36 and 37 is arranged in parallel with this battery 35. These resistors have been chosen such that the voltage division point has a voltage of 7 volts.This voltage division point is now connected to the base of transistor 30. The input 38 of this detection circuit is connected to the base of transisto r 31 and the output 39 is connected to the collector of transistor 30. More specifically, the resistors 33 and 34 as well as the current I produced by the current source circuit 32 are dimensioned such thatthe transistors 30 and 31 act as a switch. This detection circuit 20( . ) now supplies at its output 39 an outputvoltage of V,=l 2 Volts when the input voltage exceeds 7 volts. In contrast therewith it produces an output voltage of V1 =7 volts when its input voltage is less than 7 volts.

Theclockpulseswhicharetransmitted bythe switch 28 (Fig.3) are applied to the interface circuit 25( . ) viathe switching arrangement 21 ( . ) (Fig.2). An embodiment of the interface circuit is shown in Fig. 5.

It comprises a counting circuit 40 to which the said clock pulses are applied. The counting position of the counting circuit is applied via parallel outputs (one bit per output) to a digital-to-analogue converter 41, which supplies at its output a voltage which is proportionalto this counting position. The counting circuit 40 has a memory function so that a given counting position is not lost and the digital-to- analogue converter 41 continuously produces the same output voltage as long as the push-button 29 is not operated.

The control arrangement shown in Fig. 2 incorporatesthree separate control signal sources 6( .

which are each connected to the associated connect ing pin via its own conductor. Fig. 6 shows an embodimentofacontrol arrangementin all the control signals are generated by a central control signal source 42 which, in accordance with the mannerdescribed in the United Kingdom Patent Application No.2,053,539 A may be in the form of a microprocessor with a keyboard connected thereto. In the embodiment shown two lines, namely a data line 43 and a clock line 44 are connected to this central control signal source. The central controlsignal source produces all the control signals and applies them bit-sequentially and consecutively to the data line 43.It applies clock pulses to the clock line 44 at a rate which is the same as the rate at which the bits of the control signals occur at the data line. This clock line renders the central control signal source suitable for connection to what is commonly referred to as a sequential system bus.

Each control signal produced by the central control signal source is formed by an address code followed by a number of information bits which themselves are followed by a stop sign. The address code indicates for which of the control circuits the subsequent information bits are intended. The stop sign indicates that at that instant no further bits are presentforthe selected control circuit.

As shown in Fig. 6, the data line 43 is connectable to the pin 5(2) and the clock line is connectable to the pin 5(3). These two pins are also in this case connected to the input 22( . ) of the switching arrangement21 ( . ), which is now also controlled bythe indication signal produced by the indication circuit 20( . ). The output 23( . ) of this switching arrangement is again connected directly to the control input 4( . , 2)of the associated control circuit 4( . ), more specifically to the colour saturation control circuit 4(2) and the brightness control 4(3). Output 24(2) of switching device 21 (2) is connected to the input 45(1) of a switching arrangement 45, which is only shown symbolically. It has an inactive terminal 45(2) and three signal output terminals46(. ).Each signal output46( . ) is connected to the control input 4( .2) of the associated control circuit 4( . ) viathe associated interface circuit 25( . ).

Switching arrangement 45 is controlled by a code detector47 which has a data input47(1) which is connected to the output 24(2) of the switching device 21 (2). It also has a clock input 47(2) which is connected to the output 24(3) ofthe switching device 21(3). This code detector 47 is of such a construction that it can detect, for example, four code words, namely three address codes A, B and C and the stop signal D. If more specifically the stop sign is received, then the switching device 45 is adjusted to the inactive condition. This inactive condition issymbolised by connecting the input45(1) of the switching device to the inactive outputterminal 45(2).When add ress code A is received then the input of the switching arrangement 45 is connected to the signal output46(1), on receipt of address code B this input is connected to the signal output 46(2), while on receipt of address code C the input 45(1) is connected to the signal output 46(3).

As can be seen from Fig. 6 the control arrangement shown therein has the considerable advantage that it is not necessary to make the peak-value detector 18 inoperative when the control signals are digital signals, it is also now not necessary to apply a digital control signal to the pin 5(1). As a consequence thereof, capacitor 17 may now be permanently connected to the pin 5(1).

The code detector 47 may be of a construction as shown schematically in Fig. 7. It comprises a shift register 48 in which the bits occurring at the input47(1) are written and shifted underthe control ofthe clock pulses occurring at the clock input 47(2). Four comparison circuits 49t . ) to each of which a comparison-addresscodeA, B, ar D is applied areconneced to this shift register 48. These comparison address codes are stored in memories 50( . ). If the content of the shift register 48 corresponds to a comparison address code, then the associated comparison circuit produces an output signal which connects the input 45(1) of switching arrangement 45 to that output 45(2) or46( . ) which corresponds to this address code.

a) As is shown already in the embodiment of Fig. 6 it is alternatively possible to control all the switching devices 21 ( . ) used in the control arrangement shown in Fig. 2 by one and the same detection circuit, for example detrection circuit 20(2).

b) In theforegoing it has been tacitly assumed that the counting circuit40 which is used in the interface circuit25( ) is formed by a modulo-N counter. It is, however, alternatively possible to use an up/down counter having an counting input and a down counting input.

If such a counting circuit is used in the control arrangementshown in Fig. 6, then the switching arrangement 45 must be of such a construction that it has for each up/down counter an output which is connected to the uFcounting input and an output which is connected to the down-counting input, these outputs being individually addressable.

Claims (10)

1. Acontrol arrangementforcontrolling at least one adjustable quantity of an information signal, comprising: a) at least one control circuit having an informa tion signal inputfor receiving an information signal and a control input; b) means for receiving a control signal; c) firstmeansforcouplingthecontrol inputofthe control circuit to the control signal receiving means; characterized in that d) a detection circuit is provided which is con nected to the control signal receiving means and produces an indication signal which is representative oftheform (analogueordigital) ofthe control signal; e) said first means comprises first switching means controlled bythe indication signal and has e.1 an input connected to the control signal receiving means;; e.2 a first output connected to the control input of the control circuitforapplying said control signal to the control inputwhen the control signal is in a first of its forms; e.3. a second output; f) second meansforcouplingthe second output of thefirstswitching means to the control input of the control circuitfor applying said control signal to the control inputwhen the control signal is in a second of its forms.

2. Acontrol arrangement as claimed in Claim 1, characterized in thatthe said second means incorpo rate a cascade arrangement of a memory and a digital-to-analogue converter.

3. A control arrangement as claimed in Claim 2, characterized in thatthe memory is in the form of a digital counting circuit.

4. Acontrol arrangement as claimed in Claim 2, characterized in that between the cascade arrange ment and the second output ofthefirst switching 5 means second switching means are provided controlled by the output signal of an address decoder the input of which is coupled to the control signal receiving means.

5. A control arrangement as claimed in Claim 4, characterized in thatthe second switching means has two or more outputs, to each of which a cascade arrangement of a memory and a digital-to-analogue converter is connected, whilethe output of each cascade arrangement is connected to the control input of an associated control circuit.

6. A control arrangement as claimed in anyofthe preceding Claims, characterized in thatthe detection circuit is in the form of a level detector.

7. Acontrol arrangement as claimed in any of the preceding Claims, characterized in that connected to the control signal receiving means there is a control signal source in the form of a potentiometer arrange- mentwhich produces an output signal whose level is located in a first range.

8. Acontrol arrangement as claimed in any of the preceding Claims, characterized in that connected to the control signal receiving means there is a control signal source which isintheform of a digital signal sourcewhich producesanoutputsignalconsisting of a sequence of "0" and "1" pulses whose levels are in a second range.

9. A control arrangement as claimed in Claim 7 or 8, characterized in that the control signal source incorporates a microprocessor which at its output repeatedlyproducesanaddresscodefollowed bya number of information bits.

10. A control arrangement substantially as herein described with reference to Figures 2 to 7 of the accompanying drawings.