GB2117519A

GB2117519A - Detecting cigarette packets

Info

Publication number: GB2117519A
Application number: GB08305883A
Authority: GB
Inventors: Athanasios Papaphilippopoulos; Peter Shawyer
Original assignee: Molins Ltd
Current assignee: Mpac Group PLC
Priority date: 1982-03-05
Filing date: 1983-03-03
Publication date: 1983-10-12
Also published as: GB2117519B; GB8305883D0

Abstract

In a detector control circuit for checking that components of cigarette packets, for example duty stamps, are present and correctly positioned, the output from a detector (36) is continuously monitored through a portion of the machine cycle in a circuit comprising two bistable elements (43, 44). Failure to detect a normal signal at any time within said portion of the machine cycle causes a change of state in the element (43), resulting in a fault signal being generated. This may be applied to a device (49) which rejects faulty packets downstream of the detector. <IMAGE>

Description

SPECIFICATION Detecting cigarette packets in cigarette packing machines and wrapping machines detectors are arranged to inspect the presence and correct positioning of various components within each interval required for the production of one packet - termed a machine cycle. Such components may be, for example, foil wrappers, card blanks or duty stamps at various stages of assembly in a hinged lid packing machine.

In known arrangements a signal generated by a detector (a detector signal) is examined at a precise predetermined instant within each machine cycle by means of an adjustable timing cam, or by means of a rotating potentiometer. In order for such a system to work correctly the component of interest must be passing the detector when the detector signal is being examined. In practice this has involved a considerable amount of time and effort in setting up the detector, and has placed restrictions on the resolution of the systems such that high resolution detectors could not usefully be employed.

It is an object of the present invention to reduce the dependency on timing signals and reduce the setting up procedure.

According to the present invention there is provided a method of detecting a component of a succession of cigarette packets in which one packet is produced during each machine cycle, comprising the steps of generating a detector signal relating to the component of each packet and having respective conditions indicative of a satisfactory component or of a defective component; setting a storage device to a first state at the start of an active period; setting a storage device to a second state on detecting a predetermined one of said conditions at any time during the active period; interrogating the storage device at the end of the active period; and producing an output signal if the storage device is in a predetermined state when said storage device is interrogated.

The active period is a part of each machine cycle during which the detector signal is monitored, the condition of the detector signal outside the active period being of no interest. The active period may consist of substantially all of the machine cycle but preferably consists of a part during which the component is passing the detector.

Preferably the predetermined condition is indicative of a satisfactory component and the storage device is set to the second state if the detector signal is in this condition at any time during the active period. On interrogating the storage device an output signal may be produced if the storage device has not been set to the second state.

According to a second aspect of the present invention there is provided an apparatus for detecting a component of a succession of cigarette packets in which one packet is produced during a machine cycle, comprising a detector for generating a detector signal relating to the component of each packet and having respective conditions indicative of a satisfactory component or of a defective component; means for setting a storage device to a first state at the start of an active period; means for setting the storage device to a second state on detecting one of said conditions at any time during the active period; interrogating means for interrogating the storage device at the end of the active period; said interrogating means including means for producing an output signal if the storage device is in a predetermined state when said storage device is interrogated.

In a preferred embodiment the apparatus also comprises means for switching between a first mode of operation and a second mode of operation. In said first mode of operation the storage device is set to the second state if the detector signal is in the condition indicating a satisfactory component, and the interrogating means may produce an output device if the storage device has not been set to the second state when said storage device is interrogated. In said second mode of operation the storage device is set to the second state if the detector signal is in the condition indicating a defective component, and the interrogating means may produce an output signal if the storage device has been set to the second state when said storage device is interrogated.

Preferably, means are provided for applying a reset pulse to the storage device at the start of the active period for setting the storage device to the first state and preferably means are also provided for applying a clock pulse to the interrogating means at the end of the active period to initiate the interrogation of the storage device. In a preferred arrangement the reset pulse and the clock pulse are produced in response to a timing pulse; the reset pulse may be produced by means for modifying the timing pulse and the clock pulse may be produced by delaying the timing pulse.

Preferably means are also provided for rejecting defective packets comprising a rejection device, and means for delaying the output signal and operating the reject device when the defective packet is in a co-operating position.

The invention will now be described, by way of example only, with reference to the accompanying figures in which: Figure 1 shows a diagrammatic representation of a detector for detecting the presence and correct positioning of a foil wrapper surrounding a bundle of cigarettes before the bundle is enclosed in a hinged lid packet, Figure 2 shows a circuit for use with the detector of Figure 1, Figure 3 shows a detector for detecting duty stamps applied to hinged lid packets, and Figure 4 shows a circuit for use with the detector of Figure 3.

In Figure 1 there is shown a part of a hinged lid packing machine in which a cigarette bundle 1 is wrapped in a foil wrapper 2 and is then conveyed to a station 4 where the bundle is enclosed in a hinged lid packet. In order to detect bundles which do not have a foil wrapper (or which have a displaced wrapper) a flap 5 on each wrapper passes under a detector 6, for example a metal detector of known design.

A logic circuit 7 receives a detector signal from the detector 6 and activates an output device 8 if the detector signal does not indicate the presence of a wrapper during each machine cycle. The logic circuit receives a timing pulse at a non-critical instant in each machine cycle from a proximity probe 9.

The logic circuit 7 is shown in Figure 2 and consist of two D-type bistables 11 and 12 (for example, Model MC 14013B supplied by Motorola Semiconductors of East Kilbride, Scotland, or their equivalents) and associated timing and indicating circuitry.

The operation of the bistables is as follows: on applying the rising edge of an electrical pulse to a clock input C1, C2 the signal level (high or low) applied to a data input D1, D2 is transferred to a Q output Q1, Q2, and the complimentary level is transferred to an inverted Q' output Q'1, Q'2. A high level applied to a set input S1, S2 sets the Q output high and the Q' output low, and a high level applied to a Reset input R1, R2 resets the Q output low and the Q' output high.

On detecting a foil wrapper the detector 6 applies a high level to the clock input of C1 of bistable 11. The data input is permanently tied to a supply rail + V (applying a voltage substantially equal to a high signal), therefore on receiving said detector signal at the clock input C1, output Q1 is set high and the inverted output Q'1 is set low. The timing pulse from the proximity probe 9 is applied to a pulse modifying circuit 13, consisting of a low pass filter, a Schmitt trigger and a monostable, which forms a sharp positive clock pulse of 2 milliseconds (ms) duration.

The clock pulse is applied to the clock input C2 of bistable 12, thus transferring the signal applied to the data input D2 of bistable 12 to the output Q2 of that bistable. If a foil has been detected Q'1 will be low and therefore Q2 will be low when bistable 12 is clocked. Bistable 12 therefore interrogates the Q' 1 output of bistable 11.

The clock pulse generated by the pulse modifying circuit 13 is inverted by an inverter 14 producing a negative pulse of 2 ms. This is applied to a monostable 15 which generates a second positive pulse of 2 ms when it receives the rising edge of the negative pulse. The second positive pulse is applied to the reset input R1 (of bistable 11) 2 ms after the clock pulse has been applied to the clock input C2 of bistable 12. This resets the inverted output Q'1 of bistable 11 high until foil is detected by the detector 6. If foil is not detected before a clock pulse is applied to the clock circuit C2 of bistable 12, the output Q2 will go high.

The output Q2 of bistable 12 is applied to the indicating device 8 (activated when Q2 is high) and may also be applied to a drive control circuit 16, via a diode 17; the control circuit stopping the machine when Q2 is high. Alternatively, or in addition, the inverted output Q'1 from bistable 11 may also be applied to a data input D6 of a shift register 19, via a diode 20, which is incremented by clock pulses applied to a clock input C6. The shift register activates a rejection device 21 when a defective packet is in a co-operating position.

Diode 17 and diode 20 allow other similar outputs to be wired together in an "OR" configuration to the drive control circuit 16 and the shift register 19 respectively. Once a missing foil has been detected, and the machine has stopped, the fault is rectified and a reset signal is applied to the reset input R2 of the second bistable 12 by closing and then releasing a switch 22. The set inputs S1 and S2 of bistables 11 and 12 are tied to a supply rail - V (applying a voltage substantially equal to a low signal).

Preferably a plurality of detectors with similar associated circuitry are included on the machine; each circuit then receives the same timing pulse at a suitable position in the machine cycle, thus eliminating the need for individual timing devices for each detector.

Other examples of detectors where this circuit may be employed on hinged lid packing machines are: an ends detector, which detects a complete bundle of cigarettes before they are wrapped in foil; an end of foil detector, which detects the foil as it is wrapped around the cigarettes; a blank detector, which detects cardboard blanks before a bundle of cigarettes is applied; a blank edge detector, which detects movement of the cardboard blank as it is wrapped around the bundle.

The construction of the detectors may vary (for example, mechanical, optical, or electro-magnetic), but each gives an output which may be in one of two possible states.

Figure 3 shows an apparatus for applying duty stamps to hinged lid packets and a detectorfor detecting the presence of such stamps. Stamps 30 are stored between supports 31 and are removed singly by a roller 32. Glue is applied to a stamp, while held on the roller 32, by a gluing roller 33 before the stamp is applied to a packet 34. A packet 35 then passes under a detector 36 which supplies a signal to a logic circuit 37. If the signal supplied to the logic circuit indicates that a stamp is not present on the packet, a fault is indicated by a device 38.

The detection of stamps is usually very difficult if the background colour of the stamp is similar to that of the unstamped packet. To overcome this problem a high resolution detector is employed (for example, a Visolux RL4 detector supplied by Warner Electrics Ltd., of County Durham, England) which is capable of detecting printing on the duty stamp. The detector consists of a light source and a light detector which are focussed onto a small area at a fixed focal length.

Packets must therefore pass the detector at said focal length for satisfactory operation, unlike low resolution detectors as previously described. A circuit for use with such a detector is shown in Figure 4.

The circuit of Figure 4 includes two D-type bistables 43 and 44 similar to bistables 11 and 12 shown in, and described with respect to, Figure 2. In a first mode of operation the output of the detector 36 is required to be high when printing on the stamp is detected; therefore said output may be inverted by an inverter 40 selectable by a switch 41. The inverted or non-inverted output is then amplified by an amplifier 42 and applied to the clock input C3 of bistable 43. The data input is tied to a supply rail + V (at a voltage substantially equal to a high signal) therefore on receiving a high signal from the amplifier 42 the Q3 output of bistable 43 goes high. The Q3 output is applied to the data input D4 of bistable 44 which transfers this signal to its Q4 output when a clock pulse is received at C4.

Atiming pulse is generated by a proximity probe 45 and is applied to a first pulse modifying circuit 46 similar to circuit 13 of Figure 2. The output from the first pulse modifying circuit 46 is applied to a second pulse modifying circuit 47 which produces a positive pulse of very short duration on receiving a rising edge. This pulse is applied to the reset input R3 of bistable 43.

The output from the first pulse modifying circuit 46 is also applied to an inverter 48 producing a negative pulse, the rising edge of which provides a clock pulse to the clock input C4 of bistable 44. Bistable 43 is reset before bistable 44 interrogates it, therefore a stamp must be detected between resetting bistable 43 and clocking bistable 44; the active period is therefore not necessarily the whole of the machine cycle. If a stamp is not detected during the active period bistable 43 is not set and bistable 44 is also not set when a clock pulse is applied to its clock input C4. The Q4 output of bistable 44 will therefore be low, which is applied as an active low to a reject device 9 thus rejecting the defective packet. Device 38 consists of a light emitting diode and a resistor connected between the Q'4 output of bistable 44, and the + V supply rail.The light emitting diode is constantly illuminated in normal operation (when Q'4 is low) and is not illuminated when Q'4 is high thus indicating a fault.

The inverted output Q'3 is applied to a data input D5 of a logic circuit 50, which detects three defective packets out of a consecutive series of 5, and activates a second fault indicating device 51 (similar to device 38) if such a condition exists. The logic circuit 50 consists of a one bit shift register and a five input majority logic gate (for example model MC14530B, supplied by Motorola Semiconductors).

Signals received from the inverted output Q'3 of bistable 43 (high indicating a missing stamp) are sequentially clocked through the shift register when it receives the rising edge of a clock pulse applied to a clock input C5 from inverter 48. Such signals sequentially appear on each of five parallel lines which connect the shift register to the majority logic gate, the lines therefore apply five consecutive signals to the majority logic gate. An output Z of the logic circuit 50 is high if less than three of the lines are high, and low if three or more of the lines are high indicating a serous fault condition. When the output Z of the logic circuit 50 is low the indicating device 51 is illuminated and the machine may be stopped while appropriate action is taken.The logic circuit 50 is reset by a switch 52 which momentarily connects a reset input R5 to the + V voltage supply rail.

A second switch 53 connects the reset input R5 of the logic device 50 and the set input 54 of bistable 44 to the + V voltage supply rail. This switch is applied to disable the circuit when not required, for example when duty stamps are not being applied. The set input S3 of bistable 43 and the reset input R4 of bistable 44 are tied to a supply line - V applying a voltage substantially equal to a low signal.

In a second mode of operation the packet is printed with an area having a different colour (termed a colour marker) from the rest of the packet, and a duty stamp is applied over the colour marker.

The circuit is therefore required to detect a colour marker and take the necessary action. Switch 41 is positioned so that a high output is produced when the colour marker is detected and switch A (consisting of two ganged contacts 55 and 56) is moved into the up position.

In this mode of operation bistable 43 is not set when duty stamps are present and a high signal from the inverted output Q'3 is applied to the data input D4 of bistable 44. On detecting a colour marker, bistable 43 is set and a low is applied to the data input D4 of bistable 44. All other functions of the circuit are the same as for the first mode.

The circuit of Figure 4 may also operate in a third mode by moving a switch B (consisting of ganged contacts 57, 58, 59, 60) into the up position while switch A is in the position shown. In this third mode the output from the detector is examined at an instant. The detector signal is supplied to the data input D3 of bistable 43 and the C3 input is clocked by the output of the pulse modifying circuit 46. The reset input R3 of bistable 43 is not required in this mode and is tied to the - V supply rail.

If the detector signal is low (indicative of a fault) when it is clocked, output Q3 of bistable remains low and applies a low to the data input D4 of bistable 44.

Bistable 44 is clocked 2 ms after bistable 43, the output Q4 goes high and the inverted output Q4 goes low indicating a fault condition.

Claims

1. A method of detecting a component of a succession of cigarette packets in which one packet is produced during a machine cycle, comprising the steps of generating a detector signal relating to the component of each packet and having respective conditions indicative of a satisfactory component or of a defective component; setting a storage device to a first state at the start of an active period; setting the storage device to a second state on detecting one of said conditions at any time during the active period; interrogating the storage device at the end of the active period; and producing an output signal if the storage device is in a predetermined one of said states when said storage device is interrogated.

2. A method according to claim 1 in which the storage device is set to the second state if the detector signal is indicative of a satisfactory component.

3. A method according to claim 2 in which an output signal is produced if the storage device has not been set to the second state when said storage device is interrogated.

4. Apparatus for detecting a component of a succession of cigarette packets in which one packet is produced during a machine cycle, comprising a detector for generating a detector signal relating to the component of each packet and having respective conditions indicative of a satisfactory component of a defective component; means for setting a storage device to a first state at the start of an active period; means for setting the storage device to a second state on detecting one of said conditions at any time during the active period; interrogating means for interrogating the storage device at the end of the active period; said interrogating means including means for producing an output signal if the storage device is in a predetermined one of said states when said storage device is interrogated.

5. Apparatus according to claim 4 in which the storage device is set to the second state on detecting the condition of the detector signal indicative of a satisfactory component.

6. Apparatus according to claim 5 in which the interrogating means produces an output signal if the storage device has not been set to the second state when the storage device is interrogated.

7. Apparatus according to claim 5 or claim 6 further comprising means for switching to a second mode of operation in which the storage device is set to the second state on detecting the condition of the detector signal indicative of a defective component; and the interrogating means produces an output signal if the storage device has been set to the second state when said storage device is interrogated.

8. Apparatus according to any of claims 4to 7 including means for producing a clock pulse and means for applying said clock pulse to the interrogating means to initiate the interrogation of the storage device.

9. Apparatus according to any of claims 4 to 8 in which the means for setting the storage device to a first state includes means for producing a reset pulse and means for applying said reset pulse to the storage device.

10. Apparatus according to claim 9 when dependant on claim 8 including means for generating a timing pulse and means for producing the clock pulse and the reset pulse in response to the timing pulse.

11. Apparatus according to claim lOin which the means for producing the clock pulse includes delay means for delaying the timing pulse.

12. Apparatus according to any of claims 4 to 11 further comprising a rejection device for rejecting defective packets; and a shift register means for delaying the output signal and activating the rejection device.

13. Apparatus according to any of claims 4to 12 in which the storage device is a first D-type bistable and the detector signal is applied to the clock input of said D-type bistable.

14. Apparatus according to claim 13 in which the interrogating device is a second D-type bistable and a signal from the first D-type bistable is applied to the data input of the second D-type bistable.

15. Apparatus according to any of claims 4to 14 including means for activating a warning device if a first predetermined number of defective components are detected out of a second predetermined number of consecutive packets.

16. Apparatus according to claim 15 in which the warning device is activated if three defective packets are detected out of five consecutive packets.

17. Apparatus according to claim 15 or claim 16 in which the warning device includes a first light emitting diode.

18. Apparatus according to any of claims 4 to 17 in which the output signal prevents a second light emitting diode from being illuminated.

19. Apparatus according to any of claims 4 to 18 including means for selectiveiy inverting the detector signal.

20. A method substantially as described herein with reference to Figures 1 and 2, and Figures 3 and 4.

21. Apparatus substantially as described herein with reference to Figures 1 and 2, and Figures 3 and 4.