GB2116403A - Improvements relating to digital data transmission - Google Patents
Improvements relating to digital data transmission Download PDFInfo
- Publication number
- GB2116403A GB2116403A GB08301742A GB8301742A GB2116403A GB 2116403 A GB2116403 A GB 2116403A GB 08301742 A GB08301742 A GB 08301742A GB 8301742 A GB8301742 A GB 8301742A GB 2116403 A GB2116403 A GB 2116403A
- Authority
- GB
- United Kingdom
- Prior art keywords
- bits
- signals
- groups
- parity
- error checking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Error Detection And Correction (AREA)
Abstract
Data bits such as digital samples of a sound signal are supplemented by error checking bits. e.g. provided by a Parity Generator, and these error bits are used to carry additional data bits (Extra Data) very securely by using the additional data bits to modify groups of the parity bits by way of a Pattern Generator and Parity Modifier. The additional data may be 3-bit scale factors applying to groups of digitally companded samples. The modification is detectable and reversible and may be selective inversion of all bits in a parity bit group. At the receiving end the Data and Parity bits are conventionally treated in a Parity Checker whose output can be recognised as groups of un-modified (non-inverted) and modified (inverted) bits by a Pattern Recogniser, using majority logic so that recognition is not upset by occasional bit errors. The Pattern Recogniser thus recovers the Extra Data and enables the actual parity bits to be recovered via a Pattern Generator and Parity Check Modifier. These bits are used conventionally in relation to Corrective Action on the main Data. <IMAGE>
Description
SPECIFICATION
Improvements relating to digital data transmission
The present invention relates to an improved method of digital data transmission and an improved transmitter and receiver. The object of the invention is to enhance the data-carrying capacity by utilizing parity and other error checking signals also to carry information signals.
It is a further object of the invention to enable such supplementary information signals to be transmitted with a high degree of reliability.
For convenience, the present application refers simply to transmission of data. This may be transmission by transmission line, radio, optical fibre, etc. but may equally be transmission by a recording/playback process. The appended claims are to be interpreted accordingly. The medium whereby transmission takes place, i.e. any propagation or recording medium which involves delay and possible distortion, may be referred to as a channel.
When simple parity bits are added to data at the input to a channel and then checked afterwards, almost all the checks are correct if the channel contributes few errors to the data. It could be argued that the signalling capacity of the parity channel is then being wasted, as it is carrying very little information. The present invention proposes a general technique for using some of the information capacitiy of the parity channel, thereby increasing the overall efficiency of the data channel. The invention is defined in the appended claims.
Although described in terms of binary data, the principle can be applied directly to any digital data, for example data using a ternary or higher base number. Although described, in the example, in terms of simple parity check bits the invention can be applied to other error protection methods.
The invention will now be described in more detail, by way of example, with reference to the accompanying drawings, in which:
Figs. 1 (a) and 1 (b) are block diagrams of a conventional data transmission system and a system embodying the invention respectively,
Fig. 2(a) and 2(b) are schematic diagrams of the transmitter and receiver of a specific embodiment of the invention for use with a companded digital sound transmission system, and
Figs. 3(a) and 3(b) are schematic diagrams of the transmitter and receiver of a modified embodiment.
The technique is described in general terms by reference to Fig. 1. A conventional data channel with parity added at the input and checked at the output is shown in Fig. 1 (a). A failure of a parity check implies the need for corrective action which, in practice, depends on the nature of the data and channel.
In Fig. 1 (b) an extra data input is used to control a pattern generator; the patterns are distributed over several parity bits. The parity bits are then modified by the pattern before being transmitted. The modifier is, most simply, a modulo-2 ("exclusive or") sum of the parity and the pattern bit-by-bit. At the end of the channel a parity check is performed. In the absence of error this check would give, for example, all zeroes, but instead it now gives one of the patterns. The output of the checker is examined in a pattern recogniser where the nearest or identical pattern is converted back into extra data output. This pattern, corrected if necessary, is used to modify the output of the parity checker to restore its conventional significance.If because of channel errors, the pattern recogniser cannot give an equivocal decision about the extra data it may
itself signal the need for corrective action. When, under high error rate conditions, the wrong pattern is recognised the consequent modification of the parity check will provide false information.
Practical examples of an embodiment of the technique will now be given. They relate to the near-instantaneous companded system of digital sound transmission such as described in Croll,
M.G. Moffat M.E.B. Er Osborne, D. W. 1973, "Nearly-instantaneous digital compander for transmitting six sound-programme signals in 2.048 Mbit/s multiplex", Electron. Letters, 1973, 9, 14, pp 298-300. Sound signals are sampled at 32kHz and the samples are uniformly quantised to 14-bit accuracy. Consecutive groups of 32 coded samples are examined and scaled by a factor 1, 2, 4, 8 or 1 6 to give a 10-bit signal whilst preserving the long-term dynamic range.
This gives a saving in required channel bit-rate but it requires the scale factor for each group to be transmitted very reliably. This scale factor, one of five values, is conventionally coded as a threebit number with some unused states. In order to protect the data corresponding to the five most significant bits of the companded samples, a simple parity check is used on each sample (32 parity bits per group) or on pairs of samples (16 parity bits per group). In the embodiments of the present invention, these parity bits are used to signal the scale factor, which would otherwise be sent as additional data requiring good protection.
In all of Figs. 2(a) to 3(b), crosses are employed to symbolize exclusive or operations. All operations are represented schematically and are of a well-known nature in themselves. As is equally well known, they may be implemented by dedicated circuits or by use of a programmed microprocessor.
Referring to the transmitter shown in Fig. 2(a), a block 10 of 32x 10 bits is formed for transmission, in the known manner outlined above and the accompanying 3-bit scale factor is formed and latched in a register 11. In accordance with conventional practice, a 32-bit parity block would be formed in a register 12 solely by exclusive-or operations on the 5 most significant bits of each 10-bit sample in the block 10. However, in carrying out the invention,
Fig. 2(a) shows how 27 of the 32 parity bits at the input are modified in three groups of nine
according to the three bits of the scale factor. The
pattern for each extra data bit is nine parity bits
either all changed or all unchanged. In the output
decoder (Fig..2(b)) the parity check is performed
conventionally by performing exclusive or
operations on the 5 most-significant bits of each
sample in the received block 20 and then
exclusive-or'ing with the bits in the received parity
block 21. In a conventional system, all 32 outputs
from the block 21 would (in the absence of errors)
be all "O" or all "1" depending upon whether
even or odd parity were employed. However, in
performing the present invention, the three
groups of nine checks are gathered together in
majority logic gates 22 to give the scale factor
bits. This is the pattern recogniser. The nine-input
gates give an output according to which state is
held by five or more of their inputs.The result of
this pattern recognition, the three-bit scale factor,
is latched in a register 23 and is moreover used to
modify the appropriate three groups of nine parity
checks to give a conventional result, as indicated
by the exclusive-or operations on lines 24. The 32
parity bits are thus recovered in block 25 for use
in the conventional manner. It will be appreciated
that five or more of any particular group of nine
parity checks would need to fail (each due to 1, 3,
or 5 errors in the six bits tested) to give a wrong
scale factor, At low error rates this probability is
very low as indicated in the table below.
Figs. 2(a) and (b) show that the remaining five
parity bits could be used to provide further
signalling capacity using this technique, by
application of further data to inputs a to e.
The corresponding outputs 26 would be
applied to auxiliary data recovery circuits which
will provide parity correction signals on lines 27.
Alternatively, it would be beneficial to extend the
three majority logic gates 22 to have 1 0, 11 and
11 inputs and so use all the 32 parity bits. This
would give the greatest immunity to scale factor
error. In the case of the 10-input gate there may
be a situation with five inputs each way, this
corresponds to the 'possible corrective action'
shown in Fig. (b) and it would be clear in this
case that that particular bit in the scale factor is in
doubt. There may be application where this "no
mans' land" area of operation can be used to
monitor the behaviour of the channel and take
corrective action whether or not there is an even
number of inputs to the majority logic gates.The
preferred allocation of the scale factor three-bit
codes to the five factors, and of the gate outputs
to the bits of these codes, can be selected so as to
yield best results, without affecting the principle
of the invention.
Figs. 3(a) and (b) show similar diagrams where
there are 1 6 parity bits each protecting the five
most significant bits of a pair of samples. In this
case, there are three groups of five parity bits
used to send and recognise the pattern, and the
immunity to scale factor error is reduced as each
check is more likely to fail and only three failures
in five are needed to alter the majority. Again there is possible advantage to be gained by using one 6-input gate to take advantage of 1 6 parity bits.
The computed failure rates of the two systems as drawn are given below. It is clear that at random bit error rates at which the sound samples themselves are not significantly degraded (i.e. less than about 10-9) the scale factor failure rate is insignificant.
Random Wrong scale factor code channel bit rate error rate Figure 2 Figure 3 10-2 1.9x10-4 2.4x10-2 10-3 3 x10-9 4 x10-5 10-4 3 x10-14 4 x10-8 10-5 3 x10-19 4 x10-" The technique for signalling in parity as described above could find many applications particularly where a small amount of wellprotected additional data needs to be sent.The example of the companding scale factor detailed above is of immediate relevance to broadcasting; other potential applications include the control of digital multiplexers, in particular framing and adjusting for different bit rates ("bit stuffing").
In the case of binary data the invention can be seen to reside in a data transmission system transmitter and receiver. In the transmitter a group of error checking bits is used to transmit a supplementary data bit by leaving the group of bits unchanged for one supplementary bit value and subjecting the group to a predetermined, detectable and reversible transformation for the other supplementary bit value. In the specific case of a group of parity bits, the transformation can be inversion of all parity bits within the group.
At the receiver the group of bits is tested to ascertain whether or not the transformation has been applied. Specifically it is determined whether the majority of parity bits give a false or true parity check. The supplementary bit value is thus determined and the normal error checking and/or correcting procedures are applied on the basis of the received group of bits when it is determined that the transformation has not been applied and on the basis of the received group of bits subjected to the reverse (inverse) transformation when it is determined that the transformation has been applied.
Examples of transformations of the error checking signals have been given with reference to Figs. 2(a) to 3(b) but there are naturally many other possibilities. One advantageous example is to use distanced codes as the second digital information signals, for example the six codes described in our copending application 8226590 (Serial No ) may be transmitted by enclusive or'ing with the 1 6 parity check bits. This gives full "majority of nine" benefit as explained in the said application when only 1 6 signalling bits are available.
Claims (10)
1. A method of transmitting digital data wherein first digital information signals are processed to derive error checking signals, groups of the error checking signals are selectively subjected to at ieast one predetermined, detectable and reversible transformation in dependence upon second digital information signals, and the first digital information signals
are transmitted accompanied by the selectively transformed error checking signals.
2. A method according to claim 1, wherein the transmitted signals are received, the selective transformations are detected to recover the second digital information signals, the error signals are selectively subjected to reverse transformation in dependence upon the detected transformations to recover the original error checking signals, and error checks are carried out in accordance with those error checking signals in conjunction with the first digital information signals.
3. A method according to claim 1 or 2, wherein the data is binary data and the or each reversible transformation consists in forming an exclusive or function between a group of bits of the first digital information signals and a predetermined pattern of bits.
4. A method according to claim 3, wherein the predetermined pattern is all ones, whereby the transformation consists in bit-wise inversion of the bits of the said group.
5. A method according to claim 3 or 4, wherein the received data and error checking signals are processed in accordance with the algorithm upon which the error checking is based to recover groups of bits which, in the absence of errors introduced during transmission, will possess a first predetermined pattern if not subject to transformation before transmission and will possess a different predetermined pattern for the or each transformation selectively effected before transmission, each recovered group of bits is assigned to that pattern to which it is closest, thereby to recover the second digital information signals, and errors are detected and/or corrected on the basis of any bit discrepancies between the recovered groups of bits and the patterns to which they are assigned.
6. A binary transmitter comprising means responsive to first binary data signals to form error checking bits, means responsive to second binary data signals to subject groups of the error checking bits selectively to detectable, reversible transformations, and means for transmitting the first binary data signals accompanied by the selectively transformed groups of error checking bits.
7. A transmitter according to claim 6, wherein the means responsive to the second binary data signals use each bit thereof to leave a corresponding group of error checking bits unchanged for one value of the said bit and, for the other value of the bit, to form an exclusive or function between the group of bits and a predetermined pattern of bits.
8. A binary data receiver for use with a transmitter according to claim 6, comprising means responsive to received binary data signals and error checking bits to form groups of
recovered bits, means for matching the groups of recovered bits with a plurality of predetermined patterns so as to assign each group to its closest pattern, means providing further binary data signals corresponding to the assignations of the groups, and means providing error detecting and/or correcting bits in accordance with any discrepancies between the groups of bits and the patterns to which they are assigned.
9. A method according to claim 1 or 2, wherein the first digital information signals comprise data using a ternary or higher base number.
10. A method according to claim 3, wherein a plurality of different patterns of bits are employed to transmit distanced codes as the second digital information signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08301742A GB2116403B (en) | 1982-03-01 | 1983-01-21 | Improvements relating to digital data transmission |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8205950 | 1982-03-01 | ||
GB08301742A GB2116403B (en) | 1982-03-01 | 1983-01-21 | Improvements relating to digital data transmission |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8301742D0 GB8301742D0 (en) | 1983-02-23 |
GB2116403A true GB2116403A (en) | 1983-09-21 |
GB2116403B GB2116403B (en) | 1985-10-23 |
Family
ID=26282115
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08301742A Expired GB2116403B (en) | 1982-03-01 | 1983-01-21 | Improvements relating to digital data transmission |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2116403B (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2146875A (en) * | 1983-09-09 | 1985-04-24 | Racal Res Ltd | Communications systems |
GB2177280A (en) * | 1985-05-09 | 1987-01-14 | British Broadcasting Corp | Digital data transmission |
GB2191913A (en) * | 1986-06-20 | 1987-12-23 | American Telephone & Telegraph | A multiplexing demultiplexing arrangement for a digital transmission system |
GB2243056A (en) * | 1990-04-11 | 1991-10-16 | Stc Plc | Repeater supervision |
WO1993012598A1 (en) * | 1991-12-11 | 1993-06-24 | Signal Processors Limited | Combination of two signals, the second appearing as a noise for the first one |
EP0569280A1 (en) * | 1992-05-06 | 1993-11-10 | Telediffusion De France | Method and system for transmission of a digital signal coded with N bits by an emitting and receiving interface for signal coded with N+M bits and utilisation in digital television |
GB2281179B (en) * | 1993-08-18 | 1998-03-11 | Roke Manor Research | Apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit |
EP0898429A2 (en) * | 1997-08-16 | 1999-02-24 | Deutsche Telekom AG | Measuring method and device for evaluating digital transmission systems |
WO1999027674A1 (en) * | 1997-11-20 | 1999-06-03 | Ericsson, Inc. | Method and apparatus using parity status for signaling |
WO2003017690A3 (en) * | 2001-08-20 | 2003-08-21 | Qualcomm Inc | Method and system for utilization of an outer decoder in a broadcast services communication system |
EP2398177A1 (en) * | 2010-06-21 | 2011-12-21 | Alcatel Lucent | Radio interface common reconfiguration |
EP2400682A1 (en) * | 2010-06-23 | 2011-12-28 | Robert Bosch GmbH | Method and device for a checksum modification and identifying a checksum modification |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7177658B2 (en) | 2002-05-06 | 2007-02-13 | Qualcomm, Incorporated | Multi-media broadcast and multicast service (MBMS) in a wireless communications system |
US8804761B2 (en) | 2003-08-21 | 2014-08-12 | Qualcomm Incorporated | Methods for seamless delivery of broadcast and multicast content across cell borders and/or between different transmission schemes and related apparatus |
US8694869B2 (en) | 2003-08-21 | 2014-04-08 | QUALCIMM Incorporated | Methods for forward error correction coding above a radio link control layer and related apparatus |
US7318187B2 (en) | 2003-08-21 | 2008-01-08 | Qualcomm Incorporated | Outer coding methods for broadcast/multicast content and related apparatus |
-
1983
- 1983-01-21 GB GB08301742A patent/GB2116403B/en not_active Expired
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2146875A (en) * | 1983-09-09 | 1985-04-24 | Racal Res Ltd | Communications systems |
GB2177280A (en) * | 1985-05-09 | 1987-01-14 | British Broadcasting Corp | Digital data transmission |
GB2191913A (en) * | 1986-06-20 | 1987-12-23 | American Telephone & Telegraph | A multiplexing demultiplexing arrangement for a digital transmission system |
GB2191913B (en) * | 1986-06-20 | 1990-08-22 | American Telephone & Telegraph | Digital block multiplexer, demultiplexer, and digital transmission systems |
GB2243056A (en) * | 1990-04-11 | 1991-10-16 | Stc Plc | Repeater supervision |
GB2243056B (en) * | 1990-04-11 | 1994-03-30 | Stc Plc | Repeater supervision |
WO1993012598A1 (en) * | 1991-12-11 | 1993-06-24 | Signal Processors Limited | Combination of two signals, the second appearing as a noise for the first one |
EP0569280A1 (en) * | 1992-05-06 | 1993-11-10 | Telediffusion De France | Method and system for transmission of a digital signal coded with N bits by an emitting and receiving interface for signal coded with N+M bits and utilisation in digital television |
FR2691030A1 (en) * | 1992-05-06 | 1993-11-12 | Telediffusion Fse | A method and system for transmitting an N-bit coded digital signal over a N + M bit coded signal transmission-reception interface and their use in digital television. |
GB2281179B (en) * | 1993-08-18 | 1998-03-11 | Roke Manor Research | Apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit |
EP0898429A2 (en) * | 1997-08-16 | 1999-02-24 | Deutsche Telekom AG | Measuring method and device for evaluating digital transmission systems |
EP0898429A3 (en) * | 1997-08-16 | 2000-12-20 | Deutsche Telekom AG | Measuring method and device for evaluating digital transmission systems |
WO1999027674A1 (en) * | 1997-11-20 | 1999-06-03 | Ericsson, Inc. | Method and apparatus using parity status for signaling |
US6282685B1 (en) | 1997-11-20 | 2001-08-28 | Ericsson Inc. | Methods and apparatus for signaling using parity status |
WO2003017690A3 (en) * | 2001-08-20 | 2003-08-21 | Qualcomm Inc | Method and system for utilization of an outer decoder in a broadcast services communication system |
EP2136492A1 (en) * | 2001-08-20 | 2009-12-23 | Qualcom Incorporated | Method and system for utilization of an outer decoder in a broadcast services communication system |
US7787389B2 (en) | 2001-08-20 | 2010-08-31 | Qualcomm Incorporated | Method and system for utilization of an outer decoder in a broadcast services communication system |
JP2013085263A (en) * | 2001-08-20 | 2013-05-09 | Qualcomm Inc | Method and system for utilization of outer decoder in broadcast services communication system |
JP2015156669A (en) * | 2001-08-20 | 2015-08-27 | クゥアルコム・インコーポレイテッドQualcomm Incorporated | Method and system for utilization of outer decoder in broadcast services communication system |
EP2398177A1 (en) * | 2010-06-21 | 2011-12-21 | Alcatel Lucent | Radio interface common reconfiguration |
WO2011160769A1 (en) * | 2010-06-21 | 2011-12-29 | Alcatel Lucent | Radio interface common reconfiguration |
EP2400682A1 (en) * | 2010-06-23 | 2011-12-28 | Robert Bosch GmbH | Method and device for a checksum modification and identifying a checksum modification |
Also Published As
Publication number | Publication date |
---|---|
GB8301742D0 (en) | 1983-02-23 |
GB2116403B (en) | 1985-10-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB2116403A (en) | Improvements relating to digital data transmission | |
CA2003862C (en) | Error correction and detection apparatus and method | |
US6425107B1 (en) | Data encoder/decoder for a high speed serial link | |
CA2036545A1 (en) | Method and apparatus for detecting a frame alignment word in a data stream | |
EP0397385B1 (en) | Error correction method and apparatus | |
EP0280013B1 (en) | Device for verifying proper operation of a checking code generator | |
EP0729674B1 (en) | Cyclical redundancy check method and apparatus | |
EP0140381B1 (en) | Decoding method and system for doubly-encoded reed-solomon codes | |
US4688207A (en) | Channel quality monitoring apparatus | |
EP1183605B1 (en) | System and method for protecting data and correcting bit errors due to component failures | |
US20030095606A1 (en) | Method and apparatus for multi-level signaling | |
JPS58131843A (en) | Error correcting method and device | |
EP0230066B1 (en) | A method for decoding data transmitted along a data channel, and an apparatus for executing the method | |
MY112136A (en) | Method of converting a series of m-bit information words to a modulated signal,method of producing a record carrier,coding device,decoding device,recording device, reading device, signal, as well as arecord carrier | |
EP0864125A4 (en) | Data integrity and cross-check code with logical block address | |
GB1400363A (en) | Processing binary coded information | |
US4606028A (en) | Digital transmission system | |
US5093831A (en) | Fast calculation circuit for cyclic redundancy check code | |
US5371741A (en) | Method and arrangement of multiplexing serial data using wired-OR | |
US4109856A (en) | Method for transmitting binary signals | |
EP0291961B1 (en) | Method of and device for decoding block-coded messages affected by symbol substitutions, insertions and deletions | |
EP0453081B1 (en) | Information signal processing method and apparatus | |
US6718505B1 (en) | Method and apparatus for error correction in a process of decoding cross-interleaved Reed-Solomon code (CIRC) | |
US4453158A (en) | Method for encoding analog signals | |
JPS62285525A (en) | Method and apparatus for binary data processing |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
PE20 | Patent expired after termination of 20 years |
Effective date: 20030120 |