GB2115248A - Trimmable resistive scaling network suitable for digital to analog converters - Google Patents

Abstract

A trimmable resistive scaling network is described in the context of a digital-to-analog converter in which the higher order bit currents I1-I3 are binarily divided in a main ladder, and the lower order bit currents I4-I7 are equiweighed sources divided in an R-2R ladder. The network (T.D.N.) includes at least one trimmable resistor RB, and is used to divide the output of the R-2R ladder in order to correct the ratio between the higher and lower order bits. <IMAGE>

Description

SPECIFICATION Trimmable resistive scaling network suitable for digital to analog converters This application is related to the copending application entitled "A Circuitfor Improving the Performance of Digital-to-Analog Converters," filed on even date herewith.

This invention relates generally to an improved resistive dividing or scaling network which may be trimmed to achieve either higher or lower scaling factors and more specifically, to a resistive dividing network useful in scaling the relative combinations of the higher and lower order bits in a digital to analog converter (DAC hereinafter).

In the past, integrated circuit DAC's have been configured with the higher order bits binarily divided in a main ladder and the lower order bits binarily divided in an output R-2R ladder. The bits are summed atan output node, such as shown in Figure 1, where Ii, 12 and 13 represent the higher order bit currents and 14-17 (and higher-not shown) represent equalcurrentsourceswhich are binarilydivided in the R-2R ladder sequence shown in Figure 1.

The current sources Ii - 17 are understood to betoggled by digitally-controlled bit switches (not shown).

Initially, the circuit is adjusted by a trim to set the 11/12/13 ratio as well as by an independent trim so that current sources 14-17.. . . make binarycontribution at the output. Such a procedure may often result in an incorrect ratio between the higher order bits Ii 13 and the lower order bits 14-17 .......

The lower order bit outputs usually are divided or scaled before summation with the higher order bits. A trimmable scaling or dividing network can be used to divide the entire output ofthe R-2R ladder without changing the binary division accomplished within the output ladder. The utility ofthistechnique is severaly limited ifthe trimming method (which conventionally adjusts resistorvalues upward) can only increase or only decrease the relative contribution ofthe lower order bits with respect to the higher order bits.

In the past, it was possible to build a DAC without using a R-2R ladder network by incorporating a quad current switch approach. In a quad current switch, four current sources and switches would be grouped together, with their currents scaled at a ratio of 8:4:2:1. In a 16-bit DAC, for example, there would be four quad current switches. The output of the first quad currentswitch would be coupled directlyto the DAC output. The second quad current switch output would be divided by 16, the third quad current switch output would be divided by 256, and the fourth quad current switch would be divided by 4096. The dividing network used to scale the respective quad current switches was comprised of a pair of resistors and was usuallytrimmable both up and down.For example, between the first and second quad current switches, the dividing circuit would be comprised of a firsttrimmable resistor of value Rand second trimmable resistor of value 1 5R, so asto achieve the 16:1 ratio between the first and secnd quad current switches. Between the second and third quad current switches, the dividing circuit was comprised of trimmable resistors having respective values Rand 255R. Between the third and fourth quad current switches, the dividing circuit networks was comprised oftrimmable resistors having a ratio of to 4095R.

The trimmable resistors in the dividing circuits weredifficultto build in the ratios of 1:15, 1:255 and 1 :40A5, and would change with age. In addition it was very difficult to trim the resistors (up and down) to get accurate sensitivity and resolution. As a result, the quad current switch approach has been supplanted by the R-2R ladder network. However a need existed to provide for modern DACs incorporating R-2R ladder networks, a trimmable scaling or dividing networkwhich both maintains the desired circuit impedance levels, allows independent trimming of the bit ratios, and can be trimmed to effect a relative increase or decrease of the lower order bit contribution at the output.

According to one aspect of the present invention there is provided a trimmable resistive scaling networkfor precisely adjusting a signal level at an outputterminal of a DAC,comprising in combination: first resistive means providing a first impedance coupled to a resistance ladder; first current source means coupled to said resistance ladderthrough said first resistive means; trimmable second resistive means coupled between said firstcurrent source means and analog ground, and trimmable third resistive means coupled between said first current source means at its coupling to second resistive means and said output terminal, said second and third resistive means controlling the relation between said current source means and said signal level.

According to another aspect of the present invention, there is provided in a digital to analog converter including an R-2R ladder network means for ratioing the contribution of a lower order bit generating means and separate higher order bitgenerating means, the improvement comprising resistive scaling means comprising first and second trimmable resistors for adjusting the relative contributions of the lower and higher order bits about a predetermined design center.

In accordance with one embodimentofthe invention, it is an object of this invention to provide an improved dividing network for a DAC.

It is another object of this invention to provide an improved dividing networkfor a DAC that allows the contribution ofthe lower order bits to be adjusted up or down with respect to the contribution ofthe higher order bits.

It is yet a further object of this invention to provide a simple scaling networkfor a DAC wherein the nominal values ofthe resistive components lie in a simple integral relationtotheresistorvaluesinthe R-2R ladder.

It is still another object of this invention to provide an improved scaling network wherein the trimmable resistors are configured for a match oftheir required resolution and range capabilities.

In accordance with one embodiment of this invention, a trimmable resistive scaling network suitable for use in a DAC and having the capabilityfor eigher reducing or enhancing the signal contributed bythe lower order bits is disclosed. In accordance with a more particular embodiment of the invention, there is disclosed a trimmable scaling networkfor a DAC wherein the trimmable resistors are configured for a match oftheir required resolution and range capabilities.

Embodiments of the invention will now be described, byway of example, with reference to the accompanying drawings, in which; Figure 1 is illustrative of a trimmable divider or scaler network for matching the relative contributions of higher order bits represented by II -- 13 and lower order bits 14-17 .......

Figure 2 shows details of a divider or scaler network with onetrimmable resistor which can reduce the relative contribution of the lower order bits.

Figure 3 illustrates a trimmable divider or scaler network comprising two trimmable resistors which may be adjusted to either increase or decrease the relative contribution of the lower order bits.

With reference to Figure 2, the trimmable resistor 4R in combination with fixed resistor 2R as components of the divider network serve to binarily scale approximately selected current sources I1 - 17 ......

at the output node as well as to reduce the relative contribution of the lower order bits by a trim of the resistor4R which increases its value. Because resistor 4R may only be increased in value by conventional trim techniques, its initial or nominal value must be lessthan 4R (relative to the resistor values in the R-2R ladder) byan amount which is roughly twice the expected tolerances in the nominal matches of the ladder resistors. This means that fairly large adjustments in the nominal 4R resistorwill be required even in the case where all the resistive components lie exactly on the design center.

Onewayto overcomethisdisadvantage is shown bythe embodiment of Figure 3. Here a first trimmable resistor RA shunts a portion of the bit currents 14- ...... to ground while trimmable resistor RB partially determines the fraction ofthe lower order bit currents which will be summed atthe output. The trimmable scaling network also comprises a third resistor having a nominal value 2R, i.e. the same as the resistors connected to ground in the R-2R ladder which binarilydividesthe lower order bit current sources. Since the impedance looking to the right from the 15 node is 2R, the fixed resistor in the trimmable network must have the same value in orderto make the contribution of i4 at the output twice as equal currentsource 15.

Trimmable resistors RA and RB maytake on a range of nominal discrete complementa ry values as shown in the following table: RA/R RB/R 112 4/9 312 12/11 2 4/3 3 12,7 4 2 infinity 4 The values of RA and R5 above are normalized by the nominal value of the resistors R in the R-2R ladder.The last case corresponds to the situation of Figure 2 with the disadvantages hereinbefore, of the other possible choices, the pair RAZOR = 4 and RB/R = 2 are the bestfor monolithic integration because the resulting values are low-order integral multiples both mutually and with respecttothe resistors in the R-2R ladder. Thusthe geometric layout ofthe resistors is simplified in thatthe lengths of the resistors may be simply doubled or quadrupled with a high confidence level of achieving the desired nominal ratios.

It may be shown in general (forthecomplementary pairs of values of RA and Rg above) that the output current is invariant when the following trim ratio is achieved: output change for percent change in RB = -1+RA output for percent change in RA 4R Thus for the case where RA = 4R, the trim sensitivity to RB is opposite to the twice as great as thatfor RA.

Thus the trim tab on RB is desirably designed fortwice the resolution and half the range (percent) as that on RA. This may be simply accomplished in the case RA/R = 4, RR = 2 by providing a fixed (untrimmed) portion of Rwith a value of Rand a trimmed portion of value R of identical configuration to each of four unit resistors in RA, SO that both RA and RB have equal absolute trim effects on the output.

While the invention has been particularly described with reference to preferred embodiments thereof, it will be understood by those skilled in the artthat the foregoing and other changes in form and details may be made therein without departing from the spirit and scope ofthe invention. For example, trimmable resistive scaling networks in accordance with the foregoing teaching may be used to set the ratios between more than two subjects of current sources and/or for applications otherthan DAC devices.

Claims (10)

1. Atrimmable resistive scaling network for precisely adjusting a signal level at an output terminal of a DAC, comprising, in combination: first resistive means providing a first impedance coupled to a resistive ladder; first current source means coupled to said resistance ladderthrough said first resistive means; trimmable second resistive means coupled between said first current source means and analog ground; and trimmable third resistive means coupled between saidflrstcurrent source means at its coupling to second resistive means and said output terminal, said second and third resistive means controlling the relation between saidcurrentsource means and said signal level.

2. Thenetworkofclaim 1, where said second resistive means has a nominal value of twice said third resistive means.

3. The network of claim 1 or claim 2, where said trimmable second resistive means and said trimm ably third resistive means have substantially equal absolute trim ranges.

4. In a digital to analog converter including an R-2R ladder network means for ratioing the contribution of lower order bit generating means and separate higher order bit generating means, the improvement comprising resistive scaling means comprising first and secondtrimmable resistorsfor adjusting the relative contributions of the lower and higher order bits about a predetermined design center.

5. The converter of claim 4,wheresaid firstand second resistors have values in a ratio of substantiallytwo to one.

6. Theconverterofclaim 5, where each of said first and said second resistors have a substantially two to one resistance ratio with one ofthe resistors in said R-2R ladder.

7. The converter of claim 4 or clai m 5, where said first and said second resistors cause substantially equal absolute effects in the output signal.

8. Theconverterofclaim Sorclaim6,wheresaid first resistor comprises a fixed portion and a trimmable portion, each of said portions having a substantially equal resistive value.

9. Atrimmable resistivescaling networksubstantially as hereinbefore described with reference to Figures 1,2 or3 of the accompanying drawings.

10. Means forratioing the contribution of lower order but generating means and separate higher order bit generating means in a digital to analog converter substantially as hereinbefore described with reference to figures 1,2 or 3 of the accompanying drawings.