GB2115240A - A.C. power supply control apparatus - Google Patents

Abstract

The power applied from an a.c. supply to one or more loads is controlled by phase-controlling a semiconductor switch such as a Triac so that, in each cycle or half-cycle of the supply waveform, the switch is on for a time dependent upon the amount of power to be applied to the load. Previously the or each switch has been controlled by an analog control device and, particularly where say a large number of loads are to controlled independently, the analog control devices have been controlled in turn by a computer. Herein is disclosed control apparatus wherein a microprocessor based computer system, is able to phase-control a series of load-power control switches directly in the sense that the control is not via an intermediate analog control device. To do this, the central processor unit of the computer system receives into an internal register a series of mask words indicative of switches to be turned on at different stages during each supply cycle or half cycle interspersed with time delay signals for timing out the respective stages. <IMAGE>

Description

SPECIFICATION Control apparatus This invention relates to apparatus for controlling the power applied to a load from an alternating supply by phase-controlling an electrically triggerable switch connected to the load and the supply.

More particularly but not exclusively the invention relates to apparatus for controlling the brightness of one or more electric lamps.

The brightness of an electric lamp fed from the a.c.

mains can be controlled by varying the instant, during each half cycle of the mains waveform, at which a semi conductor switch such as a Triac connected between the lamp and the supply is triggered. It is known to generate the triggering signals for the switch by an analogue trigger signal generating device, for example a device which taps off part of the mains supply, applies a user variable delay to this part and then applies this to the switch trigger terminal. Thus, the longer the applied delay, the later the triggering during each mains half cycle and the less bright is the lamp.

It is also known, particularly in the field of theatre and display lighting, to control a number even a very large number of lamps by means of a computer.

However, between the computer and the switches for the respective lamps there is provided an interface consisting of an appropriate number of digital to analogue converters and the aforementioned analogue trigger signal generating devices i.e. the computer does not control the switches directly but instead acts indirectly by controlling say the phase delay applied to the tapped off part of the mains waveform used to trigger each switch.

This form of interface makes a computer controlled lighting installation rather expensive. Accordingly one object of this invention is to provide lighting cpntrol apparatus for which such an interface does not necessarily have to be provided.

According to one aspect of the invention, there is provided control apparatus for controlling the power applied to a load from an alternating electrical supply by phase-controlling an electrically triggerable switch connected between the load and the supply, the apparatus comprising a phase-detector device for forming a series of timing signals at respective times when the supply is at a predetermined point in its waveform and a microprocessor Based computer system which includes a microprocessor unit having an internal storage register and which is operable for storing in said register a digital signal dependent upon the power required to be supplied to said load and for responding to a signal from said phase detector device to measure out an elapsed time period indicated by said stored signal and to then generate an output signal for initiating triggering of said switch.

According to another aspect of the invention, there is provided control apparatus for controlling the power applied to a load from an alternating electrical supply by phase-controlling an electrically triggerable switch connected to the load and supply, the control apparatus comprising supervisor circuit means which includes a phase-detector device for forming a series of timing signals at respective times when the supply is at a predetermined point of its wave form, and output signal producing means which includes a time measuring circuit operable for storing a digital signal dependent upon the power required to be applied to said load and for responding to each of said series of signals from said phase detector device to measure out an elapsed time period indicated by said stored digital signal and to then generate an output signal for initiating triggering of said switch.

Preferably said time measuring circuit is operable for storing a plurality of digital signals dependent upon the power required to be applied from said supply to a plurality of loads and for responding to each of said timing signals to measure out elapsed time periods indicated by the stored digital signals and to generate respective output signals for initiating triggering of respective electrically triggerable switches. In this case said time measuring circuit may be operable for measuring out in succession respective ones of a plurality of elapsed time periods indicated by respective ones of a plurality of stored digital signals and, when each period has been measured out, for generating one or more output signals for initiating triggering of one or more corresponding ones of a plurality of electrically triggerable switches.Advantageously, said time measuring circuit is operable for storing a plurality of further digital signals each indicative of one or more of said switches which are to be triggered following a respective one of said elapsed time periods, the time measuring circuit becoming responsive to the respective further digital signal following measuring out of each elapsed time period to generate output signals for initiating triggering of the switches indicated by that further digital signal.

Preferably said time measuring circuit comprises memory means for storing the or each digital signal and a microprocessor circuit programmed to receive the or each said digital signal and to perform said measuring out of the or each elapsed time period.

The microprocessor circuit may be programmed to receive from said memory means a plurality of digital signals in succession, to regard alternately received ones of said digital signals as being indicative of respective elapsed time periods and to measure out these periods by decrementing the signals and, after so measuring out each such period, to generate an output signal dependent upon the next received one of the other digital signals.

Advantageously, the microprocessor circuit is programmed to regard said memory means as a stack memory and the program for the microprocessor circuit comprises instructions to receive digital signals from successive memory locations indicated by a stack pointer register of the microprocessor and, each time, to increment the content of The drawing(s) originally filed was/were informal and the print here reproduced is taken from a laterfiledformal copy.

that register.

The said phase-detector device may comprise comparator means for comparing said supply with respective reference voltages substantially equis paced above and below zero volts, and signal shaping means for responding to the comparator means togenerate respective pulse signals prior to each zero crossing of the supply waveform.Said supervisor circuit means preferably further includes computer means programmed for calculating, from a signal indicative of an amount of power to be applied to the load or a respective one of the loads, an elapsed time during a supply waveform cycle after which said switch or the respective one of the switches is to be triggered in order to provide that amount of power, said computer means being responsive to a timing signal from said phase detector device to make a digital signal indicative of said calculated elapsed time available to said output signal producing means.

The supervisor circuit computer means may be operable for calculating a plurality of elapsed times and for transferring digital signals indicative of said times to respective ones of a plurality of output signal means which are able to control switches connected to respective different loads.

According to a third aspect of the invention, there is provided an installation comprising one or more electric lamps, electrically triggerable semiconductor switch means for controlling the application of a mains electrical supply to the lamps, and control apparatus as described above connected for contrilling the triggering of the switch means.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which: figure lisa block diagram of a lighting installation comprising a plurality of electric lamps and appar atus for controlling the brightness of each lamp, figure 2 is a simplified circuit diagram of a phase detector device used in the figure 1 control appar atus, figure 3 is a simplified circuit diagram of a supervisor unit used in the figure 1 control appar atus, figure 4 is a simplified circuit diagram of an output module used in the figure 1 control apparatus, figure 5 is a circuit diagram of a drive circuit connected to a series of electric lamps, figure 6 is a timing diagram relevant to the operation of the figure 1 control apparatus the left-hand side of this diagram having an expanded time axis relative to the right-hand side, and figures 7a and 7b are a program flow-chart for a microprocessor used in the output module offigure 4, and a memory location diagram for this microp rocessor.

Referring first to figure 1, the illustrated lighting controller is operable for controlling up to eight sets of sixteen lamps 1, i.e. up to one hundred and twenty-eight lamps in all although only some of them are shown. The controller comprises a super visor unit 2 and a mains supply phase detector 3 constructed on a printed circuit board unit 4 along with eight printed circuit board connector sockets 5 by way of respective ones of which eight output modules 6 or respective further printed circuit boards are interconnected with the supervisor unit 2.

The supervisor board unit 4 also carries a power supply circuit 7 which forms from the mains supply a five volts d.c. supply for driving the supervisor unit, phase detector and the output modules. Each output module controls the application of the mains supply to each lamp of a respective one of the sets of lamps by a respective drive circuit 8.

The supervisor unit 2 interfaces with a numerical keypad 9 and an arrangement of light-emitting diodes 10 and optionally, via a serial data line 11, with a computer 12 having a serial data interface 13.

The keypad 9 and/or the computer 12 may be used to transfer data to random access memory within the supervisor unit 2 for controlling the lamps 1 and for selecting control programs prestored in read only memory within the unit 2. The control programs may be such as to cause the lamps to produce predetermined fixed or moving patterns of light, for example for advertising signs, discotheque light shows and such. The light emitting diode arrangement may provide indications of the operating state of the supervisor, the lamps being controlled, which of several pre-stored control programs has been selected and so on. As will be appreciated, the number and kind of data input and output peripherals can be modified if desired.For example, in addition to or instead of any or all of the devices shown, there could be provided a series of potentiometers operable via analog to digital converter(s) and perhaps a multiplexing arrangement, for simply controlling the brightness of different lamps 1 or different groups of lamps. To provide a sound-tolight effect an analog-to-digital converter interface could be provided to control the lamps from an audio signal received either from a transducer arrangement provided specifically for the purpose or direct from an audio system already present at the site of use.

If it is present, the computer 12 could be near by or remote from the controller. If it is remote, the line 11 could incorporate some form of wireless transmis sion link, say an optical link. Computer 12 can also receive state indicative data from supervisor unit 2 via line 11. If the computer 12 is not required, then of course the serieal data communication capability of the supervisor unit need not be provided either.

The mains supply phase detector 3 is operable for producing a series of narrow low-going pulses the leading edges of which coincide with instants pre ceding, by about 100 uSecs. or so, respective zero-crossings of the mains supply. As shown in figure 2, the detector comprises an input network of three resistors 20, 21 and 22 and two back-to-back Zener diodes 23 and 24, which divides the mains voltage by about three and then limits the reduced voltage waveforms at plus and minus ten volts or so.

The signal from the input network is applied to the inverting inputs of two comparator amplifiers 25 and 26, the non-inverting inputs of the amplifiers being arranged to receive potentials of plus and minus five volts respectively from a potential divider compris ing three resistors 27 in series. The two ends of the potential divider are connected to the output terminals of an auxilliary power supply unit which supplies at these terminals plus and minus fifteen volts respectively and which also drives the two amplifiers 25 and 26. The power supply comprises a mains transformer 28 of which the secondary drives a bridge rectifier comprising diodes 29.The output voltages of the rectifier are smoothed by series resistors 30 and parallel capacitors 31 and regulated by Zener diodes 32, the capacitors and Zener diodes being connected between the plus and minus fifteen volt lines from the rectifier and a line which is connected to a centre-tap of the transformer secon darywinding and to the neutral sideof the mains supply to the input network of the phase detector.

This ensures that the signal supplied to the amplifiers 25/26 by the input network and the potentiometer and amplifier drive voltages are all referenced to the same level.

The outputs of the amplifiers 25 and 26 are interconnected via a resistor 33 and the transmitting diode 34 of an opto-coupler 35. Whenever the signal supplied by the input network lies between plus and minus five volts, the outputs of the amplifiers 25 and 26 are at different levels so current flows through diode 39. At other times, the amplifier outputs are either both high or both low so no current flows therebetween. Thus, on the output side of the optocoupler 35 there appears a train of pulses which are centred on respective zero crossings of the mains waveform and the leading edges of which precede the zero-crossings by the required 100 Secs.

or so. These pulses are applied to the clock input of a single shot multivibrator 36 to which there is coupled a timing circuit comprising resistor 37 and capacitor 38 and which is triggered by the leading edge of each input pulse to produce a respective one of the required narrow low-going output pulses. Each output pulse might have a width of say 15 Secs. or so.

As well as being taken off to the supervisor unit, the output pulses from the multivibrator 36 are also fed to the clock input of a second single-shot multivibrator 39 having an RC timing circuit set so that, in response to the trailing edge of each pulse from multivibrator 36, multivibrator 39 produces a high going pulse'having a width of about 9m. Secs. or so.

These pulses are fed to an inhibit of multivibrator 36 so as to suppress a good deal of any spurious pulses which may occur while allowing generation of pulses at times which are expected considering the mains frequency.

Referring now to figure 3, the timing pulses from the detector of figure 2 are fed to the interrupt input of a Z80 microprocessor 40 comprised in the supervisor unit. An eight line bus system 41 interconnects the eight data terminals DO to D7 of the microprocessor with the data outputs of 8255 programmable peripheral interface or "PPI" 42, the parallel data terminals of a 6850 serial parallel interface or "ACIA" 43 (the abbreviation ACIA stands for the term 'asynchronous communications interface adaptor'), the data terminals of a one kilbyte RAM memory system 44 comprising two 2114 RAM chips (not separately shown), the data terminals of a ROM memory system 45 which can accommodate up to four 2716 Eproms to give a total ROM capacity of eight Kilobytes but which depending on the particular kind of control application to be carried out, need not be fully populated, and, via a two-way puffer amplifier arrangement 46, with a respective group of the connector elements in each of the output module connector sockets 5. The first eight address outputs A0 to A7 of the microprocessor 40 are fed to buffer amplifier unit 37 and then, as buffered address signals BA0 to BA7 via bus system 48 to the RAM and ROM memories 44 and 45. The bus 48 also takes microprocessor address outputs A8 and A9 to the RAM memory 44, outputs A8, A9 and A10 to the ROM memory 45 and signals BA0 to BA6 to a respective group of connector elements in each connector 5. Address outputs A8 to A10 are also fed to the A, B and C inputs respectively of each of two one of eight address decoders 49 and 50.Microprocessor address outputs All to A13 are connected to respective ones of the A, B and C inputs of a decoder 51 while the address output Al 5 of the microprocessor and its memory request terminal MREQ are connected to the read and write inputs G2A and G2B respectively of a one of eight decoder 51. Decoder 51 acts as a chip select decoder and accordingly four of its outputs, labelled as ROM 0, ROM 1, ROM 2 and ROM 3, are taken to a gating system 52 along with a buffered version BRD of the microprocessor memory read signal RD to select one of the four Eproms making up memory 45 for a read operation thereon.

A 2114 Ram chip has a 1 K x 4 bit capacity so the two chips making up RAM memory 44 are used together, one group of four locations in each chip being addressed by the ten bit address signal BA0-BA7, A8 and A9 for communication with the four data lines DO to D3 and the four data lines D4 to D7 respectively. Thus, only a single select signal needs to be provided for the RAM memory by decoder 51. This signal, labelled RAM, is combined by gate system 53 with signal BRD and also a buffered version BWR of the microprocessor memory write signal WR to form a RAM memory select signal and a read/write signal for the memory 44.

Two further outputs of the decoder 51 provide select signals AC1A and PPI for the serial/parallel interface 43 and the programmable peripheral interface 42. The last output of the decoder provides a signal OM for selecting the direction of data transfer through buffer amplifier arrangement 46, i.e. for assisting in selecting a read or write operation involving the output modules connected to socket connectors 5. The two-way buffer amplifier arrangement 46 comprises two LS 15244 eight-bit buffer chips (not separately shown), the first being connected for signal transfer from bus 41 to sockets and the second in reverse for transfer from sockets to bus. The signal OM is and-gated with signal BWR to form a "transfer data to output modules" signal which is fed to the enable input of the first buffer chip, and signal OM is also and-gated with BRD to form a "read from output modules" signal which is fed to the enable input of the second buffer chip. The remainder of the means for output module selection involves signal OM being fed to the G2A inputs of the two decoders 49 and 50, the G2B inputs thereof being fed with signals BRD and BWR respectively.

These two decoders are thus operable, in response to signals OM, BRD and BWR, and the microprocessor address signals A8 to Awl 0, to produce, from decoder 49, a set of read signals SRD0 to SRD76r initiating a read operation involving a selected one of the output modules and, from decoder 50 a set of write signals SWRO to SWR7 for initiating a write operation involving a selected one of the output modules.

The function of the serial/parallel interface 43 is to transmit information between the lighting controller and computer 12. As mentioned earlier, the computer 12 is optional and, if the computer is not required, the interface 3 need not be provided either (unless, of course, it is wanted for serial communication with some other apparatus). The serial data transmit and receive terminals Tx and Rx of the interface, its hand-shake control terminals RTS and CTS, meaning "request-to send" and "clear-to-send" respective!X, and its "data carrier detect" terminal are connected to corresponding terminals of the interface 13 as will be clear to those skilled in the art. The serial/parallel interface select signal ACIA from decoder 51 is applied to one of the chip select inputs of the interface 43, the other(s) (not shown) being grounded.Signal BWR is fed to the read/write input RW of the interface and is also Nand-gated with signal BRD to provide a signal for application to the enable input E. The reset input RS is controlled by the buffered microprocessor address signal bit BA0.

The interrupt request output terminal IRQ is applied to the non-maskable interrupt input NMI of the microprocessor. Finally, the interface transmit and receive timing inputs TxClk and RxClk are fed with a timing signal from a frequency divider 54 which is, in turn fed from a master clock generator 55. The clock generator 55, of which the component parts are not shown, comprise a crystal controlled 16 MHz oscillator driving a four bit binary counter which thus makes available clock signals at frequencies of 8,4,2 and 1MHz respectively. The 2MHz signal is fed via buffer circuit 56 to the clock input 13 of the microprocessor. The 2MHz signal is also applied to a respective element of each of the socket connectors 5 for onward transmission to the output modules.

The input of the frequency divider 54 is connected to a desired one of the four outputs of the counter in the clock generator 55, for example via a selectable link connection. This divider divides the selected clock signal frequency by thirteen to produce an interface timing signal at a frequency of 615.38 KHz, 307.7 KHz, 153.85KHz or 76.92 KHz. The ACIA is programmed to use the selected timing signal to produce a desired standard Baud rate in the range 1200 to 38,400 Baud.

The function of the programmable peripheral interface 42 is to provide for parallel data transfers between the microprocessor 40, the keypad 9 and the indicator diode arrangement 10. The latter arrangement could be connected to the interface via one or more decoders (not shown). A suitable detailed arrangement of the connections to the keypad and indicator arrangement will be clear to those skilled in the art- it depends somewhat upon the required form of these devices and upon any further or alternative input"output devices required, for example the aforementioned arrangement of slide potentiometers. By way of example, a 4 x 4 matrix keypad could have its columns connected to respective ones of the lines CO to C3 of the interface port C, these lines being set up as outputs while the keypad rows are connected to Port A lines A0 to A3 configured as inputs.A test switch 59 is connected to one of the spare port A lines, say A7 shown. Port C lines C4 to C7 could control a series of light-emitting diodes in arrangement 10 via a 4 to 16 line decoder while respective further diodes therein could be controlled from port B lines BO to B5 via respective buffer inverters (not shown). One of the I/O lines of the interface, B7 as shown say, is kept free for applying an output module reset signal to each output module via the connectors 5 and via an or-gate 60 and inverting buffer 61.Or-gate 60 is also connected to receive an output module reset signal from a reset signal generator unit 62, which is further operable for providing conjugate supervisor reset signals to the interface 42 and to microporcessor 40 (the Z80 microprocessor reset is active low and the 8255 interface reset is active high), these reset signals being generated by unit 62 either when the system is first set in operation or in response to operation of push-button switch 63. The output module reset signal from line B7 of interface 42 is microprocessor controlled as explained later. On the system side of interface 42, the data lines DO to D7 are connected to bus 41 as mentioned earlier.The interface address input lines A0 and Al are connected to receive the buffered address signals BAO and BA1 from the microprocessor while the read, write, chip select and reset interface control lines RD, WR, CS and Reset receive signals BRD, BWR, PP1, and the aforementioned reset signal from generator unit 62.

Referring now to figure 4, each output module 6 comprises a further Z80 microprocessor 70 of which the data terminals DO to D7 are connected via bus system 71 to the data terminals DO to D7 of a 128 byte 6810 random access memory 72, the inputs of each of two 74LS273 eight-bit latch devices 73 and 74 and, via a 74LS244 eight-bit buffer 75, to respective connector elements which, while the module is connected to one of the socket connectors 5 on supervisor unit board 4, receive appropriate ones of the supervisor data signals BD0 to BD7. Correspondingly, address terminals A0 to A6 of the microp rocessor 70 are connected via bus 76 and a further eight-bit buffer 77 to connector elements which receive respective ones of the supervisor unit address AO to A6. Bus 76 also interconnects with the address inputs AO to A6 of the memory 72 while the remaining bit path of buffer 77 is used to transfer the supervisor unit write signal SWR to the read/write terminal RiW of the memory, a resistor 82 being connected between this terminal and the high side of the five volt d.c. supply and to a Nand gate 77 of which the other input is connected to the read output terminal RD of microprocessor 70 and of which the output is connected to the chip select input CS of memory 72. The clock and reset signals from the supervisor unit are passed to the clock and reset inputs of the microprocessor, the reset signal being also fed to the enable inputs of the buffers 75 and 77 and to the clear inputs of the latches 73 and 74.The clock input of each latch is connected to the output of a respective one of two Nand gates 78 and 79. One input of gate 78 is connected to the address terminal A6 of microprocessor 70 while one input of gate 79 is connected to microprocessor address terminal A7.

The other input of each gate is connected via a common buffer inverter 80 to the microprocessor memory write terminal WR. The wait, bus request and both interrupts of the microprocessor are commoned via a resistor 81 to the high side of the d.c.

supply. The outputs of the latches 73 and 74 are connected to respective inverting buffers, for example contained in three 7405 devices as shown, of which the outputs form the outputs of the output module and are connected to the corresponding drive circuit 8.

Referring now to figure 5, each drive circuit 8 comprises a mains filter network 90 formed by inductor 91 and delta connected capacitors 92. The connections to the lamps 1 are made so that each is in series with a triac 93 between the mains supply lines 94 and 95 from network 90. The control input of each triac 93 is connected to one output terminal of a respective opto-coupler 96, the other output terminal of the opto-coupler being connected via a resistor to the lamp side of the same triac. The input terminals of each optocoupler are respectively connected via a resistor 97 to the high side of the 5 volt d.c. supply and to a corresponding output line from the corresponding output module 6.

As shown in figures 6 a and b, when the system is first powered up or when the reset button 63 is pressed, generator 62 sets the two supervisor reset signals produced thereby for the microprocessor 40 and interface 42 respectively, and the output module reset signal to their active states. The active state of the output module reset signal OMR1 lasts for about 1 millisecond longer than that of the supervisor reset signals which themselves may time out after about 1 millisecond.To give these signals, the generator 62 could comprise, for example, two monostables (not shown) of which the clock inputs are fed by a gate (not shown) having respective inputs coupled to the push-button 63 and, via say a capacitor, resistor, diode combination to the 5 volts d.c. supply line so that the gate receives an input pulse and the monostables activated on switch-on of the system or when the button 63 is operated. The supervisor reset signals can then be taken from the Q and Q outputs of one monostable, this having an R.C. timing circuit to give it a one millisecond time out while the output module reset signal is taken from the Q output of the other monostable, this having a two-millisecond R.C.

timing circuit.

The one millisecond period between time t1 when the supervisor reset signals SVR and SVR become inactive and time f3 when the output module reset signal OMR1 becomes inactive is used by the microprocessor to carry out any required initialisation routines including initialisation of the interface 42. Such initialisation includes setting up, at time t2, an active state of the output module reset signal OMR2 (figure 6fl at the B7 output of interface 42 so that, even after signal OMR1 has become inactive, the output modules remain stopped for a time as shown at figure 6g. During initialisation, the ability of the interrupt signal INT (figure 6g) from the mains phase detector 3 to interrupt the operation of processor 40 is prevented by the lack of a software generated interrupt enable (figure 6c).This is applied at time t which time is dependent upon the software being run in the microprocessor and which, to show its variability is indicated by a shaded area in figure 6c.

The microprocessor now continues to execute its main program while being accessible to the arrival of the next and each subsequent interrupt signal INT from phase detector 3, whereupon it enters an interrupt routine. The interrupt routine includes maintaining (for the first interrupt signal INT to arrive) or generating (for each subsequent interrupt signal) the active state of OMR2 for a short predetermined time spanning each period between arrival of an interrupt signal and the following zero crossing of the mains waveform (figure6d).

The main program for the microprocessor causes it to receive from interface 42 or 43, or possibly from the read-only memory 45 (as part of an auxilliary program for executing some predetermined illumination pattern), information concerning the de sired brightness of the respective lamps 1 and, from it, the microprocessor calculates, for each output module 6, i.e. for each set of sixteen lamps, a series of delay times da, d2 and so on, possibly but not necessarily up to d16, these delay times repsectively being ones which are to elapse between each return to the inactive state of the output module reset OMR2 (and hence also OMRT) and a first "event" which is to take place in connection with the associated set of lamps, between that first "event" and the next "event", and so on.Each ofthese "events" comprises the triggering of one or more of the triacs 93 in the appropriate drive circuit 8 and hence the energisation of the corresponding lamps 1.Each return to the inactive state by OMR2 occurs at about the start of a new half-cycle of the mains waveform so, the shorter the delay after which a particular triac 93 is triggered, the brighter will be the lamp connected to that triac. Each delay time is stored in random access memory 44 along with a two-byte mask word indicative of which lamps of the set are to be energised after that delay time. Thus, it may be that there is stored only one delay time and a mask word indicating all sixteen of the lamps-this would be the case if all the sixteen lamps are to be equally bright. On the other hand, if the lamps are all to have different brightnesses, then there would be stored sixteen delay times and a corresponding number of mask words.

As mentioned earlier, whenever an interrupt signal INT arrives from the phase-detector 3, the output module reset signal OMR2 and hence OMRT are rendered active. Within drive circuit 8, signal OMRT enables the buffers 75 and 77, clears the latches 73 and 74 and resets the output module microprocessor 70. As a result, any triac trigger signals being applied by the latches 73 and 74 are removed, the corres ponding triacs thereby switching off at the subse quent mains waveform zero crossing. A reset signal applied to a Z80 microprocessor automatically tris tates its address and data lines so the random access memory 72 within the output module becomes available, via the buffers 75 and 77, within the memory map of the microprocessor 40 of the supervisor unit 2.Meanwhile the interrupt routine of microprocessor 40 includes the application to its address lines All to A13 and Al 5 and its control line MREO of signals which, via the decoders 49,50 and 51, set the buffer arrangement 46 in the supervisor unit for data transfer from the supervisor unit to the output modules and select, in turn, the random access memories 72 of the respective output mod ules for a write operation thereto. While each memory 72 is selected, the microprocessor 40 extracts from memory 44 the appropriate series of delay times and mask words and transfers them to the memory 72. The microprocessor 40 now returns to its main program calculating any new values of delay and storing them with the appropriate mask words.The output module reset signal becomes inactive so buffers 75 and 77 are disabled and the clear signal is removed from latches 73 and 74 in each output module. The microprocessor 70 in each output module now starts to run a simple program for which a flow chart is shown in figure 7a. Namely, with the memory 72 regarded as a stack memory and the stackpointer register of the microprocessor initialised to the top location of the stack, at which microprocessor 40 has previously stored the first delay time d1 of the series of delay times associated with this output module as shown at figure 7a delay time d1 is "popped" from the stack into a sixteen-bit register of the microprocessor and then de cremented until it equals zero.When it is equal to zero, the content of the next stack location is popped to the sixteen-bit register, this content being the mask word associated with the first delay timed1.

This word is put out to the latches 73 and 74 to initiate triggering of the corresponding triacs 93 in the associated drive circuit 8 and hence energisation of the corresponding lamps. The microprocessor now returns to pop the next stack location which will contain delay time d2, decrements it to zero, pops the corresponding mask word in the next stack location and so on. The function of the 'delay pad' step in Figure 7a is to ensure that the total time up to the end of a second or subsequent delay remains constant despite any changes that occur previously.

Thus, say that one lamp has a particular brightness, i.e. the associated triac is triggered after a particular total delay time in each cycle. If then, the number of delay values making up that total delay time changes, i.e. if another lamp is newly to become brighter than the first one, then the delay pad operation may need to pad out or reduce the values to ensure that the first lamp keeps the same brightness. Figure 6h shows, as an example, a signal TRl,which is the buffered and inverted output from one of the outputs of one of the latches 73 and 74 and which thus controls, via one of the optocouplers 96 in the associated drive circuit, a corresponding triac 93.As shown at each time t7, i.e. after delay d1 following each time t6 at which OMRT becomes inactive, the inverted latch output signal TR1 goes low and hence turns on the transmitter diode of the corresponding opto-coupler 96. The receiver side of that opto-coupler thus becomes operable to apply triggering current to the corresponding triac 93 and the corresponding lamp receives the drive voltage L1 shown in figure 6i. From each time t7, the microprocessor times out delay time d2 leading up to time t8 in the figure when a further inverted latch output signal TR2 (figure 6ç5 goes low and the associated lamp receives drive voltage L2 (figure 6k).

Since this waveform comprises less of each mains half-cycle than Ll,the second-mentioned lamp will be less bright than the first. It will be appreciated that figures 6h and 6k are given only by way of example to demonstrate how the micro-processor times out the delay d1, between the end of the output module reset and triggering ofthetriacforthe lamp(s) which are to be brightest, then the delay d2 before triggering of the triac for the next brightest lamp and so on.

As mentioned earlier, depending upon the required brightness of the sixteen lamps associated with the particular output module, there might be sixteen delay times d1 to d16 to be timed out each leading to only one latch output changing state (this giving different brightnesses of all the lamps). If some of the lamps are to be equally bright, then there would be fewer than sixteen delay times to be timed out and after each of one or more of those times more than one latch output will change.

It will further be realised that the illustrated controller is not necessarily only applicable to the control of electric lamps but could be used say for the control of speed and/or power of a series of motors or other loads.

Further the illustrated distribution of the parts of the overall controller to a supervisor unit, a series of output modules, and drive circuits is not essential.

For example, each output module and associated drive circuit could comprise one unit, or each drive circuit could be split-up even to the extent of simply providing a single triac unit close to each of a series of widely separated lamps, each such unit possibly including an opto-coupler or the opto-coupler could be in a separate unit or provided as part of the output module, and so on.

As will be realised, the apparatus illustrated is able to produce phase-controlled firing pulses for control of power to a load or loads directly from a microp rocessor, i.e. without the need for a separate timing register at the output side of the microprocessor.

Using the illustrated apparatus, a resolution of up to 400 brightness steps is possible provided the de tailed design of the apparatus is properly done (i.e.

the respective delays are incrementable in steps of around 25 usecs). Of course, using a faster microp rocessor and faster clock signals, even this resolu tion may be improved.

It is an advantageous feature of the illustrated apparatus, that each of the output modules 6 need not not contain any ROM memory- instead these contain RAM memory and the output module operating program is held in ROM in the supervisor circuit 2 -the program is then copied to the output modules on power-up of the system.

Of course, it is not essential that the system should be configured as shown. Each output module could be adapted for stand-alone operation by replacing its RAM, or supplementing it, with some ROM memory containing the operating program and, if desired, the stored delay and mask signals. In this case, the zero crossing signal would normally be fed to the interrupt input of the output module microprocessor rather than to its reset input.

Some of the ROM memory in the supervisor circuit could be used to store a look-up table for modifying the calculated delay values to give a linear characteristic or some desired non-linear characteristic relating demanded and actual lamp brightness, i.e.

instead of just calculating delays in linear relationship to the demanded brightness, the supervisor unit could use the look-up table to introduce a non-linear element in the calculation, say to compensate for non-linearity in the relationship between delay time and actual or subjective lamp brightness.

It will be realised that the delay and mask values need not be downloaded to the output modules at every cycle of the mains supply- rather such downloading can be arranged to occur only if and when some change in the desired brightness pattern is required.

It will normally be advantageous for all the lamps to be provided with some power, i.e. by always ensuring that each associated triac is turned on for some predetermined minimum time during each mains cycle, in order to keep the lamp filaments warm and thereby ensure that no current surges occur or are reduced when any lamp is suddenly brightened. This is done simply by so writing the software for the supervisory unit that every lamp is turned on after some chosen maximum delay. This software can also include features which give some desired characteristic to the power demand of the overall system -for example, it could be arranged to ensure that a predetermined maximum power demand is not exceeded or to smooth out sudden changes in demand.

Claims (12)

1. Control apparatus for controlling the power applied to a load from an alternating electrical supply by phase-controlling an electrically triggerable switch connected between the load and the supply, the apparatus comprising a phase-detector device for forming a series of timing signals at respective times when the supply is at a predeter mined point in its waveform and a microprocessor based computer system which includes a microp rocessor unit having an internal storage register and which is operable for storing in said register a digital signal dependent upon the power required to be supplied to said load and for responding to a signal from said phase detector device to measure out an elapsed time period indicated by said stored signal and to then generate an output signal for initiating triggering of said switch.

2. Control apparatus according to claim 1, where in said microprocessor unit is operable solely for taking said digital signal into its internal register, for timing out said time period and generating said output signal, and wherein the apparatus comprises a further microprocessor unit which is operable for calculating said digital signal and making it available to the first-mentioned microprocessor unit.

3. Control apparatus according to claim 2, wherein the two microprocessors share a common random access memory area to which the further microprocessor is operable for writing said digital signal and from which the first-mentioned microprocessor reads the digital signal.

4. Control apparatus according to claim 1, wherein said computer system is operable for storing a plurality of digital signals dependent upon the power required to be applied from said supply to a plurality of loads and for responding to each of said timing signals to measure out elapsed time periods indicated by the stored digital signals and to generate respective output signals for initiating triggering of respective electrically triggerable switches.

5. Control apparatus according to claim 4, wherein said computer system is operable for measuring out in succession respective ones of a plurality of elapsed time periods indicated by respective ones of a plurality of stored digital signals and, when each period has been measured out, for generating one or more output signals for initiating triggering of one or more corresponding ones of a plurality of electrically triggerable switches.

6. Control apparatus according to claim 4 or 5, wherein said computer system is operable for storing a plurality of further digital signals each indicative of one or more of said switches which are to be triggered following a respective one of said elapsed time periods the computer system becoming responsive to the respective further digital signal following measuring out of each elapsed time period to generate output signals for initiating triggering of the switches indicated bythatfurtherdigital signal.

7. Control apparatus according to claim 6, wherein said microprocessor unit is programmed to receive into its internal register from a memory a plurality of digital signals in succession, to regard alternately received ones of said digital signals as being indicative of respective elapsed time periods and to measure out these periods by decrementing the signals and, after so measuring out each such period, to generate an output signal dependent upon the next received one of the other digital signals.

8. Control apparatus according to claim 7, wherein said microprocessor unit is programmed to regard said memory as a stack memory and the program for the microprocessor circuit comprises instructions to receive digital signals from succes sive memory locations indicated by a stack pointer register of the microprocessor and, each time, to increment the content of that register.

9. Control apparatus according to any preceding claim, wherein said phase-detector device compris es comparator means for comparing said supply with respective reference voltages substantially equi-spaced above and below zero volts, and signal shaping means for responding to the comparator means to generate respective pulse signals prior to each zero crossing of the supply waveform.

10. Control apparatus according to claim 2, wherein said further microprocessor unit is operable for calculating a plurality of elapsed times and for transferring digital signals indicative of said times to respective ones of a plurality of output signal means which are able to control switches connected to respective different ioads.

11. Control apparatus substantially as hereinbefore described with reference to the accompanying drawings.

12. An installation comprising one or more electric lamps, electrically triggerable semi-conductor switch means for controlling the application of a d.c.

mains electrical supply to the lamps, and control apparatus according to any preceding claim connected for controlling the triggering of the switch means.