GB2115162A - Apparatus for testing circuit interrupting devices such as fuses - Google Patents

Abstract

An apparatus for testing a plurality of circuit interrupting devices, at least some of which have their supply terminals connected to the supply via switches, includes resistors (19) grounding the load terminals of all the devices, and pull-up resistors (27) connecting the supply terminals to the supply independently of the switches. An exclusive OR gate (28) is provided for each of those devices and indicates by its output whether the device is open- circuit. Signals from the OR gates (28) and the remaining load terminals are collected by an AND gate (20) which controls a warning lamp (25). <IMAGE>

Description

SPECIFICATION Apparatus for testing circuit interrupting devices such as fuses This invention relates to an apparatus for testing circuit interrupting devices, such as fuses.

It has already been proposed to test fuses by connecting a plurality of inputs of a logic circuit to the load terminals of a bank of fuses, the logic circuit providing an output if any one or more of the fuses is open circuit.

Such an arrangement cannot, however, be used when one or more of the fuses in the bank is not directly connected to the supply, but is connected, instead, via a switch.

Clearly, the known logic circuit cannot distinguish between the condition in which a fuse is blown and that in which the switch is open, since, in either case, the input to the logic circuit will be low.

It is an object of the present invention to provide an apparatus for testing a bank circuit interrupting device such as fuses in which this disadvantage is avoided.

In accordance with the invention there is provided an apparatus for testing a plurality of circuit interrupting devices at least one of which has its supply terminal connected to a supply via a switch device, said apparatus comprising a plurality of test terminals for connection to respective ones of the load terminals of the circuit interrupting devices, at least one further test terminal for connection to the supply terminal of the at least one circuit interrupting device, a semiconductor detector circuit connected to said test terminals and said at least one further test terminal, said detector circuit operating in the case of said at least one fuse to detect whether the associated test terminal and the further test terminal are interconnected by detecting a test voltage applied thereto, and a warning device operable by the detector circuit on detection of any open circuit interrupting device.

Preferably each test terminal is connected to a ground terminal by an associated one of a plurality of first resistors, so as to provide a low input to the detector circuit in the event of the load controlled by the circuit interrupting device being open circuit. The or each further test terminal may be connected by further resistor means to a supply terminal so as to apply said test voltage thereto.

The detector circuit preferably includes in respect of the or each of said at least one further test terminals, an exclusive OR gate having inputs connected respectively to the associated test terminal and the associated further test terminal. The output of the or each such gate and any remaining test terminals are connected to an AND gate.

Alternatively, in a more complex form of the invention the semiconductor detector circuit may include decoder means, and the warning means may include an alpha-numerical display driven by said decoder means and arranged to provide an alpha-numerical display indication of the location of the open-circuit device.

The above described apparatuses may be incorporated in the cover of a fuse box having removable fuses forming the circuit interruption devices. The test terminals are in the form of contacts arranged to make direct contact with exposed terminal portions on the fuses. An additional contact for making direct contact with an exposed contact on the supply side of any of the fuses which is connected to the battery via a switch is also provided.

In the accompanying drawings: Figure 1 is an exploded view, partly in section of a vehicle fusebox and its cover for use in an example of an apparatus in accordance with the invention; Figure 2 is an underside view of the cover; Figure 3 is the electrical circuit diagram of an example of the invention; and Figure 4 is the circuit diagram of another example of the invention.

Referring firstly to Fig. 1, the fusebox 10 is designed to receive six blade type fuses 11 each of which has an area 11 a of each blade exposed on its top surface. The cover 1 2 for the fusebox has an array of spring contacts 1 3 mounted on it, each such contact 1 3 being positioned, when the cover is mounted on the fusebox to engage the area 11 a of an associated one of the fuses, on the load terminal side thereof. A plurality of additional spring contacts 14 are each mounted on the cover to contact an area 11 a of the associated fuse on the supply side thereof.

As shown in Fig. 1 each spring contact 13, 1 4 is slidably mounted in a tubular body 1 5 which has a flange 1 6 at one end which serves to locate the body on the cover and also to limit movement of the contact 1 3 under the face of its spring 1 7. A clip 1 8 attaches the body to the cover.

Turning now to Fig. 3 it will be seen that each of the contacts 1 3 is connected to a test terminal which is connected to the vehicle ground by way of a pull-down resistor 1 9.

The spring contacts 1 4 on those of the supply terminals which are not connected directly to the battery are connected by pullup resistors 27 (of lower ohmic value than the resistors 1 9) to the supply. These additional contacts 14 and the associated contacts 1 3 are connected to the inputs of EXCLUSIVE OR gates 28 (one for each fuse with a switched supply) and the outputs of the EXCLUSIVE OR gates are connected to inputs of an AND gate 20 via respective inverters 29. The remaining contacts 1 3 are connected respectively to inputs of the AND gate 20. AND gate 20 is supplied via a connection to one of the terminals 14, via a resistor 21, a zener diode 22 being employed to stabilise the voltage supplies.The output of AND gate 20 is connected by a resistor to the base of a pnp transistor 24 which has its emitter connected to an ignition switch controlled rail and its collector connected by a warning lamp 25 to ground.

With this circuit the outputs of any EXCLU SIVE OR gate 28 is high only if its two inputs are different, indicating that the fuse is opencircuit. The resistors 27 ensure that this different input condition occurs whatever the state of the associated supply switch or any load switch. The output of AND gate 20 goes low if any fuse is ruptured and the lamp 25 is thus lit.

Turning finally to Fig. 6, a more complex circuit is shown which utilizes an alphanumerical display as warning device to indicate exactly which fuse is blown. the display is in the form of two four-digit seven-segment LCD display devices (type 586-920) 30 and 31 arranged side-by-side to provide a continuous eight digit display. In the event of a fuse faiiing the four digits on display 30 display the word FUSE in a flashing display. Two of the digits of display 31 display the number of the blown fuse, in the form 06 or 05 etc.

Each fuse has a contact 1 3 and a contact 14 as in Fig. 5 and an associated exclusive OR gate 28 having a pull-up resistor 27 and a pull-down resistor 1 9. The outputs of the gates 28 are connected to six of the inputs of a priority encoder 32 (type CD 4532B) providing a three bit binary output in accordance with the "highest" priority high input from gates 28. The E1 input of the encoder 32 is connected to the supply by a resistor 33 and to ground via a test display switch 34. The E0 output of encoder 32 is connected to an inverter 35, the output of which is connected to one input of a NAND gate 37.The other input of NAND gate 37 is connected to the output of an inverter 38, which, together with another inverter 39, two resistors 40 and 41 and a capacitor 42 forms a squarewave oscillator of conventional design providing square waves at the desired display flashing frequency.

The output of gate 37 is connected to the BLANK input of a display driver circuit 50 (type CD 4543B) and is also connected to an inverter 43 feeding one input of an exclusive OR gate 44. the other input of gate 44 is connected to the output of an inverter 45 arranged with another inverter 46, two resistors 47, 48 and a capacitor 49 to form a square wave oscillator operating at a frequency of about 100 Hz. The output of gate 44 is connected to the pins shown of displays 30 and 31. The output of inverter 45 is connected directly to the PH pin of driver circuit 50 and to the indicated pins of display 31. The segment outputs of driver circuit 50 are connected to the appropriate segment pins of display 31.

The circuit also includes an array of inverters 51 connected to respective outputs of the gates 28 and driving light emitting diodes 52 via resistors 53, the diodes 52 being arranged on the fuse box and the displays 30, 31 in the instrument panel of the vehicle.

When all the fuses are intact, the gates 28 outputs are low. If any one goes high, an appropriate three bit binary signal is output by encoder 32 and the signal at terminal E0 goes low. This provides a high input to gate 37, which then provides a square-wave output in antiphase with the output of inverter 38. This square wave is applied to the blanking output of driver circuit 50 causing the number of the blown fuse to flash on the display 31. The gate 44 passes the output of inverter 45 during the flashing intervals and thereby causes the FUSE display elements to flash.

Claims (9)

1. An apparatus for testing a plurality of circuit interrupting devices at least one of which has its supply terminal connected to a supply via a switch device, said apparatus comprising a plurality of test terminals for connection to respective ones of the load terminals of the circuit interrupting devices, at least one further test terminal for connection to the supply terminal of the at least one circuit interrupting device, a semiconductor detector circuit connected to said test terminals and said at least one further test terminal, said detector circuit operating in the case of said at least one fuse to detect whether the associated test terminal and the further test terminal are interconnected by detecting a test voltage applied thereto, and a warning device operable by the detector circuit on detection of any open circuit interrupting device.

2. An apparatus as claimed in claim 1 in which each test terminal is connected to a ground terminal by an associated one of a plurality of first resistors.

3. An apparatus as claimed in claim 2 in which the or each further test terminal is connected by further resistor means to a supply terminal so as to apply said test voltage thereto.

4. An apparatus as claimed in claim 3 in which said further resistor means comprises in respect of the or each further test terminal, a second resistor of lower ohmic value than said first resistor.

5. An apparatus as claimed in claim 4 in which the detector circuit includes in respect of the or each of said at least one further test terminals, an EXCLUSIVE OR gate having inputs connected respectively to the associated test terminal and the associated further test terminal.

6. An apparatus as claimed in claim 5 further comprising an AND gate to which the output of the or each EXCLUSIVE OR gate is connected via an inverter and to which any remaining test terminals are connected.

7. An apparatus as claimed in claim 5 in which the detector circuit further comprises decoder means connected to each exclusive OR gate, said warning means comprising an alpha-numerical display driven by said decoder means and arranged to provide an alphanumerical indication of the location of the open-circuit interrupting device.

8. An apparatus for testing a plurality of circuit interrupting devices substantially as hereinbefore described with reference to Figs.

1 to 3 of the accompanying drawings.

9. An apparatus for testing a plurality of circuit interrupting devices substantially as hereinbefore described with reference to Figs.

1, 2 and 4 of the accompanying drawings.