GB2113934A - Determining switching threshold in CMOS circuits - Google Patents

Abstract

A CMOS logic input circuit includes a bias generator stage (TR1, TR2) controlled by a reference voltage. A second stage (TR3, TR4) is controlled by this bias, such that its input generator a low or a high signal at its output dependent on whether that input is above or below the reference voltage supplied to the bias generator. Input signals "earth" and "supply" voltage offsets to reduce or cancel out the variation of the input switching threshold due to the uncorrelated spreads of N and P channel transistor turn on voltages which generates a low or high output dependent on whether this input is above or below the reference voltage. <IMAGE>

Description

SPECIFICATION Improvements in integrated circuits This invention relates to integrated circuits, and in particular to input arrangements for complementary metal-oxide-silicon (CMOS) logic circuits.

CMOS integrated logic circuits are employed in a wide variety of applications where their low power consumption confers a distinct advantage over other logicfamilies. One of the problems associated with all CMOS input circuit designs is that of achieving the desired tolerance on its switching threshold voltage, e.g. to render the circuit TTL compatible, despite the unrelated production spreads of P and N channel transistor characteristics. Where a CMOS circuit is produced in large volume by a single manufacturer this does not constitute an insoluble problem as the mask designs can be matched to typical device parameters and strict process controls can be applied.Where, however, a circuit is to be made in small volume by a variety of manufacturers all of whom employ slightly different processing techniques it has previously been necessary, to obtain electrical uniformity of the finished circuits, to design a mask set for each manufacturer. This is an extremely expensive procedure and inevitably results in a high unit cost for the finished circuit.

The object of the invention is to minimise or to overcome this disadvantage.

According to one aspect of the invention there is provided a complementary metal-oxide-silicon (CMOS) logic input circuit, including means for generating a stabilised bias voltage with which input signals are compared to define the output logic state of the circuit.

According to another aspect of the invention there is provided a complementary metal-oxidesilicon (CMOS) logic input circuit, including a reference voltage source, a bias generator, and to a two input switching stage, wherein the bias generator is adapted to supply a bias voltage corresponding to the reference voltage to one input of the switching stage, wherein the other input of the switching stage provides the circuit logic input, and wherein said switching stage is arranged to switch to a first or second output condition according to the level relative to the bias voltage of a logic signal applied to the other input.

It will be appreciated that although because of difficulties in accurately controlling doping profiles, oxide thickness etc., transistor and resistors with predetermined and reproducible characteristics cannot readily be fabricated, components with the same intended length and width, processed close together on the same silicon wafer, will however match accurately.

Furthermore by ratioing effective component dimensions, transconductances and resistances can be accurately ratioed. Thus a resistive potential divider across the power supply can provide an accurate fraction of that supply as a reference voltage, or a pair of N-channel, or of Pchannel, transistors with the same applied gate voltage will pass accurately ratioed drain current, provided their drain voltages are high enough for both devices to operate under saturated conditions.

It will of course be understood that the term CMOS as employed herein includes both silicon gate and metal gate constructions although for most appiications we prefer to employ silicon gate techniques.

An embodiment of the invention will now be described with reference to the accompanying drawings in which: Fig. lisa block diagram of the CMOS input circuit; Fig. 2 shows one embodiment of the circuit of Fig. 1, with a resistive potential divider supplying the reference voltage; and Fig. 3 shows a Schmidt trigger arrangement employing the circuit of Figs. 1 and 2.

Referring to Fig. 1 , the input circuit includes a bias generator BG the output of which is coupled to one input of the switching stage (OP). The other input of the switching stage comprises the circuit input I/P. The stage OP switches to a high or low output condition dependent on whether the signal applied at the input IP is above or below the reference voltage.

A circuit arrangement embodying this technique is shown in Fig. 2. In this circuit the voltage reference is provided by resistors R1 and R2 whose dimensions, and hence ohmic values, are in a predetermined ratio and which together form a potential divider. This provides a reference voltage which is clearly defined relative to the circuit supply voltage. The voltage tapping of the potential divider is connected to the gate of an nchannel transistorTR1 arranged in series with a complementary p-channel transistor TR2. The gate of this p-channel transistor is shorted to its drain thus ensuring that negative feedback sets an appropriate gate voltage for it to sink the current passed by TR 1 and that both TRi and TR2 are operating under saturated conditions.

The bias voltage produced at the gate of TR2 is also applied to the gate of the output stage load transistor TR4 and this ensures that the drain current of TR4 in saturation, ratios to that of TR2 and, since the current in TR1 and TR2 are equal, to the drain current of TR I. Thus if the ratio of the sizes of TR1 to TR2 is the same as the ratio of the sizes of TR2 to TR4, TR3 will pass the same current as TR4 when its gate voltage is the same as TR3's, i.e. when the circuit input voltage equals the reference voltage.Since TR4 is operating in a constant current mode for a significant range of output voltages, the output stage gain will be high and the output can be made to switch from high to low for small input voltage channels about VREF, i.e. the switching threshold has been established at VREF Because of drain to gate feedback capacitance in transistor TR4 its gate bias voltage will tend to go positive temporarily during a positive going output transition and negative during a negative going transition. This would reduce the pull up current when it is needed to switch the output high and increase it when transistor TR3 is switching the output low, resulting in slower circuit operation. If maximum speed of operation is desired then this tendency can be reduced by connecting a capacitor (C1) between the gate and source of transistor TR4.For 5 volt supply operation a typical value for this capacitor would be 50'times the feedback capacitance of transistor TR4. The tendency can also be reduced by increasing the size of transistors TR 1 and TR2 to reduce the drive impedance to the bias line. A trade off between speed and power consumption has to be fixed for each application of the circuit, as increasing the size of transistors TR1 and TR2 increases the current through these devices. A single bias generation circuit can however be used to bias all the input interfaces in an IC, i.e. a single bias voltage generator may be employed to provide a reference input level for a plurality of similar switching stages.

One example of the use of the technique is the construction of a Schmidt trigger circuit is shown in Fig. 3. In this arrangement two complete input circuits of the type described above are used. One is supplied with the desired high level switching threshold as a reference VREF H1 and the other with the desired low level threshold VRF Lo. Both are supplied with the same input. When this input goes above the high threshold level the circuit with that level as a reference sets an R-S flip flop BS1. When the input signal goes below the low threshold level the inverted output of the other input circuit via IV 1 resets the R-S flip flop. The flip flop output thus follows the input, but with Schmidt trigger hysterisis.

It will be appreciated that although the circuit arrangements described herein can be realised with discrete devices they will normally comprise or be incorporated in an integrated circuit.

Claims (8)

1. A complementary metal-oxide-silicon (CMOS) logic input circuit, including means for generating a stabilised bias voltage with which input signals are compared to define the output logic state of the circuit.

2. A complementary metal-oxide-silicon (CMOS) logic input circuit, including a reference voltage source, a bias generator, and to a two input switching stage, wherein the bias generator is adapted to supply a bias voltage corresponding to the reference voltage to one input of the switching stage,.wherein the other input of the switching stage provides the circuit logic input, and wherein said switching stage is arranged to switch to a first or second output condition according to the level relative to the bias voltage of a logic signal applied to the other input.

3. A CMOS logic input circuit as claimed in claim 2, wherein said voltage source includes a potential divider comprising a plurality of resistors the values of which are defined by their surface configurations.

4. A CMOS logic input circuit including a resistive potential divider connected between the supply terminals of the circuit and whereby, in use, a reference voltage is obtained, a bias voltage generator a first complementary pair of p-channel and n-channel transistors and adapted to generate a bias voltage corresponding to said reference voltage, and a two input switching stage comprising a second complementary pair of pchannel and n-channel transistors, wherein the pchannel and n-channel transistors of the two pairs are respectively similar in construction, wherein the bias voltage is fed to one input of the switching stage, the other input providing the logic signal input of the circuit, and wherein said switching stage is arranged to switch to one or other of two output logic conditions according to the level relative to the bias voltage of a signal applied to said signal-input

5. A circuit as claimed in any one of claims 2 to 4, and including a plurality of similar switching stages each coupled to the bias generator.

6. A CMOS logic input circuit substantially as described herein with reference to Figs. 1 and 2 of the accompanying drawings.

7. An integrated circuit incorporating one or more logic input circuits as claimed in any one of claims 1 to 6.

8. A Schmidt trigger circuit substantially as described herein with reference to Fig. 3 of the accompanying drawings.