GB2113444A - Matrix addressed liquid crystal displays - Google Patents

Abstract

The liquid crystal layer (11) of a matrix addressed display device is sandwiched between a transparent plate (13) and a silicon wafer (14) containing active devices by which the display is addressed. The wafer carries a matrix array of pads (17) accessed by gates formed in the wafer, and the wafer includes additional circuitry enabling this matrix array to be used as the storage elements of a dynamic random access memory. This allows the array elements of a wafer to be individually tested before it is used to form part of a display device, and, in the completed device, allows on wafer refreshing of the display after read-out of the state of the elements thus enabling a significant reduction in power consumption. <IMAGE>

Description

SPECIFICATION Matrix addressed liquid crystal displays This invention relates to a liquid crystal display cells of the type with picture elements (pels) arranged in a matrix array, and in which the liquid crystal layer is bounded on one side by a semiconductor layer provided with circuitry for addressing the cell. One example of such å cell is described in the specification of our Patent Application No. 2079022A, to which attention is directed.

The present invention is particularly concerned with.incorporating within the semiconductor layer circuitry that will enable the monitoring of data applied to picture elements. Such monitoring has at least two possible important uses.

If the circuitry is designed so that the monitored information can be electrically read from semiconductor layer, this may be used for testing the quality of its circuitry before proceeding to incorporate the layer into a display cell. In this context it is to be noted that the quality of the circuitry needs to be particularly high to get an acceptable yield of satsifactory cells on account of the large number of active devices present in the semiconductor layer. Thus for instance in the case of display having an array of 240 x 240 pels, 57,600 active devices are needed just for the display area, and several thousand more are required for access circuitry and control required to reduce the number of external connections to an acceptable number. Subjective evaluation has indicated that less than 1% random faults can typically be tolerated in the display.Clearly the yield can be improved by adopting fault-tolerance design techniques, but, in view of the scale of the problem, the supplementing of this by electrical testing prior to assembly of cells is advantageous.

A further advantage flows from designing the circuitry so that the monitored information is used to refresh the display without having to rely for this upon refresh data supplied to the circuitry of the layer from elsewhere. This can be achieved by using the pels as the storage elements of a special kind of dynamic random access memory. One feature distinguishing this from a conventional design of random access memory is that it is normally desirable to alternate the electric field across the liquid crystal layer so as to avoid, or at least limit, electrolytic degradation associated with unidirectional electric fields. This means that the data of the display needs to be replaced by its complement.Therefore when 'on-layer' refreshing is employed, and an alternating field is required, this refreshing must make provision for the alternation by periodically refreshing the data with its complement. A useful advantage resulting from the use of 'on-layer' refreshing can be a significant saving in power consumption. This is particularly important for battery-powered display applications.

According to the present invention there is provided a liquid crystal display cell which has a liquid crystal layer sandwiched between an upper transparent electroded plate and a lower plate formed by or carrying a semiconductor layer provided with a matrix array of semiconductor gates connected with an overlying matrix array of liquid crystal cell electrodes adjacent the liquid crystal layer, wherein the semiconductor layer includes circuitry enabling the determination of whether or not the charge held by the capacitance associated with each one of said liquid crystal cell electrodes of the matrix array is above or beneath a given threshold.

The invention also provides a liquid crystal display cell-which has a liquid crystal layer sandwiched between an upper transparent electroded plate and a lower plate formed by or carrying a semiconductor layer provided with a matrix array of semiconductor gates connected with an overlying matrix array of liquid crystal cell electrodes adjacent the liquid crystal layer wherein the semiconductor layer includes circuitry enabling the use of said matrix array of gates and the capacitance associated with their associated liquid crystal cell electrodes as the storage elements of a dynamic random access memory in which the stored information is periodically completed.

There follows a description of a liquid crystal display cell embodying the invention in a preferred form. The description refers to the accompanying drawings in which: Figure 1 depicts a schematic cross-section through the device, Figure2 depicts the basic picture element circuit diagram, Figure 3 depicts a block diagram of the on-wafer circuitry, Figure 4 depicts the row access circuitry in greater detail, Figure 5depicts the column access circuitry in greater detail, and Figure 6 depicts a block diagram of the external (off-water) circuitry Several different electro-optic liquid crystal effects involving dichroic dyes are possible for a display cell having its liquid crystal layer backed by active silicon wafer. These include the dyed nematic without front polariser, the dyed nematic with front polariser, and the dyed chloesteric-nematic phase change modes of operation.The dyed nematic without front polariser suffers from the disadvantage that, although the brightness is good, the contrast is poor. This is because only one of the two principal planes of polarisation of light through the crystal is subject to absorption by the dye, and thus about half the light is transmitted unchanged. Dyed nematics using a single front polariser avoid this problem by filtering out the mode of propagation that is not attenuated by the dye. This gives an excellent contrast ratio, but a heavy penalty is paid in terms of brightness due to the absorption of light in the polariser. For this reason, dyed nematic displays with a front polariser can look excellent in transmitted light, but reflected light displays only appear to be attractive in situations where there is strong front illumination.The dyed phase change effect is therefore preferred because it can provide the combination of acceptable contrast and good brightness.

Such a cell, with a pitch of between 3 and 4 microns, shows an optical transfer characteristic with a strong hysteresis. This hysteresis sets a maximum value to the acceptable 'off' voltage (rms) appearing on the active matrix. The active matrix scanning scheme has been designed to give a high drive voltage of 10 V(rms) so as to enable the smallest possible cholesteric pitch to be used. This maximises the absorption of the 'off' state. Measurements on a large number of such display cells with thicknesses between 10 and 15 m suggest that if the 'off' voltage is 1 V or less the device will switch rapidly off.

Referring to Figure 1, a dyed cholesteric nematic phase change cell on silicon is constructed by forming an envelope for a layer 11 of liquid crystal by sealing together, with an edge seal 12, a glass sheet 13 and a four inch diameter single crystal wafer of silicon 14. The edge seal 12 may be a plastics seal, thereby avoiding some of the alignment problems associated with the use of high temperature used in the provision of glass frit edge seals. The glass sheet 13 is provided with an internal transparent electrode layer 15 which is covered with a transparent insulating layer 16 designed to prevent the passage of direct current through the cell. The silicon wafer 14 is provided with a 240 by 240 matrix array of metal electrode pads 17, each measuring 0.25mm by 0.25mm, which is similarly covered with a transparent insulating layer 18.The exposed surfaces of the two insulating layers 17 and 18 are treated to promote, in the absence of any disturbing applied field, a particular alignment state of the adjacent liquid crystal molecules. Parallel homogeneous alignment is preferred for the dyed cholesteric nematic phase change mode of operation because it has been found to provide a faster response. Within the area defined by the edge seal the silicon slice 4 is held spaced a precise distance from the glass sheet 13 by means of short lengths of glass fibre (not shown) trapped between the two adjacent surfaces so as to provide the liquid crystal layer with a uniform thickness of typically 10 to 12 microns. Beyond the confines of edge seal the silicon wafer 14 is provided with a small number of pads 19 by which external electrical connection may be made with the circuitry contained within the wafer.

A particular pel is driven into the 'on' state by applying a potential to its pad 17 that is different from the potential applied to the front electrode 14. Each pad 17 is connected to the output of a MOS FET switch formed in the wafer 14 so that, when the FET is conducting, the pad can be charged up to a sufficient potential relative to that of the front electrode to activate the liquid crystal. The FET is then turned off to isolate the pad while those of other lines of the array are being charged. The pad is recharged after a complete cycle, and it is necessary to ensure that the leakage of charge away from the pad in the interval between successive chargings is not excessive. Part of this leakage will be through the liquid crystal layer and part through the turned-off FET. The arrangement of an FET in relation to its associated pad and access lines is represented in Figure 2.Each pel pad 17 is connected to the drain of its associated FET 20 whose gate and source are respectively connected to the associated row and column access lines 21 and 22. For reasons which will be explained later the connection between the FET drain and the pel pad 17 may not be a direct connection, but may be one made via a capacitor (not shown). The display is written line by line, with the data appropriate to each line being applied in turn to the column access lines, source lines, 22, while the row access lines, gate lines, 21 are strobed. In choosing how to make the access lines it is important to have regard to electrical risetimes, power consumption, and yield in manufacture. Three types of conductor were considered : metal, polysilicon, of diffusion.Metal lines have the shortest risetimes (typical resistance is 0.03 ohms per square and capacitance about 2 x 10-5 Fm-2), polysilicon next (resistance 20-50 ohms per square and capacitance about 5 x 10-5 Fm-2). Diffusions have lower resistance (about 10 ohms per square) but higher capacitance (about 3.2 x 10-4 Fm-2). The source lines 22 require the shortest risetime (particularly when the display is being blanked) and hence it is preferred to make them of metal throughout, and to make the gate lines of metal except at the crossovers where diffusions are used.

The dyed cholesteric nematic change effect typically requires an 'on' to 'off' voltage ratio of at least 10:1. A square wave signal is used to drive the front electrode 15 (Figure 1) to achieve as high as possible an rms voltage across the liquid crystal layer, and the scanning scheme used in the silicon slice 14 aims to match this waveform, or its complement, as closely as possible. A major problem for all schemes is to keep the 'off' voltage as low as possible without having to restort to splitting the front electrode into separate components. (Such splitting cannot be avoided in some circumstances, but it is preferred to avoid it if it is reasonably possible.) One way of minimising the 'off' voltage is to 'blank' the whole display each time the front electrode charges polarity.This is described in the specification of our Patent Application No. 2078422 to which attention is directed. A penalty associated with this blanking is a slight reduction in 'on' voltage.

With the scheme involving the blanking of the whole display it is preferred to have three distinct electronic modes of operating within the scheme which may be characterised as 'blank', 'scan', and 'wait'. These operations will now be briefly described in the context of the 240 by 240 array and in relation to access circuitrythat stores the incoming data in shift registers.

Blanking mode: duration 11.4'Ls Immediately after the front electrode starts to change voltage (it has a finite risetime) the shift register output latch is loaded with data (this data is either all 1's or all 0's depending on the front electrode voltage). All gate lines are driven high (with finite risetime) and so all the pel pads are driven to the front electrode voltage; 1 1.4 cos is allowed for this. All gates are driven low at the end of the blanking period. The source line data for the first row of the display is loaded during the blanking period.

Scan mode : duration 2.75 ms The display is scanned a line at a time. For each line the data is driven on to the source lines and the gate line is then driven high. Each pel pad charges to the required voltage and the gate line is then driven low again. During this time the source shift register is loaded with the data for the next line (shift registers with latched outputs are used).

Wait mode : duration 6.6 ms The wait period is simply a pause at the end of the scan, when all the FET's of the matrix are off and the charges are kept on the pel pads (apart from inevitable leages). It has proved to be unnecessary to rescan the FET matrix between front electrode changes. This is because at normal operating temperatures the FET 'off' resistance (typically greater than 1011 ohms at 25"C) is insignificant, as also is the leakage through the liquid crystal layer (liquid crystal resistivity typically greater than 108 ohm-m), and rescanning only refreshesthe pel pad voltage. If this has not significantly altered in the interval between consecutive blankings, then no advantage is gained by refreshing the pad within this time interval.

The block diagram of Figure 3 shows, in outline, the circuitry involved in the performance of these three modes of operation. Incoming data is fed to an input buffer 30 and held by a latch 31 operated by timing control 32. This particular display cell is designed for representing characters in a 6 x 10 dot matrix format, and hence the data is in put in bytes that are six bits long. Successive bytes are distributed in turn to each of eight 30-bit shift registers 33 by means of loaders 34, and these bytes are progressively shifted up the shift registers to accommodate the receipt of succeeding bytes until they are full. At this stage the data is transferred to access/sense circuitry blocks 35 from where it is transferred to the FET's of the display matrix under the control of a 240-bit Y-access shift register 36.All this circuitry is duplicated for fau It-tolerant design reasons. Thus for instance at the opposite ends of the row access lines is a second 240-bit shift register 36', and at the opposite ends of each set of column access lines is a second access/sense circuit block 35'. For testing purposes the serial outputs of the shift registers 33 are connected to test circuitry 37 provided with an output terminal 38. The half of the circuitry that proves inferior in performance on test is then disabled.

The distribution of data from the latch 31 to the access/sense circuitry blocks could alternatively be performed by means of a decoding tree similar to that used for standard random access memories. This approach is however not preferred because a requirement to read data for test purposes would necessitate the provision of an output decode circuit to deliver this information to the test output terminal 38. This circuit would have to be physically positioned on the same edge of the display matrix as the drive circuitry if the opposite edge carried the duplicate circuitry desired for fault tolerant design reasons. This would introduce further complexity in the layout of the column access circuits and thereby introduce its own yield problems.

A single 240 bit shift register 36 is satisfactory for row access for each half of the duplicated circuitry. One section of this shift register is depicted in Figure 4, which also shows how the gates of all the FETs 20 of display matrix are simultaneously driven high by means of a signal applied via a line 40 to the gate of a transistor 41 associated with each stage, For column access it is preferred not to use a single 240-bit shift register, but to split the function into the eight 30-bit shift registers 33 previously referred to. This is primarily because this enables the data to be fed to the access/sense circuitry units more quickly. This in turn permits a faster line scan.A fast line scan is desirable because, after blanking, an 'on' pel sees the wrong voltage until is is readdressed, and hence the rms 'on' voltage seen by an 'on' pel near the top of a line scan is greater than that seen by a similar'on' pel nearthe bottom of a line scan by an amount determined in part by the line scan speed.

The constructon of the access/sense circuitry units will now be described in more detail with particular reference to Figure 5 which depicts the circuitry associated with a single stage of one of the 30-bit column shift registers 33 and the corresponding column access line 22 of the display matrix. Each stage of the unit has logic elements 2 and 3 associated with driving the associated column access line 22, and logic elements 4 and 5 associated with reading the charge on the access line. Associated with these logic elements are three control gates 50a, 50h and 50c.

A pulse applied to 'load' line 51 drives the gate of control gate 50a of each access/sense circuitry unit high thereby causing the data stores in the shift register 33 to be applied to the column (source) access lines of the display matrix via logic elements 2 and 3. Logic element 2 acts as an inverter while the output of logic element 3 in effect depends upon the input from logic element 2 modified principally by the input from a true/complement line 52. In logic unit 2 practice the column access line 22 is charged up by a pulse applied to a precharge line 53, and the condition of the input from logic unit 2 and that of the true/complement line 52 determines whether this charge is held or dissipated before the appropriate one of the display matrix FET's 20 is switched on by a pulse applied to its gate from the 240-bit Y access shift register 36. If the true/complement line is low the output of the logic unit is the complement of the input from logic unit 2, whereas if it is high the output matches the input from logic unit 2. A duplicate line 54 is also connected with this logic unit so that, when this is held high, the output of the logic unit is isolated to enable the duplicate circuitry on the other side of the display matrix to be used.

The operation of blanking the cell is similar to that of writing in data line by line, but in this instance the 'data' is unpatterned (i.e. 'l's or all '0's) and is applied to logic unit 2 via input B from a blanking line 57, instead of via input A from the shift register 33.

Logic element 4 is used for monitoring the charge stored on a pel pad. Logic unit 3 applied the charge (or the absence of charge) to the pel pad 17 by the momentary switching 'on' of its associated display matrix FET 20. If this is functioning correctly the charge should be retained on the pel pad 17. This is tested by resetting the column access line 22 to a particular potential by a pulse applied to the precharge line 53 at a suitable time interval after addressing the pel pad 17. The FET 20 is then momentarily switched on for a second time so that the stored charge charge on its pel pad 17 is shared with that on its column access line 22. The resulting potential on the access line 22 is then compared in logic unit 4 with a reference potential applied to a line 55 connected to the unit.This comparison is made by turning the logic element 'on' by means of a clock pulse applied to a line 56. The voltage appearing at input B of logic unit 4 will be less than the reference voltage if the leakage of the pel pad is too great, and in these circumstances the unit will trigger the wrong way. The output of the unit is taken through an inverting amplifier logic unit 5, which also acts as a buffer, and is fed back into the shift register stage under the control of control gate SOb, which is turned on by means of a reading pulse applied to line 58. In this way data fed into the shift register, and then applied to the pel pads, can be later transferred back into the shift register, and fed serially from there to test circuitry 37 (Figure 3).With this arrangement true data is fed back into the shift register when the true/complement line 52islow.

The access/sense circuitry also allows the displayed data to be refreshed internally (i.e. on-wafer) without reference to incoming data. This may be useful in reducing the external circuit requirements, and can also be useful in reducing the power consumption. Refresh is carried out with the aid of control gates 50c operated by means of pulses applied to a refresh line 59 (Figure 5).

The operation of the display in this mode is as follows. Date is input to the wafer via the shift registers as before, but the refreshing of the display element voltages at each front electrode signal reversal is carried out by the detection circuitry. The previously described blanking is not possible with this scheme because all the information would be lost by the blanking before it could be used for the refreshing. The simplest alternative scaning arrangement is to complement (using the true/complement line 52) all the display voltages line by line in a sequence, with the front electrode changing voltage midway through the sequence. Because no blanking is possible, the most difficult parameter to control is the 'off' rms voltage. The 'off' rms voltage is given, to a good approximation, by

Vsupply = No. of lines x line time (t) > < factor due to barrier layers period offrontelectrode which is equal to 1370 by tfor this particular 240 by 240 display (tin seconds) To keep the 'off' voltage below 1 V rms requires the line time to be 0.5 ,us or less for this display. In circumstances in which it proves impossible to achieve a suitably short line refresh time, the 'off' voltage can be reduced, either by segmenting the front electrode, or by modiying the scanning sequence. Segmenting the front electrode gives a shorter time in the wrong state for any element. Each front electrode segment reverses its voltage in sequence as the refresh scan moves down the display.

If there are N distinct electrodes then the 'off' voltage is reduced by a factor VN Accurate alignment of the front electrode divisions over the display matrix is not necessary provided that the gap between individual electrodes is not visible, (i.e. narrower than about 12 Fm, which is achievable).

The circuitry in Figures 3 and 5 assumes that data is modified in blocks of 5 characters, and the X-shift register access is sub-divided into groups of 30 bits to achieve this result. To achieve single character entry the refresh and load lines are partitioned so that groups of 6 bits (dots) only are accessed from each of these control lines. This requires decoding of the line address together with the overall timing information to identify the correct slot in the timing sequence. Output from this decode selects data from the dot group address and dot data and applies it to the chosen X-access drive lines 22 to write the new data to the matrix.

All other character data may be refreshed in the normal way. The line, dot group, and dot data have to be present for a maximum of one frame period, or have to be stored in a buffer at the input to the wafer.

For the externally refreshed version the information to be displayed has to be stored in an external memory and entered into the wafer during each scan period. The data is required at 3.5 MHz rate, 6 bits wide.

The 6 bits correspond to one row of one character on the display. Figure 6 shows the arrangement of the external circuit. Character information data is received into the system in ASCII code at 60. If necessary this can be stored in a character memory 61, which must be 1 k by 8 bits wide. Alternatively the display may he updated line by line, which requires a smaller memory. The output from either of the memory systems is fed to a conventional ROM character generator 62. Control circuitry 63 organises which row of the character is output from the generator and fed directly to the display wafer 14. The page store memory and the character generator are capable of less than 280 ns overall access time.

The circuit requirement for the internally-refreshed version is much simpler. If the information supplied to the display system is in ASCII form, a character generator is required with the necessary control circuitry to load the data into the correct position on the matrix. If the data is supplied as the dot pattern itself, only a modified control circuit is needed, although for rapid changes of information some temporary storage memory may be necessary.

The power consumption of the external circuit for the two versions will be very different. The shift register version requires a data stream at 3.5 MHz during the scan period. Power consumption in the external circuit will be high in this period. With currently available devices the average power consumption in the external circuit may exceed 200mW.

The version using internal refreshing may typically operate for the majority of its time with the external circuit in a 'standby' mode. If, for example, the page of information is updated every 20 seconds, and this procedure takes 9600 data transfers at 3.5MHz, then the 'duty cycle' of the external electronics is only 0.014% and hence total power consumption will be very close to the 'standby' power. With a suitable choice of components this can be as low as 10 mW keeping total power consumption to below 100 mW.

Reverting attention from circuitry aspects to that of the physical construction of the cell, the metal pel pads on the silicon wafer must have specific optical properties, as well as specific electrical properties because they form the reflector that is required to back the liquid crystal layer. This may a conventional specular reflector provided, for instance by a conventional evaporated metal layer for instance of aluminium or silver.

A specular reflector does however provide certain restraints upon viewing angle and illumination conditions in order to avoid troublesome unwanted reflections. This problem is avoided by using a non-specular reflecting surface. If a diffusing surface is employed which approximates to a Lambertain diffuser a significant proportion of the light is lost through the operation of the window effect. This window effect arises because the scattering surface is in direct contact with a relatively high refractive index medium, and hence any light scattered into angles greater than the critical angle is unable directly to escape from the display. A preferred form of reflector is therefore one that is non-specular, but which scatters light predominantly into a relatively small solid angle centred on the specular reflection direction.Such a reflector can be prepared for instance by controlled evaporation of aluminium to provide a slow deposition rate typically of about 0.6 nm per second on to a hot substrate typically at about 280"C so as to promote grain growth in the deposit. A relatively thick deposit (2 to 3 microns) is required, and this introduces etching problems when using standard photolithographic technology to delineate the pads and the access lines, on the one hand, to avoid the piffall of overetching and thus destroying the electrical continuity of the access lines, and on the other hand to avoid the pitfall of underetching and thus failing to isolate one or more of the pads from an adjacent access line. Furthermore the prolonged processing time can given rise to the problem of aluminium penetration into the silicon over the transistor drain windows.These problems can be overcome by using two metallisations. The first metallisation layer can be a standard MOS process to form a complete set of picture element pads, row and column conductors and peripheral interconnections. An insulator is deposited in top of this, as a standard passivation layer. A second metallisation is then deposited and defined to form a set of picture pads only. These register with the existing set formed by the first metallisation. There is no need to open windows in the passivation before the second metallisation, as coupling between the two sets of picture pads can be purely capacitive. The primary advantages in this method arise because the optical properties of the first metallisation are of no consequence, and hence the manufacturer can use standard processing up to and including the passivation.The optical properties of the second metallisation are important, but this metallisation requires relatively low definition etching for which granularity of the metallisation presents less of a problem. With the two metallisations the percentage of active display area can be increased by making the top pad of the second metallisation, largerthan the bottom of the first.

The disadvantages are that the inclusion of the extra dielectric reduces the liquid crystal ON : OFF rms voltage ratio, and any overlap of the top pad beyond the bottom pad increases the dc bias between display pad and front electrode. This extra dielectric layer could be of Silox, but this is not preferred because of its relatively low dielectric constant and iack of conformity. Silicon nitride is better in both respects, but a polyimide layer is preferred.

Dyed phase change devices require close control of the display cell gap. The spacing between the pel pads and the front glass panel should have a tolerance of + 2 ym or better for average spacings in the range 10 to 12 Rm. This is conveniently achieved by a construction in which the silicon wafer forms the rear panel of the display. It is not mounted on any substrate, and its spacing from the front glass panel is maintained by the plastic edge seal, and a number of short 10 to 12 Fm diamater glass fibre particles that are distributed inside the display. By this means the silicon wafer can be made to conform to any curvature of the front glass panel, resulting in a close control of gap tolerance, provided that steps are taken to ensure that the silicon wafer tends to bow inwards (to trap the fibre spacers) rather than outwards, and the clamping jigs used do not exert too much pressure and crush the fibres.

An example of a suitable liquid crystal filling for the cell is the nematic guest/host mixture marketed by BDH under the designation D86 (black dye) in host E63. To this needs to be added a quantity of chiral additive, typically the cyano-biphenyl marketed by BDH under the designation CB15, to provide the requisite diolestric pitch, in this instance typically between 3 and 4 microns.

Claims (10)

1. A liquid crystal display cell which has a liquid crystal layer sandwiched between un upper transparent.

electroded plate and a lower plate formed by or carrying a semiconductor layer provided with a matrix array of semiconductor gates connected with an overlying matrix array of liquid crystal cell electrodes adjacent the liquid crystal layer, wherein the semiconductor layer includes circuitry enabling the determination of whether or not the charge held by the capacitance associated with each one of said liquid crystal cell electrodes of the matrix array is above or beneath a given threshold.

2. A liquid crystal display cell as claimed in claim 1, wherein the semiconductor layer includes circuitry enabling said determinations to be transferred serially in electrical form from said semiconductor layer.

3. A liquid crystal display cell as claimed in claim 2, wherein the semiconductor layer includes a set of shift registers and circuitry adapted to assemble input data therein for parallel transfer a line at a time to the individual capacitance associated with the liquid crystal cell electrodes of the matrix, and to effect the parallel transfer of said determinations a line at a time into said set of shift registers for serial read-out.

4. A liquid crystal display cell as claimed in claim 1,2, or 3 wherein the semiconductor layer includes circuitry adapted to use said determinations individually to refresh the charge held by the capacitance associated with each one of said liquid crystal call electrodes of the matrix array.

5. A liquid crystal display cell as claimed in claim 4, wherein each said refresh of each one of the liquid crystal cell electrodes of the matrix array is a refresh with the complement.

6. A liquid crystal display cell as claimed in claim 4, wherein everynth refresh (whereon is an integral number greater than unity) of each one of the liquid crystal cell electrodes of the matrix array is a refresh with the complement.

7. A liquid crystal display cell which has a liquid crystal layer sandwiched between an upper transparent electroded plate and a lower plate formed by or carrying a semiconductor layer provided with a matrix array of semiconductor gates connected with an overlying matrix array of liquid crystal cell electrodes adjacent the liquid crystal layer wherein the semiconductor layer includes circuitry enabling the use of said matrix array of gates and the capacitance associated with their associated liquid crystal cell electrodes as the storage elements of a dynamic random access memory in which the stored information is periodically complemented.

8. A liquid crystal display cell as claimed in any preceding claim, wherein the semiconductor layer is a single crystal slice of silicon.

9. A liquid crystal display cell as claimed in any preceding claim, wherein the liquid crystal display mode is dyed cholesteric nematic phase change.

10. A liquid crystal display cell substantially as hereinbefore described with reference to the accompanying drawings.