GB2113030A - Circuitry for reducing common mode signals - Google Patents

Circuitry for reducing common mode signals Download PDF

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Publication number
GB2113030A
GB2113030A GB08223988A GB8223988A GB2113030A GB 2113030 A GB2113030 A GB 2113030A GB 08223988 A GB08223988 A GB 08223988A GB 8223988 A GB8223988 A GB 8223988A GB 2113030 A GB2113030 A GB 2113030A
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United Kingdom
Prior art keywords
common mode
current
circuit
input
differential
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Withdrawn
Application number
GB08223988A
Inventor
Thomas Joseph Robe
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RCA Corp
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RCA Corp
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Publication date
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Publication of GB2113030A publication Critical patent/GB2113030A/en
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45008—Indexing scheme relating to differential amplifiers the addition of two signals being made by a resistor addition circuit for producing the common mode signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45066—Indexing scheme relating to differential amplifiers the resulting deducted common mode signal being added at the one or more inputs of the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45078—Indexing scheme relating to differential amplifiers the common mode signal being taken or deducted from the one or more inputs of the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45151—At least one resistor being added at the input of a dif amp

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Networks Using Active Elements (AREA)

Abstract

A circuit for substantially reducing common mode signal superimposed on differential signals includes first and second resistive dividers (10, 20) having input (11, 12), output (13, 14) and common (15) terminals. The differential mode (Vdm) plus common mode (Vcm) signals are applied to the divider input terminals and also to a further circuit (40) which is selectively responsive to the common mode signal to the exclusion of the differential mode signals. An output signal from the further circuit modulates the common terminal (15) of the dividers (10,20) to cancel the common mode signals at the output terminals (13, 14) of the dividers (10, 20). <IMAGE>

Description

SPECIFICATION Circuitry for reducing common mode signals This invention relates to circuitry for reducing common mode signals occurring with differential signals. An illustrative application is for improving the common mode rejection of differential input amplifiers.
Frequently it is necessary to sense relatively small differential mode signals in the presence of relatively large common mode signals. This is particularly troublesome when the sensing apparatus operates from supply potential which is substantially smaller than the amplitude of the common mode signal. Nominally a sensing device, e.g., amplifier, will only be sensitive to input signal variations with amplitudes occurring within the range of the supply potential. Large common mode signals superimposed on the input signal may a) lock the sensing apparatus in a particular state rendering it totally insensitive to the variations (i.e., the signal of interest), b) place the signal variations in an input signal range at which the sensing apparatus is undesirably nonlinear or c) damage the input circuitry of the sensing apparatus.In order to limit the detrimental effects of large common mode signals circuit designers include attenuators between the signal source and sensing apparatus to insure that the signal plus common mode component will not exceed supply potential. Unfortunately, the attenuators also attenuate the desired signal tending to reduce the overall sensitivity of the apparatus.
J. I. Brown in the article "Differential Amplifiers That Reject Common-Mode Currents" published in the December 1971 issue of the IEEE Journal of Solid State Circuits, described a differential sensing system comprising a first amplifier having differential input terminals. Signal is applied to the amplifier input terminals through attenuators, i.e., simple matched resistive dividers, a first end of each divider is arranged for receiving a respective input signal and the second end of each divider is connected to a reference potential. A second differential input amplifier is arranged to selectively sense the common mode signal at the differential input terminals of the first differential amplifier.The sensed common mode signal is amplified and inverted by the second amplifier and used to modulate the attenuator reference potential to cancel the common mode signal component appearing at the operational amplifier input terminals by negative feedback.
An advantage of the Brown circuit is that the input signal attenuation factor may be significantly reduced. A disadvantage of the Brown circuit is that the common mode feedback amplifier must have relatively high gain. As a result the amplifier must be phase compensated to insure stability with the result of limiting the frequency response of the common mode compensation.
A second solution to the high common mode signal problem is exhibited in the Fairchild Semiconductor 9613 "Dual Differential Line Receiver". This circuit selectively senses the common mode signals at the input terminals of the attenuators and applies compensating shunt current to the respective attenuator output terminals. Since the common mode signals are sensed before being attenuated the gain of the common mode amplifier need not be as large as required in the Brown arrangement though phase compensation is still required. The relaxed gain requirement in the 9613 Fairchild circuit should enhance the frequency response of the common mode rejection.
A disadvantage of the Fairchild 9613 circuit is that it utilizes two separate common mode feedback amplifier circuits. Unless the two common mode feedback circuits have identical response characteristics they will tend to generate a differential signal between the attenuator output terminals responsive to common mode input signals. This phenomenon will adversely affect the sensitivity or performance of the circuit to which the common mode compensated signal is applied. In addition, the phase compensation limits the useful common mode rejection bandwidth.
According to the present invention, there is provided a circuit for reducing a common mode signal occurring with differential mode signals comprising: first and second similar attenuator circuits each having an input for receiving said differential plus common mode signals, an output and a common terminal, and circuit means having first and second input connections to the input terminals of said first and second attenuator circuits respectively, and an output connection to the common terminal of said first and second attenuator circuits for producing at the output connection such signal that the differential mode signal substantially free of said common mode signal is available between said output terminals of the attenuators, wherein said circuit means is selectively responsive to common mode signal at said first and second input connections and substantially non-responsive to differential mode signals thereat for producing at said output connection a signal proportional to said common mode signal and substantially antiphase therewith.
An embodiment of the circuit includes first and second similar attenuators having respective input terminals for receiving input signal, respective output terminals at which common mode signal is substantially eliminated and respective common terminals connected to a variable reference potential.
First and second similar resistors are respectively connected between the input terminals of the first and second attenuators and an input terminal of a current to voltage converter (IVC) which input terminal is conditioned to remain at a substantially fixed potential. Currents produced at the IVC input terminal by common mode input potentials are additive creating a finite input signal to the IVC.
Differential input potentials produce currents which cancel each other at the IVC input terminal, thus the IVC is selectively responsive to common mode potentials. The IVC produces a potential proportional to the common mode input current and phase inverted with respect to the common mode input potential. The IVC output potential is applied to modulate the attenuator reference potential thereby to reduce common mode potentials at the output terminals of the attenuators. In the embodiment, the common mode signal is applied to compensate an attenuated common mode signal (at the attenuator output terminals) and the common mode voltage gain between the attenuator input terminals and the IVC output terminal is less than unity obviating phase compensation with its concomitant reduction in common mode bandwidth.In addition, since the compensating signal is generated in a single circuit fewer circuit elements are required to be matched thereby easing constraints on circuit manufacture.
For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made by way of example, to the accompanying drawing the only figure of which illustrates a circuit for reducing common mode signals occurring with differential mode signals in combination with a differential amplifier.
In the drawing, differential mode signals Vdm having common mode signal Vcm superimposed thereon are to be applied to the input terminals of the differential amplifier circuit 30. The use of the amplifier circuit 30 is for illustrative purposes and may be substituted by other circuits characterized by having differential input terminals and being responsive to differential signals. It will be presumed that the amplitude of the common mode signals exceeds the range of potentials for which the amplifier 30 will be responsive or that the amplifier 30 exhibits poor common mode rejection etc. so that the common mode input levels applied to the amplifier input terminals must be reduced.
The circuit for reducing common mode signals accompanying differential mode signals of interest comprises first and second attenuators 10 and 20, sensing resistors RS1 and RS2 and a current-tovoltage converter IVC 40.
A first signal including the common mode signal Vcm and the differential mode signal of interest Vdm+ is applied to the input terminal 11 of attenuator 1 0. A second signal including the common mode signal Vcm and the differential mode signal of interest Vd,,(-) is applied to the input terminal 12 of attenuator 20. By definition the common mode signals applied to terminals 11 and 12 are in phase and of equal amplitude. The differential signals are designated with particular polarities only for the purpose of analysis, it being appreciated that in general the differential signal is a time varying AC signal.
The input signals appear at the attenuator output terminals 1 3 and 14 reduced by the factor RJ(Ra+Rb) where Ra and Rb are the resistance values of the resistors Rai, Rbl and Ra2, Rb2 forming the respective attenuator circuits 10 and 20. For the condition that the common terminals 1 5 of the attenuator circuits are connected to a fixed reference potential, the common mode and the differential mode signals are reduced by the same factor. If the common mode signals are excessive, the attenuation factor required to condition the applied signals to be in the linear input range of the amplifier may render the differential signals undesirably small.However, by modulating the reference potential to which the common terminals 1 5 of the attenuators are connected with a signal which is 1 80 degrees out of phase with the common mode signal, the attenuation factor may be reduced while achieving common mode rejection in excess of the attenuation factor. If the reference potential is modulated by a signal equal to (--)P Vcrn (where 5 is a proportionality constant) it can be shown by nodal analysis that the signal V0 occurring at the attenuator output terminals will be Vo="dm RJ(Ra+Rb)+vcm((RbiBRa)/Ra+Rb) (1) By designing p=RJRa theoretically the common mode signal can be completely eliminated.
The attenuator reference signal, is generated by resistors RS1 and RS2 respectively connected to input terminals 11 and 1 2 which selectively provide a signal current at their interconnection 1 6 proportional to the common mode signal and to the exclusion of the differential mode signal. The common mode current signal is converted by circuit 40 to an output potential at terminal 1 7 which is applied to the common attenuator terminal 1 5.
The circuit 40 input terminal 1 8 to which resistors RS 1 and RS2 are connected is a point of substantially fixed potential. In the illustrative circuit, this potential is equal to the sum of the baseemitter potentials of transistors T1 and T2. This potential may be increased by including a small degeneration resistor in the emitter circuit of transistor T1. If such an emitter resistor is included in the emitter circuit of transistor T1 it may be advantageous to include similar degeneration resistors in the emitter circuits of transistors T3 and T4.
For the purposes of analysis assume that the potential at terminal 1 8 is zero. (This assumption has no effect on the AC analysis of the circuit. The fact that the potential is actually 2Vba need only be taken into account to establish the dc bias voltages which appear at terminals 1 3 and 14 for the particular application in which the circuit is utilized).In light of the foregoing assumption the current is flowing into terminal 1 8 is given by Ils=("cm+"dm(+))/RS 1 +(Vcm+Vdm())/RS2 (2) assuming Rs1=Rs2=Rs and Vdm(+)=()Vdm() by virtue of the normal definition of differential mode signals, then equation (2) reduces to 118=2 Vcm/R5. (3) It can be seen from (3) that the input current to circuit 40 contains only common mode signal components.
Transistors T1 and T2 of circuit 40 form the master section of a current mirror. Transistor T3 is a first slave section of the current mirror and transistor T4 a second slave section of the current mirror.
The input current l,s is conducted in the collector-emitter circuit of transistor T1 and this current is mirrored in the collector-emitter circuit of transistor T3 and in the collector emitter circuit of T4. The value of the current conducted in the collector circuit of T3 is nominally equal to ()I,s. This current develops a potential across resistor R8 which is translated to output terminal 1 7 by virtue of the emitter follower action of transistor T5 which has its base electrode connected to the interconnection of resistor R8 and the collector electrode of transistor T3 and its emitter electrode connected to terminal 17.
Slave transistor T4 operates as an active pull down for terminal 1 7 to enhance circuit response time. Transistor T4 and T5 operate in push-pull fashion. It should be appreciated that transistor T4 may be replaced by a resistor connected between terminal 17 and ground (a passive pull-down).
The voltage gain, Gcm, of the common mode circuit, from terminals 11, 12 to terminal 1 5 can be shown to be equal to Gcm=2Rs/Rs=p (4) where R2 is the resistance value of the sensing resistors RS1 and RS2. By designing 2RS/RS=RJRa and choosing Ra greater than Rb for complete cancellation of the common mode signal the gain p of the circuit 40 will be less than unity for all attenuators having an attenuation factor greater than one-half, Under these conditions the circuit will be stable at all frequencies and phase compensation is unnecessary. Eliminating phase compensation requirements, i.e., the need for a relatively large valeud capacitance has a two-fold advantage.First the bandwidth of the common mode circuit is significantly enhanced relative to currently available circuits. Secondly the present circuit is highly conductive to realization in integrated circuit form.
The degree of common mode rejection obtainable is dependent upon matching the attenuators and the respective resistor ratio's affecting the common mode gain requirements. A small mismatch between the sensing resistors RS1 and RS2 will cause differential mode signal current to be applied to circuit 40. The differential mode current due to the mismatch will produce a small common mode signal at the attenuator output terminals 1 3 and 14. It can be shown, however, that the effect of the sensing resistor mismatch will be less than the percentage mismatch ARRs by the common mode gain factor which is less than unity. The percentage error in rejection of the common mode signal due to a sensing resistor mismatch will be one half the percentage mismatch ARS/R5.
Since the percentage of component mismatch can be maintained at nominally small values (in both discreet and modern integrated circuits) and since the circuit arrangement inherently reduces the effects of such mismatches, relatively good common mode rejection can be achieved without the inclusion of variable components, e.g., a potentiometer between RS1 and RS2, to compensate for component mismatches.

Claims (8)

Claims
1. A circuit for reducing a common mode signal occurring with differential mode signals comprising: first and second similar attenuator circuits each having an input for receiving said differential plus common mode signals, an output and a common terminal and circuit means having first and second input connections to the input terminals of said first and second attenuator circuits respectively, and an output connection to the common terminal of said first and second attenuator circuits for producing at the output connection such signal that the differential mode signal substantially free of said common mode signal is available between said output terminals of the attenuators, wherein said circuit means is selectively responsive to common mode signal at said first and second input connections and substantially nonresponsive to differential mode signals thereat for producing at said output connection a signal proportional to said common mode signal and substantially antiphase therewith.
2. A circuit according to Claim 1 wherein the proportionality factor is less than unity.
3. A circuit according to Claim 1 or 2, wherein each of said first and second attenuator circuits comprises a resistive divider having a first resistor connected between its input and output terminals and a second resistor connected between its output and common terminals.
4. A circuit according to Claim 1, 2 or 3 wherein said input connections of the circuit means comprise means.
connected to the input terminals of said first and second attenuator circuits for producing a current proportional to the common mode signals substantially to the exclusion of a differential mode current component, and the circuit means comprises a current to voltage converter responsive to said common mode signal current for generating a voltage proportional to said current and with substantially 1 80 degree phase relation to said current at the output connection thereof.
5. A circuit according to Claim 4 wherein the means for producing a current proportional to the common mode signal comprises first and second similar sensing resistors having respective first ends connected to a point of substantially fixed potential and respective second ends connected to the input terminals of the first and second attenuator circuits respectively.
6. A circuit according to Claim 4 or 5 wherein the current to voltage converter comprises: a current mirror having an input terminal connected to receiving said current proportional to the common mode signals and having an output terminal; a resistor connected between said current mirror output terminal and a point of supply potential; and transistor me connected to apply to the output connection of the converter, as said voltage proportional to said current, a voltage related to the voltage across the said resistors
7. A circuit for reducing a common mode signal substantially as hereinbefore described with reference to the drawing.
8. A circuit according to any preceding claim further comprising a differential amplifier having differential inputs coupled to the respective outputs of the attenuator circuits.
GB08223988A 1981-12-31 1982-08-20 Circuitry for reducing common mode signals Withdrawn GB2113030A (en)

Applications Claiming Priority (1)

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US33616981A 1981-12-31 1981-12-31

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GB2113030A true GB2113030A (en) 1983-07-27

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GB08223988A Withdrawn GB2113030A (en) 1981-12-31 1982-08-20 Circuitry for reducing common mode signals

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JP (1) JPS58117707A (en)
DE (1) DE3231850A1 (en)
FR (1) FR2519489A1 (en)
GB (1) GB2113030A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0551530A1 (en) * 1991-12-16 1993-07-21 ALCATEL BELL Naamloze Vennootschap Amplifier biasing circuit suitable for a ring-trip detection system
EP1257053A1 (en) * 2001-05-11 2002-11-13 Telefonaktiebolaget L M Ericsson (Publ) Differential signal transfer circuit
US10110175B1 (en) 2017-05-19 2018-10-23 Qualcomm Incorporated Preventing distortion in a differential power amplifier

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3713376A1 (en) * 1987-04-21 1988-11-10 Sgs Halbleiterbauelemente Gmbh COMPARATOR WITH EXTENDED INPUT CURRENT VOLTAGE RANGE

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0551530A1 (en) * 1991-12-16 1993-07-21 ALCATEL BELL Naamloze Vennootschap Amplifier biasing circuit suitable for a ring-trip detection system
AU658462B2 (en) * 1991-12-16 1995-04-13 Alcatel N.V. Amplifier biasing circuit
EP1257053A1 (en) * 2001-05-11 2002-11-13 Telefonaktiebolaget L M Ericsson (Publ) Differential signal transfer circuit
US6696890B2 (en) 2001-05-11 2004-02-24 Telefonaktiebolaget Lm Ericsson (Publ) Differential signal transfer circuit
US10110175B1 (en) 2017-05-19 2018-10-23 Qualcomm Incorporated Preventing distortion in a differential power amplifier
WO2018212900A1 (en) * 2017-05-19 2018-11-22 Qualcomm Incorporated Preventing distortion in a differential power amplifier

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Publication number Publication date
DE3231850A1 (en) 1983-07-07
JPS58117707A (en) 1983-07-13
FR2519489A1 (en) 1983-07-08

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