GB2111780A - Improvements in or relating to amplifier systems - Google Patents
Improvements in or relating to amplifier systems Download PDFInfo
- Publication number
- GB2111780A GB2111780A GB08234901A GB8234901A GB2111780A GB 2111780 A GB2111780 A GB 2111780A GB 08234901 A GB08234901 A GB 08234901A GB 8234901 A GB8234901 A GB 8234901A GB 2111780 A GB2111780 A GB 2111780A
- Authority
- GB
- United Kingdom
- Prior art keywords
- capacitance
- node
- operatively coupled
- terminal
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
Abstract
In a circuit for compensating the offset voltage of an operational amplifier (301) the output voltage of the amplifier is sampled and stored on a first capacitor (C1) during a first interval. The first capacitor is reversed in polarity and coupled to a second capacitor (C2) to permit charge redistribution therebetween during a second interval. The voltage on the second capacitor is applied to the noninverting input terminal of the amplifier. <IMAGE>
Description
SPECIFICATION
Improvements in or relating to amplifier systems
This invention relates to amplifier systems.
In general, an operational amplifier is a differential amplifier having inverting and noninverting input terminals and a single output terminal. Such an amplifiertypically exhibits an offset voltage in that when the differential voltage on the two input terminals is zero, the voltage at the output terminal does not go to zero volts, as it should in the ideal case, but to some offset voltage. This offset voltage is caused primarily by a mismatch of the input transistors of the amplifier. If this offset voltage cannot be tolerated an appropriate differential input voltage, called the input offset voltage, must be applied to the input terminals of the amplifier to compensate the mismatch and eliminate the offset voltage on the output terminal.
In many applications for operational amplifiers it is necessary or desirable to substantially eliminate the offset voltage. One such application, for example, is where the operational amplifier is used in a digitalto-analog converter in which it is desirable to maintain the error introduced by the offset voltage to be less than a fraction of the least-significant bit.
Another such application is where the operational amplifier is used as a comparator in an analog-todigital converter and the accuracy of conversion is largely determined by the error introduced by the offset voltage of the amplifier performing the comparator function. Furthermore, in many applications in which the operational amplifier is dc coupled, it is also necessary or desirable to substantially eliminate any dc level on the input signal.
Although various circuit arrangements are known for providing continuous feedback compensation of the offset voltage, such arrangements typically require complex circuitry and, therefore, are not suited for use in large scale integration (LSI) circuits. Other known offset compensation circuits which use switched capacitors for periodically sampling and storing the input offset voltage of an amplifier and subsequently subtracting the stored offset voltage from the input voltage are far simpler to implement and provide more accurate compensation. Switched-capacitor offset compensation circuits are particularly suited for LSI circuit applications, since the capacitors and analog switches required for their implementation are available in several LSI technologies. Furthermore, such circuits generally require relatively small chip areas.
The invention will be described by way of example with reference to the accompanying drawings, in which:
Figures land 2 are schematic diagrams of a known amplifier system having a sampled-data offset compensation circuit and illustrate the system during the reset and transmit intervals, respectively;
Figure 3 is a schematic diagram of an amplifier system embodying the invention;
Figure 4 illustrates exemplary waveforms of clock signals 1 and 2; Figure 5 is a schematic diagram of another amplifier embodying the invention; and
Figure 6 is a schematic diagram of a comparator system embodying the invention.
A typical prior art switched-capacitor offset compensation circuit is shown in Figures 1 and 2 in its two basic operating conditions. The amplifier 100 includes an operational amplifier 101 having inverting and noninverting input terminals 102 and 103 and an output terminal 104, a capacitor C, and five switches S1 to S5. The switches are generally insulated-gate field effect transistors (IGFETs) driven by appropriate clock signals. The impedances Z1 and
Z2 determine the voltage gain of the amplifier.
The amplifier is required to operate in the sampled data mode by alternating between a reset condition shown in Figure 1, when the output offset voltage is sampled and stored, and a transmit condition shown in Figure 2, when the input signal is sampled and an appropriate output signal is provided.
In the reset condition S1 is open to disconnect in the input signal from inverting terminal 102 of the amplifier, S2 is closed to set the voltage gain of the amplifier to unity, S5 is closed to connect the noninverting inputterminal and one side ofCto ground, S3 is closed to connect the output terminal to the other side of C and S4 is open to disconnect the other side of C from ground. Thus, the voltage on the output terminal is sampled and stored on C.
In the transmit conditions, S1 is closed to connect the input signal to the amplifier, S2 is open to allow the amplifier gain to go to approximately -Z2/Z1, S3 is open to disconnect the other side of C from the output terminal, S4 is closed to connect the other side of C to ground and S5 is open to disconnect the noninverting input terminal from ground. Thus, the offset voltage stored on C, inverted and applied to the non inverting input terminal is effectively subtracted from the input signal received on the inverting input terminal.
One disadvantage of prior art switched-capacitor offset compensation circuits is that they are susceptible to charge feed-through errors in the input offset voltage. For example, in the prior art circuit of
Figures 1 and 2, the parasitic capacitance Cp5 associated with S5 causes feedthrough charge to be transferred to C when S5 opens, thus producing an error in the input offset voltage stored on C. To cancel this error, matching charge compensating switches and/or capacitors must be added to the circuit resulting in increased circuit complexity.
Another disadvantage of known switchedcapacitor offset compensation circuits is that they do not provide compensation for a dc level on the input signal. For example in the prior art circuit of Figures 1 and 2, a dc offset level on the input signal is not compensated by the input offset voltage stored on C.
Still another disadvantage of known switchedcapacitor offset compensation circuits is that such circuits cannot be used with operational amplifiers operating as comparators. Owing to the high gain of a comparator, the amplifier offset is apt to cause the output of the comparator to go to one of two reference voltages when the differential input voltage of the comparator is zero. Therefore, the input offset voltage of a comparator cannot be directly sampled at its output terminal.
Afurther disadvantage of known switchedcapacitor offset compensation circuits is that such circuits generally permit only sampled-data operation of the amplifier.
According to this invention an amplifier system includes a differential amplifier having noninverting and inverting input terminals and an outputterminal, a first capacitance, first means for selectively providing a voltage on the output terminal to the first capacitance, a second capacitance operatively coupled between one of the input terminals and a reference voltage terminal, and second means for selectively redistributing charge between the first capacitance and the second capacitance.
The combination of the first and second capacitances and the first and second means provides a feedback path which removes the rapidly varying signal components of the output voltage while passing the slowly varying offset components of the output voltage to an appropriate input terminal of the amplifier. Therefore the feedback voltage eventually converges to the input offset voltage plus the inverse of any dc level on the input signal.
This arrangement and method of operation provides improved cancellation of charge feed-through errors and any offsets on the input signal, permits continous operation of the amplifier system and may be used when the amplifier operates as a comparator.
Referring now to Figure 3 an amplifier system 300 is of the type which may be used, for example, as a subcircuit in an LSl circuit and includes an operational amplifier 301 having an inverting inputterminal 302, a noninverting input terminal 303, an output terminal 304, a feedback impedance Z1, and an input impedance Z2. An input signal is applied to the inverting input terminal through the input impedance.The offset compensation circuit includes a switched-capacitor network 308 having a capacitor C1 connected betwee nodes 305 and 306, a switch S1 for selectively connecting the output terminal to node 305, a switch S2 for selectively connecting node 305 to a reference voltage terminal 307, which in this example is ground, a switch S3 for selectively connecting node 306 to the reference voltage terminal, a capacitor C2 connected between the noninverting input terminal and the reference voltage terminal and a switch S4 for selectively connecting node 306 to the noninverting input terminal.The switches S1 to S4 are all metal-oxide-semiconductor (MOS) transistors and are operated by nonoverlapping clock signals 4)1 and 4)2 at a rate 1/T. Exemplary waveforms of 4)1 and 4)2 are shown in Figure 4.
During the interval when 4)1 is high, S1 and S3 are closed while S2 and S4 are open. Under these conditions, the voltage on the output terminal of the amplifier is sampled and stored on C1. During the interval when 4)2 is high, S1 and S3 are open while
S2 and S4 are closed. Under these conditions, C1 is reversed in polarity and connected in parallel with
C2, and a redistribution of charge takes place between the two capacitors. The switch S4 serves as a means for transferring charge between C1 and C2.
A sufficient time separation is provided between the 4)1 and 4)2 clock pulses to permit the switches in the network to operate in a break before make sequence.
The switched-capacitor network functions primarily as a low-pass filter/inverter which removes the rapidly varying signal components of the output voltage while inverting and providing the slowly varying offset components of the output voltage to the noninverting input terminal. Owing to the feedback action of the switched-capacitor network, after a sufficient number of cycles of 4)1 and 4)2 the voltage provided to the noninverting input terminal converges to a value which is approximately the input offset voltage of the amplifier plus the inverse ofanydc level on the input signal. Moreover, the effects of charge feed-through from the operation of
S1 and S3 are also substantially cancelled by the feedback action.
In order to ensure that the rapidly varying signal components of the output voltage are removed by the switched-capacitor network, it is advantageous to make the quantity C2T/C1 much larger (e.g., by a factor of ten) than the period of the slowest component of the input signal. Therefore, it is desirable to choose the value of C2 to be larger than that of C1 (e.g. C1 =0.5pf and C2=50pf).
Referring now to Figure 5, an amplifier system 500, in which references used to refer to components of the system of Figure 3 are also used here to refer to corresponding components, includes a switched capacitor network 308 similarto the one shown in
Figure 3 in that it includes a capacitor C1 connected between nodes 305 and 306, a switch S1 for selectively connecting the output terminal to node 305, a switch S2 for selectively connecting node 305 to reference terminal 307, a switch S3 for selectively connecting node 306 to the reference terminal, and a capacitor C2 connected between the noninverting input terminal and the reference terminal.However, selective charge redistribution between C1 and C2 takes place through circuitry comprising a switch S4 for selectively connecting node 306 to node 309, a shunt capacitor C3 connected between node 309 and the reference terminal, and a switched capacitor section connected between node 309 and the noninverting input terminal. The switched-capacitor section comprises a pair of switches S5 and S6 connected in series and a shunt capacitor C4 situated between the pair of switches. All switches in the network are MOS transistors operated by nonoverlapping clock signals 4)1 and 4)2, such as those represented by the waveforms of Figure 4.Switches
S1, S3 and S5 are closed when 4)1 is high, while switches S2, S4 and S6 are closed when 4)2 is high.
The switched-capacitor network of Figure 5, by virtue of having an additional switched-capacitor section, operates as a low-pass filterlinverter having improved cutoff characteristics over that of the network of Figure 3. Removal of the rapidly varying components of the output voltage by the network of
Figure 5 is ensured by making the quantity (C3/C1) (C21C4)T much larger (e.g. by a factor of ten) than the period of the slowest component of the input signal.
Therefore, it is desirable to choose the value of C3 to be significantly larger than that of C1, (e.g. C1 =0.5pf and 63=25of), and the value of C2 to be significantly larger than that of C4, (e.g. C4=0.5pf and C2=25pf), and to make the period, T, of the clock signals long. It will be noted that the capacitance ratios used in the switched-capacitor of Figure 5 need not be as large as that required for the network of Figure 3.
In some instances it may be desirable to use more than one additional switched-capacitor section in the charge redistribution means in order to obtain further improvements in the cutoff characteristics of the network and to permit the use of even smaller capacitance ratios. In such instances the switchedcapacitor sections are connected in cascade between node 309 and the noninverting input terminal, and each additional section except the one connected to the noninverting input terminal includes a second shunt capacitance situated between adjacent sections.It is desirable to choose the value of the second shunt capacitance in each section to be significantly larger than that of the shunt capacitance which is situated between the pair of switches in the section, and the value of C2 to be significantly larger than that of the shunt capacitance situated between the switches of the section connected to the noninverting input terminal. When more than one additional switched-capacitor section is used, the values of the capacitors in the network, the period of 4)1 and 4)2, and the gain of the operational amplifier must also be chosen so as to avoid instabilities in the amplifier system. The criteria for stability of an amplifier system with respect to the phase shift in its feedback loop and its gain characteristics are well known to one skilled in the art of amplifier design.
It will be noted that in the offset compensation arrangements shown in Figures 3 and 5, the input terminal of the amplifier need not be isolated from the signal source and reset to a reference voltage when the output voltage of the amplifier is sampled.
Therefore, the invention finds application in continuous as well as sampled-data operation of the amplifier.
Referring now to Figure 6, a comparator system 600 including an operational amplifier 601 having an inverting input terminal 602, a noninverting input terminal 603, and an output terminal 604 is operated as a comparator between power supply voltages of +V and -V applied to power supply terminals 608 and 609, respectively. The output terminal swings between substantially full power supply voltages.
The offset compensation circuit comprises a switched-capacitor network 605 having a capacitor C1 connected between node 606 and a reference voltage terminal 607, a switch S1 for selectively connecting the output terminal to node 606, a capacitor
C2 connected between the inverting input terminal and the reference voltage terminal and a switch S2 for selectively connecting node 606 to the inverting input terminal. A switch S3 connected between the noninverting input terminal and the reference voltage terminal is used for resetting the noninverting input terminal. Switches S1, S2 and S3 are all MOS transistors operated with nonoverlapping clock signals 4)1 and 4)2 at a rate 1/T such as those represented by the waveforms of Figure 4.Switches S1 and S3 are closed when 4)1 is high while switch S2 is closed when 4)2 is high.
Operation of the offset compensation circuit is now explained. Assume for purposes of explanation that the comparator has a positive input offset voltage and C2 is initially discharged. When S1 and S3 first close, the output terminal goes to -V, and C1 is charged to -V. When S2 subsequently closes, the charge on Cl, which is equal to -C1V, is redistributed between C1 and C2. Thus, after the first cycle of 4)1 and 4)2 C2 acquires a voltage of -C1V/(C1 +
C2) which is applied to the inverting input of the comparator.Assuming again for purposes of explanation that the value of C2 is much greater than that of Cl, the differential input voltage applied to the comparator after the first cycle of 4)1 and 4)2 is approximately C1V/C2. If this voltage is less than the input offset voltage, the output terminal remains at -V, and after the next cycle of 4)1 and 4)2 the voltage across C2 will be approximately -2C1V/C2.Thus, after cycles of 4)1 and 4)2 the voltage across C2 will increase to approximately -nC1V/C2, and the differential input voltage applied to the comparator is approximately nC1V/C2. If this voltage exceeds the input offset voltage for the first time, the output terminal will go from -V to +V, and after the next cycle of 4)1 and 4)2 the differential input voltage will be approximately (n-1)C1V/C2. Since this voltage is less than the comparator offset voltage, the output terminal will again go to -V. Therefore once a voltage whose magnitude is within C1V/C2 of the input offset voltage is stored on C2, the differential input voltage will alternate every cycle of the clock signal between (n-1)C1V/C2 and nC1V/C2.The time required to initially store a voltage of that magnitude is nT 2: (C/2C1 )(v0/v)T, where VO is the input offset voltage. The error in the store input offset voltage is I
C1V/C2. This error can be made arbitrarily small by increasing the ratio of C2 to C1. However, increasing the capacitance ratio also increases the time required to initially store the input offset voltage.
It will be noted that in the offset compensation arrangement of Figure 6, the voltage on C2 is applied to the inverting input terminal of the amplifier.
Therefore the polarity of C1 and C1 and C2 have the same need not to be inverted before being coupled to C2 for charge redistribution.
Using an analysis similar to the one given above, it may be shown that the arrangement illustrated in
Figure 6 provides compensation for negative as well as positive offsets. Moreover, the comparator, which may be strobed or unstrobed, need not be operated between substantially equal power supply voltages of opposite polarity.
It will be understood by those skilled in the art that various modifications and alterations may be made to the described embodiments. For example, while the embodiments use MOS devices as switches, the invention may be performed with bipolar switching devices. Although the apparatus is particularly suited for LSI circuit applications, it may not always be desirable to integrate all components of such apparatus on a single chip. For example, in the arrangements illustrated in Figures 3 and 6, it is advantageous, as discussed above, for C2 to have a relatively high value. Since a high valued capacitor requires a large chip area, it may be desirable to use a discrete off-chip capacitor for C2.
Claims (7)
1. An amplifier system including a differential amplifier having noninverting and inverting input terminals and an output terminal, a first capacitance, first means for selectively providing a voltage on the output terminal to the first capacitance, a second capacitance operatively coupled between one of the input terminals and a reference voltage terminal, and second means for selectively redistributing charge between the first capacitance and the second capacitance.
2. A system as claimed in claim 1 wherein the first capacitance is operatively coupled between a first and a second node, the one input terminal is the noninverting input terminal, the first means includes a first switch operatively coupled between the output terminal and the first node, and a second switch operatively coupled between the second node and the reference voltage terminal, and the second means includes a third switch operatively coupled between the first node and the reference voltage terminal, and charge transfer means operatively coupled between the second node and the noninverting input terminal, there being provided means for causing the first and second switches to be closed during a first interval and open during a second interval, and the third switch to be open and closed during the first and second intervals respectively.
3. A system as claimed in claim 2 wherein the charge transfer means includes a fourth switch operatively coupled between the second node and the noninverting input terminals, the causing means serving to open and close the fourth switch during the first and second intervals respectively, and the second capacitance is significantly larger than the first capacitance.
4. A system as claimed in claim 2 wherein the charge transfer means includes a fourth switch operatively coupled between the second node and a third node, a third capacitance operatively coupled between the third node and the reference voltage terminal and being significantly larger than the first capacitance, one or more switched-capacitor sections coupled in cascade between the third node and the noninverting input terminal, the or each section having a pair of switches coupled in series and a first shunt capacitance situated between the pair of switches, the second capacitance being significantly larger than the first shunt capacitance of the switched-capacitor section coupled to the noninverting input terminal, and, where there is more than one such section, a second shunt capacitance situated between adjacent sections, the second shunt capacitance being significantly larger than the first shunt capacitance, and the causing means serves, for the or each section, to close and open one of the switches of the pair during the first and second intervals respectively, and to open and close the other of the switches during the first and second intervals respectively.
5. A system as claimed in claim 1 wherein the first capacitance is operatively coupled between a first node and the reference voltage terminal, the one input terminal is the inverting input terminal, the first means includes a first switch operatively coupled between the output terminal and the first node, and the second means includes a second switch operatively coupled between the first node and the inverting input terminal, there being provided means for causing the first and second switches to be closed and open respectively during a first interval, and open and closed respectively during a second interval.
6. A system as claimed in claim 5 including a third switch coupled between the noninverting input terminal and the reference voltage terminal, the causing means serving to close the third switch during the first interval and to open it during the second interval.
7. An amplifier system substantially as herein described with reference to Figure 3, 5 or 6 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US33158481A | 1981-12-17 | 1981-12-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2111780A true GB2111780A (en) | 1983-07-06 |
Family
ID=23294561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08234901A Withdrawn GB2111780A (en) | 1981-12-17 | 1982-12-07 | Improvements in or relating to amplifier systems |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS58111414A (en) |
| DE (1) | DE3246176A1 (en) |
| FR (1) | FR2518848A1 (en) |
| GB (1) | GB2111780A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2521369A1 (en) * | 1982-02-08 | 1983-08-12 | Western Electric Co | AMPLIFIER CIRCUIT COMPRISING A CANCELING SHIFT VOLTAGE |
| US4564821A (en) * | 1984-10-01 | 1986-01-14 | Motorola, Inc. | Offset cancelling AC level detector using an oscillator |
| EP0176915A2 (en) * | 1984-09-26 | 1986-04-09 | Siemens Aktiengesellschaft | Circuit arrangement for offset correction of an integrated operational amplifier |
| EP0506081A1 (en) * | 1991-03-27 | 1992-09-30 | Kabushiki Kaisha Toshiba | Voltage amplifier circuit and image pickup device including the voltage amplifier circuit |
| EP0818877A2 (en) * | 1996-07-12 | 1998-01-14 | Siemens Aktiengesellschaft | Offset compensation circuit |
| CN102185812A (en) * | 2011-05-13 | 2011-09-14 | 吉林大学 | DC (direct-current) offset filtering circuit |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3304814C2 (en) * | 1983-02-11 | 1985-06-27 | SGS-ATES Deutschland Halbleiter-Bauelemente GmbH, 8018 Grafing | Differential amplifier |
| US4841252A (en) * | 1987-08-05 | 1989-06-20 | Brooktree Corporation | System for compensating for offset voltages in comparators |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4255715A (en) * | 1979-08-27 | 1981-03-10 | Gte Laboratories Incorporated | Offset correction circuit for differential amplifiers |
| US4306196A (en) * | 1980-01-14 | 1981-12-15 | Bell Telephone Laboratories, Incorporated | Operational amplifier with offset compensation |
-
1982
- 1982-12-07 GB GB08234901A patent/GB2111780A/en not_active Withdrawn
- 1982-12-09 FR FR8220642A patent/FR2518848A1/en not_active Withdrawn
- 1982-12-14 DE DE19823246176 patent/DE3246176A1/en not_active Withdrawn
- 1982-12-16 JP JP57219336A patent/JPS58111414A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2521369A1 (en) * | 1982-02-08 | 1983-08-12 | Western Electric Co | AMPLIFIER CIRCUIT COMPRISING A CANCELING SHIFT VOLTAGE |
| EP0176915A2 (en) * | 1984-09-26 | 1986-04-09 | Siemens Aktiengesellschaft | Circuit arrangement for offset correction of an integrated operational amplifier |
| EP0176915A3 (en) * | 1984-09-26 | 1987-10-28 | Siemens Aktiengesellschaft Berlin Und Munchen | Circuit arrangement for offset correction of an integrated operational amplifier |
| US4564821A (en) * | 1984-10-01 | 1986-01-14 | Motorola, Inc. | Offset cancelling AC level detector using an oscillator |
| EP0506081A1 (en) * | 1991-03-27 | 1992-09-30 | Kabushiki Kaisha Toshiba | Voltage amplifier circuit and image pickup device including the voltage amplifier circuit |
| US5311319A (en) * | 1991-03-27 | 1994-05-10 | Kabushiki Kaisha Toshiba | Solid state image pickup device having feedback voltage to amplifier |
| EP0818877A2 (en) * | 1996-07-12 | 1998-01-14 | Siemens Aktiengesellschaft | Offset compensation circuit |
| EP0818877A3 (en) * | 1996-07-12 | 1998-09-16 | Siemens Aktiengesellschaft | Offset compensation circuit |
| CN102185812A (en) * | 2011-05-13 | 2011-09-14 | 吉林大学 | DC (direct-current) offset filtering circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58111414A (en) | 1983-07-02 |
| DE3246176A1 (en) | 1983-06-30 |
| FR2518848A1 (en) | 1983-06-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |