GB2108351A - Image pick-up apparatus - Google Patents
Image pick-up apparatus Download PDFInfo
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- GB2108351A GB2108351A GB08214621A GB8214621A GB2108351A GB 2108351 A GB2108351 A GB 2108351A GB 08214621 A GB08214621 A GB 08214621A GB 8214621 A GB8214621 A GB 8214621A GB 2108351 A GB2108351 A GB 2108351A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
- H03G1/0029—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier using FETs
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/70—Circuitry for compensating brightness variation in the scene
- H04N23/76—Circuitry for compensating brightness variation in the scene by influencing the image signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
Abstract
A conventional solid state image sensing system produces signals is which are applied to a variable gain current amplifier 11, 12, 13, 14, characterised in that the gain is set (possibly automatically in accordance with overall scene brightness) by setting the currents produced by two gauged control current sources 22, 23. FET's may be used in place of the bipolar transistors shown. <IMAGE>
Description
SPECIFICATION
Image pick-up apparatus
This invention relates to gain-controlled ampii- fiers, and is more particularly directed to a solidstate image pickup device incorporating a gaincontrolled current amplifier for converting a relatively feeble video signal to a strong video output signal with a high signal-to-noise (S/N) ratio.
A solid-state image pickup element, such as an
MOS imager, generally provides a quite weak signal which must be amplified before being applied to a successive stage. This weak video signal is particu larlysusceptible to noise due to stray currents, shot noise, and the like. In an MOS imager, the video signal is provided as a differentiated current. This signal must be integrated to obtain an average value, but integration lowers the overall level of the video signal. Thus, the integrated signal has a rather low S/N ratio.
An external amplifier is conventionally provided to amplify the output signal and thereby convert it to a level suitable for further processing. Unfortunately, this external amplifier amplifies the noise along with the video signal, and, because it is external, also introduces noise. Consequently, the resulting video output signal has a further deteriorated S/N ratio.
Furthermore, the average level of the output signal from the image pickup element varies greatly with changes in brightness or color temperature of a scene to be televised. If the gain of the circuit connected to the pickup element is too high, the peak level becomes clipped and the signal waveform becomes distorted when a bright scene is being shot. As a result, the picture becomes washed out, and lacks detail in its bright portions. On the other hand, if the gain of the circuit is too low, the average signal level is reduced and the S/N ratio can become unacceptably low when a dark scene is shot. Obviously, both of the foregoing situations are undesirable.Consequently, it would be advantageous to include a gain control element in the video signal processing circuitry so that the gain of the output circuitry associated with the pickup element changes in accordance with the brightness of the picture being picked up.
Unfortunately, conventional gain-controlled amplifiers generally are suitable only for amplifying a continuous analog signal, and no such circuit has been previously proposed which can control the amplitude of a sampled, time-shared current signal such as the output of an MOS imager or other similar image pickup device.
It is an object of this invention to provide video image pickup apparatus generating a strong video signal representing a scene with a high signal-tonoise ratio, the level of which signal is controlled in accordance with brightness conditions ofthe scene.
It is another object of the invention to provide video image pickup apparatus incorporating a current amplifier therein to avoid the aforementioned problems that occur when an external amplifier is used to amplify the video signal.
It is a more specific object to provide video image pickup apparatus employing a gain-controlled current amplifier of a type suitable for amplifying a sampled, time-shared current signal typical of the output of a solid-state imager.
According to an aspect of this invention, image pickup apparatus are provided in which there are a plurality picture element units, each formed of a photosensitive member generating a quantum of electrical charge depending on the amount of light falling thereon and an electrically controlled gating circuit for transmitting the generated amount of charge in response to scanning pulses applied thereto, with the picture element units being disposed in a two-dimensional array of horizontal rows and vertical columns. Scanning signal generators sequentially provide horizontal and vertical scanning pulses to the gating circuits of the respective picture element units, so that the electrical charges are presented, in row-by-row sequence, to an output circuit to produce a video signal.In embodiment of this invention, the output circuit includes a gaincontrolled current amplifier circuit formed of an input transistor to which the input signal current is applied and an output transistor at which an amplified output signal current appears. The gain of the circuit, i.e., the ratio of the output signal current to the input signal current, is controlled by a controllable element coupled to the input and output transistors so that the current gain can be selectively controlled, in accordance will illuminating conditions of a scene being shot by means of a control signal applied thereto.
In several embodiments the gain-controlled amplifier includes first, second, third, and fourth transistors each having a first and a second currentcarrying electrode and a control electrode, with the second and third transistors having their first current-carrying electrodes coupled together to a point of voltage, having their control electrodes coupled together to the first current-carrying electrode of the first transistor, and having their second current-carrying electrodes coupled to the control electrodes of the first and fourth transistors, respectively. The first and fourth transistors have their second current-carrying electrodes coupled together to another point of voltage.A current source supplies a constant current to the first current-carrying electrode of the first transistor, and a load device is coupled to the first current-carrying electrode of the fourth transistor. An adjustable current source supplies adjustable constant currents to the second current-carrying electrodes of the second and third transistors. In these embodiments, the input signal current is applies to the first current-carrying electrode of the first transistor and the output signal current appears at the first current-carrying electrode of the fourth transistor.
In other embodiments, the gain controlled current amplifier can include first, second, and third current mirror circuits, each having an input transistor device and an output transistor device. Current sources provide substantially constant currentto the input transistor devices of the first and second current mirror circuits; while the output transistor devices thereof are respectively coupled to the output and input transistor devices of the third current mirror circuit. First and second resistive elements, which can include the source-to-drain resistances of
MOS transistors, are coupled to the input transistor devices ofthefirst and second current mirror circuits.Third and fourth resistive elements, which can also include MOS transistors, are adjustable by means of a gain control voltage applied thereto, and are coupled to the output transistor devices of the first and second current mirror circuits. A load device is coupled to the output transistor device of the First current mirror circuit Here, the input signal cu rent is applied to the input transistor device of the iirst current mirror circuit and the output sigllal current appears at the output transistor of the first current mirror circuit.
In many embodiments, the load device can include a load capacitor having one plate coupled to the second current-carrying electrode of the second transistor and another plate coupled to a reference point, and a pre-charging transistorfor charging the one plate of the load transistor during occurrences of a switching pulse.
The above and many other objects, features, and advantages of this invention will become apparent from the ensuing description of several preferred embodiments thereof, which isto be considered in connection with the accompanying drawings.
Fig. lisa schematic diagram of a conventional solid-state image sensor.
Figs. 2A to 2F are waveform charts of scanning pulse signals used in conjunction with the image sensor of Fig. 1.
Fig. 3 is a diagram of a first embodiment of the improved image sensor according to the present invention.
Fig. 4is a schematic diagram of a pertinent portion of the improved image sensor according to a second embodiment thereof.
Fig. 5 is a schematic diagram of a pertinent poriton of the improved image sensor according to a third embodiment thereof.
Figs. 6A to 6F are waveform charts for explaining operation of the third embodiment.
Figs. 7 and 8 are schematic diagrams illustrating fourth and fifth embodiments of this invention, respectively.
Fig. 9 is a schematic diagram illustrating a sixth embodimentofthis invention.
Figs. 1 OA to 1 OF are waveform charts for explaining operation of the sixth embodiment of this invention.
Figs. 11 and 13 are schematic diagrams of a pertinent portion of seventh, eighth, and ninth embodiments.
Initially, for purposes of background and to emphasize the advantages of this invention, a conventional solid-state image sensor will be described with reference to Fig. 1.
In this conventional image sensor, an MOS (Metal - Oxide- Semiconductor) imager 1 is constituted by a plurality of picture element units S011 to Serum disposed in a two-dimensional, or X-Y array formed of m horizontal rows by n vertical columns.
A horizontal scanning circuit 2 provides successive horizontal gating pulses H1 (Fig. 2A), H2 (Fig. 2B),..
to #Hm (Fig. 2C) to the picture element units of each horizontal row in turn. At the same time, a vertical scanning circuit 3 provides interlaced odd and even vertical gating pulses #v01 (Fig. 2D), #v02 (Fig. 2E) ....
VE1, #VE2,....#VEn. The interlacing of the vertical gating pulses corresponds to the interlacing of a television image, in which a field of odd lines and a field of even lines alternate.
In this image sensor, each of the m picture element units S011, S012,....S01m for the first odd line are disposed in lines in the horizontal direction, and the picture elements units for the remaining lines are similarly disposed.
Each of the picture element units S011, S012,...,
S01m,...SEnm is formed of a photo diode D011, D012...
, D01M,...DEnm which can be a PN or PIN type, and an associated MOS gating transistor M011, M012,...,
M01M,...MEnm. The photodiodes have their cathodes connected in common to a target voltage source VT and have their anodes coupled to the source electrode of the associated MOS gating transistors Moll, M012,....M01m, MEnm.The drain electrodes of these transistors are connected to respective vertical transmitting lines Lv1, Lv2,....Lvm, for each vertical column (i.e., for each successive horizontal position) while the gate electrodes of the MOS gating transistors of each particular horizontal row are connected in common to an output of the vertical scanning circuit 3 to receive a particular scanning pulse #v01, Xv02 .... XVEn in accordance with the particular image line to be scanned. For example, the scanning signal #v01 of Fig. 2D is furnished to the gate terminals of the transistors Mo1, to M01M of the first odd horizontal row during a first horizontal scanning period.
The remaining odd lines and all of the even lines of the picture element units S011, S012....S01m,....SEnm are constituted in like manner.
Consequently, an odd field of video is generated in response to feeding of odd vertical scanning pulses #v01, #v02... - . . to the gate electrodes of the transistors M011, M012,....M01m; M021, M022....M02m in the sequential odd horizontal rows, and an even field of video is generated in response to feeding of even vertical scanning pulses #VE1, #-ve2.... XVEn to the gate electrodes of the transistors ME11, ME12... - .. - MEIM ..MEnm of the sequential even rows.
Each vertical transmitting line LV1, LV2,....LVm has associated with it a capacitance Cv for storing the electric charge passed by the gating transistors M011,
M011....M01m....MEnm in response to each particular vertical scanning pulses #V01, to #VEn, so that the capacitances Cv at any line interval hold the electrical charge generated in one particular horizontal row of picture element units S011 to S01m,...., SEn1 to SEnm
Each of the vertical transmitting lines LV1 to LVm also includes a respective MOS transistor M1, M2...
MM having a source electrode coupled to the associ
ated capacitance Cv, and having a gate electrode
coupled to a respective output of the horizontal
scanning circuit 2 to receive a particular horizontal
scanning pulse #H1, #H2....#Hm. The drain electrodes
of the MOS transistors M1 to M. are connected in
common to a horizontal output transmitting line LH.
A capacitance CH is associated with the horizontal transmission line LH, while a load resistor 4 of a value R, bridges between a DC voltage source Voc and the
horizontal transmitting line LH.
Here, the capacitances CH and Cv are shown as lumped values, but in practice they are substantially distributed over the respective transmitting lines LH and Lvi to Lvn.
The horizontal output transmitting line LH is also coupled to a gate electrode of an output MOS transistor 5 connected as a source follower and serving as an isolation stage, with its drain electrode connected to a drain potential Vdd and its source electrode connected to voltage source 6 and also to a pre-amplifier 7 to amplifythe video signal and provide the same to an output terminal 8.
In this MOS imager 1, light incident on the diode Doll to DEnm of each picture element unit S011 to SEnm causes the diodes to generate electron-hole pairs.
Consequently, a signal charge Os is stored between the gate and source electrodes of each respective
MOS gating transistor Mot, to MEnm. The size of each signal charge Qs depends on the strength of the light incident on the particular diode Dot, to DEnm.
Occurrence of the vertical scanning signals #V01, V02,....#VEn places at a high level all of the gate electrodes of the gating transistors Moll to M01m;
M021 to M02m;...; MEmt to MEnm for one particular horizontal row. As a result, all of the signal charges Qs for the picture element units S011 to S01m; S021 to
S02m;....SEn1 to SEnm of that particular row are gated to the capacitances Cv for the respective vertical transmission lines Lv, to Lvm.
As shown in Figs. 2Ato 2C, the horizontal scanning pulses tor to Hm go from iow to high levels at times t2,t3... to and return to their low levels so as not to overlap one another. However, each such scanning pulses #H1 to #Hm is of a sufficient length to transfer the charge From each capacitance Cv to the capacitance C,i.
As shown in Figs. 2D and 2E, the vertical scanning pulses ssyO, is high from a time t, until a later time t4, at which time the next vertical scanning pulses #V02 becomes high. In fact, all of the vertical scanning pulses fVOt to #VEn are provided in a non-overlapping fashion.
If it is assumed that the pulse width of each horizontal scanning pulse #H1 to Hm is T, the time t2 that the first scanning signal Hi is made high occurs a predetermined time after the time t, or t4 following the onset of each vertical scanning pulses #V01 to #VEn.
As aforementioned, each transmitting line LH and Lvi to Lvn has a respective capacitance CH and Cv; the
load resistor 4 has a resistance value RL. The signal charge Qs stored in each picture element unit SOt, to
SEnm generates a signal current i5 (Fig. 2F) to flow whenever the associated horizontal and vertical scanning pulses are high. For the charge QS011 of the
picture element S011, these pulses are both high from the times t2 to t2 (Fig. 2A). Thus, the signal current is associated with this particular picture element unit
S011 can be expressed.
The resulting output voltage Vout at the input to the preamplifier 7 becomes
Here, it is important that the time constant
RL(CV+CH) be sufficiently small that all of the charge
Qs is transferred during each on period (x = t2-t1) of the horizontal scanning pulses H1 to 4)Hn That is, for a value k defined by the equation RL(CV+CH)=#/k ............ (3) be rather larger than unity, for example k= 5.
The same requirement holds true for all the picture element units S011 to SEmn. For example, for the signal charge Qs012 of the picture element SO12, the output voltage Vout becomes
Thus, as each unit S011 to San. and SE11 to SEnm is sequentially scanned, its respective signal charge
QS011 to QSEnm and QSE11 to QSEnm flows through its associated vertical signal transmitting line LV1 to LVm, and then through the horizontal transmitting line LH and the load resistor 4 as a signal current is, which is used to derive the video signal as the output voltage Vout- However, it is clear from Fig. 2E and from equations (2) and (4) above that the output voltage Vout is a differential voltage, and cannot, with satisfactory results, be used directly as a stable input for a sample-hold or peak-hold circuit. Therefore, it is generally necessary to produce an average, or mean value of the output voltage Vaunt by use of an integrator or low-pass filter. This results in an average output voltage [Vout]mean as expressed
Here, k is set at K =1 5 as was true in equation (3) so that the factor e-k can be disregarded.If the signal charge Qs is thought of as being the product of the signal voltage Vs times the gate-to-source storage capacitance Co' of a particular picture element unit S, and the discharge time thereof is represented by the expression k3RL(CV+CH from equation (3), then the average output voltage [Voujmean becomes
As k is large compared to unity, and the capacitance Co is small compared to the capacitances Cv and CH, it becomes readily apparent from equation (6) that the mean value[VOut]mear, is extremely low.
Therefore, the preamplifier 7 is required to have both a high gain and a high S/N ratio, and, consequently, is quite expensive.
Further, in a usual MOS imager, the circuit elements from the light-receiving potion 1 to the source-follower transistor 5 are integrated onto a single IC chip, and the preamplifier 7 is an external device connected to the transistor 5. Outside noise, such as clock noise, is likely to be introduced at the input of the preamplifier 7. Aiso, because the average value signal [Vout]mean is so small, it is easily affected by outside noise, and the S/N ratio suffers greatly.
One possible approach to improving the signal strength of the output signal [Vout]mean has been to
make the value k small (k=1), i.e., correspondingly to increase the value R, of the load resistor 4. However, if the resistor 4 is too large, the complete signal charge Qs for each picture element unit Swill not be entirely transmitted during a single horizontal scanning pulse period 7,and there is noticeable deterioration in both horizontal and vertical resolution.
Afirst embodiment of this invention is shown in
Fig. 3, wherein elements common to the circuit of
Fig. 1 are identified with the same reference characters, and a detailed description thereof is omitted.
Here, instead of the load resistor 4, the source follower 5, and the preamplifier 7, the horizontal signal transmitting line LH ends in a gain-controlled current amplifying circuit 10.
This gain-controlled amplifying circuit 10 includes first, second, third and fourth junction transistors 11, 12, 13, and 14, each of which in this embodiment is an NPN transistor. The second and third transistors
12, 13 have their bases joined together to the collector of the first transistor 11 and have their collectors coupled to a source of collector voltage Vcc. The first and fourth transistors 11, 14 have their emitters con
nected to another point of voltage Cpct and have their bases connected to the emitters of the second and third transistors 12, 13, respectively. A load
resistor 4' of value RL bridges between the source of
collector voltage Vcc and the collector of the fourth transistor 14.An isolation stage formed of an emitter
follower transistor 15 and an emitter resistor 16 cou ples the collector of the fourth transistor 14to an
output terminal 18.
A current source 21 connected between the source of collector voltage Vcc and the collector of the first transistor 11 furnishes a constant current Iothereto.
A pair of controllable current sources 22 and 23 coupled between ground and the emitter of the second and third transistors, respectively, provide controllable constant emitter currents Ic to the lattertransis- tors. Preferably, the constant emitter currents 1c have equal values, and both sources 22 and 23 are ganged together so that, when adjusted, the respective emittercurrents Ic remain equal.
Here, the input signal current Is is applied to the base of the first transistor 11 and an amplified output signal current input appears at the collector of the fourth transistor 14.
The operation ofthe circuit 10 as a gain-controlled current amplifier can be explained as follows:
The base-emitter junctions of the transistors 11 and 12 are connected in series and those of the transistors 13 and 14 are likewise connected in series, with the bases of the transistors 12 and 13 joined and the emitters of the transistors 11 and 14 joined.Consequently, the base-emitter forward voltages VBe1,
BE2, VBE3 and VBE4 of the first through fourth transistors 11,12,13,14, respectively will have the relationship
VBE1+VBE2=VBE3+VBE4 ................... (7)
In general, the base-emitter voltage VBE of a junction transistor is logarithmically related to the emitter current 1E flowing these through and emitter area A thereof:
VBE # 1n(IE/A) .......................... (8) Using the above relationships (7) and (8), if the
transistors 11 to 14, respectively, have emitter cur
rents I1 to 14 and emitter areas A, to A4, the following
relationship results::
In the embodiment of Fig. 3, the emitter current I1 is substantially the same as the constant collector current 1a provided from the current source 21. Also, the emitter current 1s is equal to the difference between the constant current Ic and the input signal current i5 (i3 = i-i5) while the emitter current i3 is equal to the constant current IC. Since the emitter current 14 for the fourth transistor 14 is substantially equal to its collector current 1out, the relationship (9) above can be rewritten
The output current Iout is then
The output voltage Vnut at the junction of the collector of the transistor 14 with the load resistor 4 becomes
Vout=Vcc.R1Iout+VBE ...... ........ . (12)
This output voltage Vout has an AC signal component Vnut
obtained by substituting the above relationship (11) into the relationship (12), and considering only terms including the input signal current is. Furthermore, by using an integrator or low pass filter, an average signal voltage [VOUdmeans can be obtained having a value
In equation (14), re2 is the resistance value at the emitter of the transistor 12, and can be determined by the relationship
where Qs is the signal charge stored on any given picture element unit S011 to SEmn, k is Boitzmann's constant, and T is the absolute Kelvin temperature of the base emitter junction of the transistor 12.
If a scanning period for the picture element units SO11 to SEmn is selected to satisfy the relationship # > > re2(CV+CH) ....................... (15) equation (14) above becomes
As is apparent from the relationship (15) above, the rate of transfer of the signal charge Qs from the vertical and horizontal signal transmitting lines Lvi to Lv. and LH is essentially determined by the value of the emitter resistance re2 of the transistor 12. The rate of charge transfer is independent of the resis tancevalue RLOf the load resistor 4'. Consequently, even when the value R, of the resistor 4' is large and the gain of the circuit 10 is high, the deleterious effects of the prior art, such as loss of resolution, do not occur.Also, because the signal current is can be amplified directly to obtain a large amplitude voltage signal v5, the S/N ratio for the entire image pickup apparatus is greatly improved. Furthermore, in accordance with the relationship (16) above, if the transistors 11 to 14 have their emitter areas A1 to A4 selected to satisfy the relation A2.A4#A1.A2 and the constant currents 1o and Ic are selected Ia > Ic, the average output voltage [Voud mean can be amplified and the gain of the circuit 10 changed simply by controllably changing the value of the constant current Ic.
A second embodiment of this invention is illustrated in Fig. 4. In this embodiment, circuit elements that are also shown in Fig. 3 are identified with the same characters, and a detailed description thereof is omitted. Here, an additional current source 24 is connected between the source of collector voltage
Vcc and the collector of the transistor 14. A load resistor 27 having a value R, is connected between the collector of the transistor 14 and a point of reference potential Voc2. The additional current source 24 provides a constant current 14C to the transistor 14 so that an output signal current iout having only AC signal components flows through the load resistor 27.
In other words, the emitter current lc, which is substantially equal to the collector current thereof, is equal to the output current lout in the relation (11) above, and can be expressed as follows:
However, if the constant current source 24 supplies to the collector of the transistor 14 a constant DC current corresponding to the DC component of the current iout of the relationship (17) above, the current flowing through the load resistor 27 becomes
As is apparent, this output current iout has only AC signal components.Consequently, the output voltage Vout in equation (13) above, which i5 the AC component of the output signal Vout can be obtained directly at the collector of the transistor 14, and its average value can be obtained according to equation (16) above.
In this case, the constant current supplied from the current source 24, will have the value
Athird embodiment of this invention is illustrated in Fig. 5, in which elements shared with the embodiment of Fig. 4 are identified with the same reference characters. In this embodiment, in place of a load resistor, the collector of the transistor 14 is connected to one place of load capacitor 36 having a capacitance of Cp, another plate of which is connected to ground. A PNP charging transistor 35 has its emitter connected to the one plate of the capacitor 36, its collector connected to ground, and its base connected to receive precharge pulses (pp.
The one plate of the capacitor 36 is also coupled through an output stage formed of a Darlington arrangement of NPN transistors 37 and 38 to the output terminal 18.
Here, at the onset of each of the horizontal scanning signals #H1, (pH2, (pHa (Fig. 6A),the signal charge
Qs stored in each picture element unit S011 to SEmn is transferred through the transmitting line LV and LH and appears a differentiated signal current is (Fig.
6B). In this embodiment, both the input signal is and the output signal current isout (Fig.6C) are both positive, as the latter represents a charging of the load capacitor 36. Thus, it is required to preset the load capacitor 36 to a constant initial low value, such as ground potential. For this reason, the clock pulse signal (pp (Fig. 6D) is supplied to the base electrode of the transistor 35 to drive the same on for a brief period immediately before the output signal current input flows. Consequently, the capacitor 36 is discharged before being partially charged up by the output signal current Isout. Thus, the load capacitor 304 has an output waveform vsnut as shown in Fig.
6E. Here, if the discharging ON time of the transistor 35, as governed by the pre-charge signal (pp is TA, the final output voltage vsnut appearing at the one plate of the capacitor 36 becomes:
If the ON time TA is set to a value sufficiently greater than the time constant re2 (CD+CH) then the integral term in the equation (19) above is nearly equal to Qs, and the output voltage vsout results as follows::
As is apparent from the above equation (20), if the capacitance Cp of the load capacitor 36 is small, the
emitter area ratio A;A4
Aik is large, and the constant current 1p is also suffi- ciently large, compared with the gain-control constant current Ic, the circuit 10 can attain a high gain, and this gain can be easily controlled by selecting appropriate values of the constant current c Furthermore, because the output waveform volt, as shown in Fig. 6E, is generally stable at a point just prior to the leading edge of the pre-charge pulse signal (pp, a sample-hold operation can be carried out at the times indicated vertical arrows in Fig. 6E,to produce a sample and held voltage SH as shown in
Fig. 6F.
Fig. 7 illustrates a fourth embodiment of this invention, wherein each of the current sources 21, 22,23, and 24 are constructed of respective junction transistors 31, 32, 33, and 34. In particular, PNPtrans- istors 31 and 34 are employed as the constant current sources for supplying the DC current 1a to the collectors of the transistors 11 and 14, while NPN transistors 32 and 33 supply an adjustable constant current 1c to the emitters of the transistors 12 and 13, respectively.
The transistors 32 and 33 have their collectors coupled to the emitters of the respective transistors
12 and 13, and have their emitters coupled together to ground. These transistors 32 and 33 have their bases connected to the base of a drive transistor 40, which has its collector joined to its base and to a controllable current source 41 supplying a control current IC1 thereto. The emitter of this drive transistor 40 is connected to ground.
The transistors 31 and 34 have their collectors connected respectively to the collectors of the transistors 11 and 14, and havetheiremitters connected together to the point of collector voltage Vcc. These transistors 31 and 34 have their bases joined together to the base of a drive transistor 42 whose emitter is connected to the voltage Vcc and whose collector is joined to its base, and is also coupled through a coUlector resistor 43 of value Ro to ground.
The transistors 42, 31, and 34 from a first current mirror circuit for supplying current to the transistors 11 and 14, while the transistors 32, 33, and 40 from a second current mirror circuit for supplying current to the transistors 12 and 13.
In the above-described embodiment, if the transistors 31, 32, 33, 34, 42, and 40 have respective emitter areas of ki, A32, A33, A34, A42, and A40, the output signal current input can be obtained substantially free of any DC current component, if following relationship are established:
A32=A33=A40 ....... (21)
In addition, if the transistor 42 has a base-emitter voltage of VBE, and the resistor 43 has a resistance value of Row the DC constant current 1p flowing to the collector of the transistor 11, will have a value established as follows::
Fig. 8 illustrates a fifth embodiment of this invention which is generally similar to the third embodiment, but wherein the bipolar transistor 35 is replaced with an MOS field effect transistor 35F. The transistor 35F, operated in a non-saturation mode, has its drain electrode connected to a source of drain potential Vdd, its source electrode coupled to the one plate of the load capacitor 36, and its gate electrode coupled to receive the pre-charge pulses #p.
Fig. 9 shows a sixth embodiment of this invention, in which a gain-controlled amplifier 100 is supplied with the input signal current i5 frorn the MOS imager 1. In this gain-controlled amplifier 100, three current mirror circuits are employed to form a doublebalance arrangement wherein any DC component of the output signal current Isout is eliminated.
In this embodiment, first and second diodearranged NPNtransistors 101 and 102havetheir bases joined to the bases of respective NPN transistors 103 and 104. The transistor 104 has its collector joined to the collector of a diode-arranged PNP trans- istor 106, while the transistor 104 has its collector coupled to the collector of another transistor 107, whose base is joined to the base and collector of the transistor 106. These NPN transistors have their emitters joined to a source of potential VCC, while the emitters of the transistors 101 to 104 are coupled to another reference voltage Voci by means of sourcedrain paths of respective MOS transistors 111, 112, 113, and 114. The MOS transistor 111 and 112 have their gate electrodes connected to a common DC bias voltage source 115 supplying a DC voltage VD thereto to maintain these transistors 111 and 112 in a non-saturation state. The MOStransistors 113 and 114 have their gate electrodes connected in common to a series combination of a DC bias voltage source 116, which supplies the DC voltage VD, and a gaincontrol voltage source 117, which supplies a control led variable voltage v.
It should be appreciated that the transistors 101 and 103 form a first current mirror circuit 121,the transistors 102 and 104 form a second current mirror circuit 122, and the transistors 106 and 107 form a third current mirror circuit 123. In these current mirror circuits, the transistors 101, 102, and 106 act as inputtransistors, while the other transistors 103, 104, and 107 act as output transistors.
Here, constant current sources 131 and 132 each supply a constant current Io to the collectors of the input transistors 101 and 102, respectively.
In this embodiment, the collector of the input transistor 101 of the first current mirror circuit 121 is coupled to the horizontal signal transmitting line LH to receive the input signal current i5. Accordingly, the output transistor 103 ofthefirst current mirror circuit 121 is the point at which the output signal current input appears.
Similarly to the foregoing third, fourth, and fifth embodiments, a pre-charging transistor 135 and a load capacitor 136 are coupled to the collector of the transistor 103, and are followed by an isolation stage formed of an emitter-follower NPN transistor 137 connected in series with a current source 138. The emitter of the transistor 137 then supplies an isolated output signal to an outputterminal 139.
The operation of this circuit can be explained with reference to Figs. 10A to 1 OF. To simplify the explanation, it will be assumed that the transistors 101 to 104, 106, and 107 have identical characteristics, and thatthe MOS transistors 111 to 114also haveidenti- cal characteristics. However, this condition is not necessary to practice this invention.
Each of the transistors 101 to 104 has an emitter current I1 to 14, respectively, flowing therethrough.
initially, if each of the MOStransistors 111 to 114 has a respective source-to-drain resistance of Rii, Ri2, R12, and R14, the collactor current 13 of the transistor 103 can be established as
The source-to-drain resistances Rii to R,4 can be established according to the following relationships 1
R11=R12= (VD+Vth) .... (24)
R13=R14= (VD+VC+Vth)
2ss ..... (25) in which ssi is the gain characteristic of the MOS trans
istors, and can be expressed as follows
wherein ,UN is the channel carrier mobility, Ent and tox are the dielectric constant and layer thickness of the oxide insulation layer on the gate region of the MOS transistor, respectively, and Wand L are the gate width and gate length thereof, respectively. In the above relationship 24 and 25, Vth is the th reshold voltage for each of the MOS transistors.
The collector current 1, flowing through the transistor 107 can be expressed as follows:
From a consideration of both the foregoing equations (27) and (23), the output signal current input flowing into the load capacitor 136, is just the difference between the currents 13 and i7, and can be expressed as follows:
isout = I3
Thus, the output signal current input will be provided substantially free of any DC components, and the gain of the circuit 100 will be substantially proportional to the level of the gain control voltage vc.
Similarly to the third embodiment (Fig. 5), in response to the leading edge of the horizontal scanning pulses (phi, bh2 #h3 (Fig. 10A), a differential input signal current is (Fig. OB) flows into the collector of the input transistor 101 of the first current mirror circuit, and an amplified output signal current isout (Fig. 1 0C) flows from the collector of the output transistor 103.If, as shown in Fig.10D, the precharging pulse (pp has a period TA representing the separation between successive ON times of the transistor 135, an output signal voltage vout will appear on the one plate of the load capacitor 136, and the same can be sampled at the times indicated by vertical arrows to provide a sampled and held signal SH as shown in Fig. 10F.
Similarly to the third embodiment discussed hereinabove, it should be apparent that the output voltage Vsout appearing at the output terminal 139 will have a value which can be calculated as follows:
In the above embodiment, it has been assumed that the MOS transistors 111 to 114 have identical characteristics. However, assuming that the ratio of gate widths to gate lengths of the MOS transistors 111 and 112 are equal to a value (W/L)N, while the ratio of the gate widths to the gate lengths of the
MOS transistors 113 and 114 are equal to a value (W/L)OUT, the following equation (29) becomes
From this equation (30), it should be apparent that by setting the ratio (W/L)aUTtO the value (W/L)lNtO be large, a large-amplitude signal output can be readily obtained.
Fig. 11 illustrates a seventh embodiment of this invention, in which the gain-control circuit 100 is generally similar to that of the embodiment of Fig. 9, exceptthatMOStransistors 141, 142, 143, 144, 145, 146, 147, and 157 are used in place of the junction transistors 101, 102, 103, 104, 135, 106, 107, and 137 of the sixth embodiment. In this embodiment, the
MOS transistors 141 to 145 are N-channel type transistors, while the MOS transistors 146 and 147 are
P-channel type transistors.
In this seventh embodiment, the output voltage v5out appearing at the one plate of the load capacitor 136 can be expressed as follows, where the MOS transistors 141 and 143 havetransconductances cf g.1 and g.3, respectively, and the MOS tr?. iz.stors 111 and 113 have source-to-drain resistances of Rn and Rut3, respectively:
The operation and advantages of this embodiment are similar to those of the aforementioned sixth embodiment.However, because the gain-control amplifier 100 is constituted entirely of MOS transistors, the entire image pickup apparatus can be inte
grated on a single semiconductor chip, and the same
MOS construction techniques used to prepare the
MOS imager 1 can also be used to prepare the MOS
gain-controlled current amplifier 100.
Fig. 12 illustrates an eighth embodiment of this
invention, which is generally similar to the Fig. 7
embodiment, but wherein depletion-type field effect transistors 151 and 152 respectively form constant current sources providing the constant current lotto the input transistors of the first and second current
mirror circuits, 121 and 122, respectively. Also, in this embodiment, the current mirror circuits 121 and
122 are feed-forward current mirror circuits. That is,
the first current mirror circuit 121, has an input MOS
transistor 211 and a pair of output MOS transistors
212 and 213 connected in series. The second current
mirror circuit 122 also has an input MOS transistor
221 and a pair of output MOS transistors 222 and 223
connected in series.The transistors 211 and 212
have gate electrodes coupled to each other and also
to the drain electrode of the transistor 212, while the
gate electrode of the transistor 213 is connected to
the drain electrode of the transistor 211. Similarly, in
the second current mirror circuit, the gate electrodes
of the MOS transistors 221 and 222 are coupled
together to the drain electrode of the MOS transistor
222 and the source electrode of the transistor 223,
while the gate electrode of the transistor 223 is cou
pled to the drain electrode of the MOS transistor 221.
This embodiment has the advantage of a higher
speed of operation than the foregoing embodi
ments, because of its feed-forward construction in
the first and second current mirror circuits 121 and 122.
Fig. 13, which is on the same sheet as Fig. 4, shows a ninth embodiment of this invention. In this embodiment, the elements shown are generally the same as in the seventh embodiment, except that a load resistor 167 extends between a source of DC voltage
VDC2 and the drain electrode of the output MOS transistor 143 of the first current mirror circuit 121. Here, the load capacitor 136 and the pre-charging transistor 145 are omitted. It should be appreciated that in this embodiment, only the Ac output signal isout flows through the resistor 167, and, therefore, the source of the Dc voltage VDC2 need not be closely controlled.
While several embodiments of this invention have been described in detail hereinabove, it is urged that the embodiments are representative only, and that many modifications and variations thereof will be apparent to those skilled in the art without departing from the scope and spirit of this invention, as defined in the appended claims.
Claims (24)
1. Image pickup apparatus comprising a plurality of picture element units each formed of a photosensitive member generating a quantum of electrical charge depending on the amount of light falling thereon, and an electrically controlled gating circuit for transmitting the generated amount of charge in response to scanning pulses applied thereto, said picture element units being disposed in a twodimensional array of horizontal rows and vertical columns; scanning circuit means for sequentially providing said scanning pulses to the gating circuits of the respective picture element units; and output circuit means coupled to receive the electrical charges in sequence from said picture element unit to produce a video signal, wherein said output circuit means includes a gain-controlled current amplifier having a signal input receiving said electrical charges as an input signal current, an output providing an amplified output signal current whose strength is related to that of the input signal current by a current gain of the gain-controlled current amplifier, and a controllable element for selectively adjusting said gain in accordance with a control signal applied thereto.
2. Image pickup apparatus according to claim 1, wherein said gain-controlled amplifier includes first, second, third, and fourth transistors, each having a first current-carrying electrode, a second currentcarrying electrode, and a control electrode, with said second and third transistors having their first current-carrying electrodes coupled together to one point of voltage, having their control electrodes coupled together to the first current-carrying electrode of said first transistor, and having their second current-carrying electrodes coupled to the control electrodes of said first and fourth transistors, respectively, the first and fourth transistors having their second current-carrying electrodes coupled together to another point of voltage; a current source coupled
between said one point of voltage and the first
current-carrying electrode of said first transistor to
provide a constant current thereto; load means cou
pled between said one point of voltage and the first
current-carrying electrode of said fourth transistor;
and adjustable current source means providing
adjustable constant currents to said second current
carrying electrodes of said second and third transis
tors, respectively; with said input signal current
being supptiedto said control electrode of said first trarlsístor and said output signal current appearing
at said first current-carrying electrode of said fourth
transistor.
3. Image pickup apparatus according to claim 2, wherein said picture element units and said first
through fourth transistors are all formed as an inte
grated circuit on one semiconductor chip.
4. Image pickup apparatus according to claim 2,
wherein said load means includes a load resistor.
5. Image pickup apparatus according to claim 2,
wherein said load means includes a further current
source coupled to the first current-carrying electrode
of said fourth transistor providing a constant current
thereto, and another load element coupled to such
first current-carrying electrode.
6. Image pickup apparatus according to claim 5,
wherein said other load element includes a load
capacitor having one plate coupled to the first
current-carrying electrode of said fourth transistor
and another plate coupled to a reference point, and a
pre-charging transistor having a first current
carrying electrode connected to a voltage reference
point, a second current-carrying electrode coupled
to said one plate of said load capacitor, and a control
electrode connected to receive a switching pulse.
7. Image pickup apparatus according to claim 6, further comprising an output isolation stage having
an input coupled to said one plate of the load
capacitor and an output.
8. Image pickup apparatus according to claim 7, wherein said output isolation stage includes a dar
iington pair of transistors having a control electrode
coupled to said one plate of the load capacitor and
an output electrode connected to said output of the
isolation stage.
9. Image pickup apparatus according to claim 6,
wherein said pre-charging transistor includes an
MOS transistor having source and drain electrodes
as its current-carrying electrodes and a gate elec
trode as its control electrode.
10. Image pickup apparatus according to claim 1,
wherein said gain-controlled amplifier includes first,
second, third, and fourth junction transistors each
having a collector, an emitter, and a base, with the
second and third transistors having their collectors
coupled together to one point of voltage, having
their bases coupled together to the collector of said
first transistor, and having their emitters coupled to
the bases of the first and fourth transistors, respec
tively, the first and fourth transistors having their
emitters coupled together to another point of vol
tage; one current source coupled between said one
point of voltage and the collector of the first transis torto provide a constant current thereto; load means
coupled to the collector of the fourth transistor; and
adjustable current source means providing adjust
able constant currents to the emitters of the second
and third transistors, respectively; with said input
signal current being applied to the base of the first
transistor and the output signal current appearing at the collector of the fourth transistor.
11. Image pickup apparatus according to claim 10, wherein said load means includes a further current source coupled to the collector of said fourth transistor providing a constant current thereto, and another load element coupled to such collector.
12. Image pickup apparatus according to claim 11, wherein said first, second, third, and fourth transistors are formed with respective emitter areas A" A2, A3, and A4, said one current source provides the constant current 1a to the collector of the first transistor, and the further current source provides the constant current to the collector of the fourth transistor at a level 14C, where
13.Image pickup apparatus according to claim 11, wherein said one and said further current sources are formed of respective one and further transistors each having an emitter connected to said one point of voltage and a collector joined to the collector of a respective one of said first and fourth transistors, and having their bases joined together; and further comprising a diode-connected transistor having an emitter joined to said one point of voltage, a base connected to a collectorthereof and to the bases of the one and further transistors, and a resistor connected between the collector of said diodeconnected transistor and another point of voltage.
14. Image pickup apparatus according to claim 10, wherein said adjustable current source means includes a current mirror circuit formed of fifth, sixth, and seventh transistors, each having a collector, an emitter, and a base, with their emitters joined together to a reference point, their bases joined together, the collectors of the fifth and sixth transistors being joined to the emitters of the second and third transistors, respectively, and the collector of the seventh transistor being joined to the base thereof; and a controllable current source coupled to the joined-together bases of the fifth, sixth, and seventh transistors.
15. Image pickup apparatus according to claim 1, wherein said plurality of picture element units provides said input signal current as a time-shared sampled signal.
16. Image pickup apparatus according to claim 1, wherein said gain-controlled current amplifier
includes first, second, and third current mirror circuits each formed of an input transistor device and
an output transistor device, each transistor device
having first and second current-carrying electrodes
and a control electrode, with the control electrodes
of both said transistor devices of each said current
mirror circuit being joined together, the current mir
ror circuits being arranged so that current flowing
into the first current-carrying electrode of the output
transistor device thereof changes in accordance with
a current flowing into said first current-carrying elec
trode of the input transistor device thereof; current
source means providing substantially equal constant
currents to the first current-carrying electrodes of the
input transistor devices of said first and second cur
rent mirror circuits, respectively; the first current
carrying electrodes of the output and input transistor
devices of the third current mirror circuit being
joined to the first current-carrying electrodes of the outputtransistor devices of said first and second
current mirror circuits, respectively, the second current-carrying electrodes of the transistor devices
of the third current mirror circuit being coupled to a
point of reference potential; first and second resistive means coupled to establish substantially equal fixed resistances between a reference point and the second current-carrying electrodes of the input transistor devices of said first and second current mirror circuits, respectively; and third and fourth resistive means coupled to establish substantially equal variable resistances between the reference point and the second current-carrying electrode of the output transistor devices of said first and second current mirror circuits, respectively; with "r:Pd input signal current being applied at the first current carrying electrode of the input transistor device of said first current mirror circuit and with said output signal current appearing at the first current-carrying electrode of the output transistor device of said first current mirror circuit
17.Image pickup apparatus according to claim 16, wherein said first, second, third, and fourth resistive means each include a respective first, second, third, and fourth MOS transistor having source and drain electrodes coupled in series between said reference point and the second cu-rnnt-carrying electrodes of the input transistor device of said first current mirror circuit, the inputtransistor device of said second @ea current mirror si circuit, the outputtransis- tor device of said first current mirror circuit, and the output transistor device of said second current mirror circuit, respectively, and each said MOS transistor also having a gate electrode; and further comprising a fixed bias source coupled to the gate electrodes of said first and second MOS transistors and a selectively variable bias source coupled to the gate electrodes of said third and fourth MOS transistors.
18. Image pickup apparatus according to claim 16, wherein the input and output transistor devices for said first, second, and third current mirror circuits each include a junction transistor having a collector, an emitter, and a base as its first current-carrying electrode, second current-carrying electrode, and control electrode, respectively, with the collector and base of each input transistor being coupled together.
19. Image pickup apparatus according to claim 18, wherein the junction transistors of said first and second current mirror circuits are all of one type and the junction transistors of said third current mirror circuit are both of another, complementary type.
20. Image pickup apparatus according to claim 16, wherein the input and output transistor devices for said first, second, and third current mirror circuits each include an MOS transistor having an drain electrode, a source electrode, and a gate electrode serving as its first current-carrying electrode, its second current-carrying electrode, and its control electrode, respectively.
21. Image pickup apparatus according to claim
20, wherein said MOS transistors for said first and second current mirror circuits are of one of an
N-channel and a P-channel type; while the MOS transistors for said third current-mirror circuit are of the other of said N-channel and said P-channel type.
22. Image pickup apparatus according to claim 20, wherein the output transistor device for each said current mirror circuit includes a first and an additional MOS transistor having source, drain, and gate electrodes, with the source and drain electrodes of the additional MOS transistor being coupled in series with the drain electrode of the first MOS transistor, and with the gate electrode of the additional
MOS transistor being connected to the drain electrode of the input MOS transistor, such that each said current mirror circuit operates as a feed-forward circuit.
23. Image pickup apparatus according to claim 16, further comprising a load capacitor having one plate coupled to the first current-carrying electrode of the output transistor device of said first current mirror circuit, and another plate coupled to a reference point; and a pre-charging transistor having a first current-carrying electrode coupled to a source of charging voltage, a second current-carrying electrode coupled to said one plate of the load capacitor, and a control electrode coupled to receive a switching pulse.
24. Image pick-up apparatus constructed and arranged to operate substantially as hereinbefore described ditch reference to and as illustrated in Figures 3to 13 of the accompanying drawings.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56074810A JPS57190409A (en) | 1981-05-20 | 1981-05-20 | Gain controlling and amplifying circuit |
JP56074809A JPS57190467A (en) | 1981-05-20 | 1981-05-20 | Signal output circuit for image pickup device |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2108351A true GB2108351A (en) | 1983-05-11 |
GB2108351B GB2108351B (en) | 1985-01-30 |
Family
ID=26415988
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08214621A Expired GB2108351B (en) | 1981-05-20 | 1982-05-19 | Image pick-up apparatus |
Country Status (6)
Country | Link |
---|---|
AT (1) | AT385617B (en) |
CA (1) | CA1185006A (en) |
DE (1) | DE3218971A1 (en) |
FR (1) | FR2506546B1 (en) |
GB (1) | GB2108351B (en) |
NL (1) | NL8202106A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3366801D1 (en) * | 1982-04-17 | 1986-11-13 | Sony Corp | Solid-state image pickup element |
FR2713037B1 (en) * | 1993-11-23 | 1995-12-29 | Thomson Csf | Injection circuit, in thermal imaging. |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5610667B2 (en) * | 1973-06-20 | 1981-03-10 | ||
JPS55105480A (en) * | 1979-02-07 | 1980-08-13 | Hitachi Ltd | Solid state pickup device |
US4225883A (en) * | 1979-06-11 | 1980-09-30 | The United States Of America As Represented By The Secretary Of The Army | Automatic responsivity compensator in an IR imaging system |
-
1982
- 1982-05-19 CA CA000403337A patent/CA1185006A/en not_active Expired
- 1982-05-19 DE DE3218971A patent/DE3218971A1/en not_active Withdrawn
- 1982-05-19 GB GB08214621A patent/GB2108351B/en not_active Expired
- 1982-05-21 FR FR8208913A patent/FR2506546B1/en not_active Expired
- 1982-05-21 NL NL8202106A patent/NL8202106A/en not_active Application Discontinuation
- 1982-05-21 AT AT0202082A patent/AT385617B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
NL8202106A (en) | 1982-12-16 |
AT385617B (en) | 1988-04-25 |
ATA202082A (en) | 1987-09-15 |
CA1185006A (en) | 1985-04-02 |
DE3218971A1 (en) | 1983-01-20 |
FR2506546A1 (en) | 1982-11-26 |
GB2108351B (en) | 1985-01-30 |
FR2506546B1 (en) | 1988-11-04 |
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