GB2104350A - A network circuit for a word processing system - Google Patents

Abstract

A network communications system circuit is provided for use in a word processing system which includes a network channel (3). The circuit has a system communications bus (34) for transferring data and address information and a processor (6) connected to the bus (34) for directing the transfer of data over the bus (34). Connected to the network channel (3) is protocol control means (10) for controlling protocol of information. State controlling means (12) is connected to the protocol control means (10) for controlling data packet formation and conversion. Multiplexing means (36, 38) is connected to the bus (34), to the protocol control means (10) and to the state controlling means (12) for selectively allowing the processor (6) and the state controlling means (12) to access the protocol control means (10). <IMAGE>

Description

SPECIFICATION Digitially locked auto-synchronizing manchester decoder The present invention relates to decoding circuitry, and more particularly to decoding circuitry for use in a word processing system utilizing a local network.

In computing systems having a number of computers, and in particular in word processing systems having a number of word or data processing stations, it is desirable to interconnect the computers or work stations by means of a local network. The local network often provides nothing more than a means for high speed communications (i.e., transferring data) among the stations over a communications channel, for example a coaxial cable provided for that purpose.

The use of high speed communications has heretofore been reliably facilitated in such systems by the use of encoding schemes, such as the Manchester code. The Manchester code imbeds a clock signal in the data to be transmitted.

A Manchester decoder from a single input signal must retrieve and separate the data and its associated clock signals. The data was encoded by causing a transition in the output signal of the encoder at least once every clock period. The nature of this transition is from an inactive to an active level for a logic "1" and a transition from an active level to an inactive level for a logic "0". These transitions take place at the midpoint of a Manchester data bit cell. The transitions can also be present at the bit cell partitions, for which they are not relevant for purposes of this invention, to retrieve the data or the clock signal. The transition is detected only at the midpoint of the bit cell. Data is sampled and a clock pulse is generated.

Transitions at the bit cell partition are dependent upon the pri I bit cell's ending level and the required starting level for the next bit cell. At all other times the data is not sampled nor is the clock pulse generated. This prevents the decoder from acting on an incorrect transition at the bit cell partition.

If the decoder becomes unsynchronized and begins to sample data on bit cell partitions, the decoder should self-synchronize at the next logical level change of the unencoded data, i.e., from a logic "1" data bit to a logic "0" or vice versa. A change in unencoded data does not have a transition at the bit cell partition. Accordingly, the decoder samples data, thus becoming synchronized, on the correct transition at the midpoint of the next bit cell. In Manchester encoding the conditions previously mentioned cause a stable level for a time period one bit cell long. The decoder of the present invention is designed to ignore transitions for 60%-80% of a bit . cell period and to trigger the clock pulse and sample data upon the next transition there after.

Previous Manchester code decoding tech niques used asynchronous timing to retrieve the clock signal from the Manchester encoded signal via asynchronous analog means such as phase locked loops having a clock generator synchronized with the Manchester data. These techniques did not generate the clock signal from the incoming signal, but rather used a free running clock generator. Disadvantages of such prior systems include a relatively large number of components, concomitant high costs of materials and assembly, and the necessity to calibrate.

U.S. patent application, serial number 155,281, filed July 2, 1980, entitled, "Man chester Code Decoding Apparatus" for Harris A. Quesnell, Jr. and assigned to the U.S.

Department of the Navy, discloses an appara tus for decoding a Manchester encoded wave form. A gating circuit responds to the mid-cell transitions in the encoded waveform to pro duce an enabling signal which causes a clock circuit to generate high frequency clock pulses. A programmable counter accumulates the generated clock pulses. If the counter exceeds a clock count threshold set by a multi position switch before the beginning of the following enabling signal, it causes a storage element to sample the encoded wave form and store the sample to provide an output signal representing decoded data.

The above-described system is actually an integrate-dump technique, not most efficient in terms of number of components or circuit complexity. Moreover, resynchronization, i.e., initialization and error recovery, is also ineffici ent in such integrate-dump systems. When a decoder of the above-identified type becomes unsynchronized, a phase shift or logical data transition occurs which appears to be the same sort of transition that the decoder is normally expected to detect. Accordingly, for the worst case the integrate-dump system requires two phase shifts before resynchroni zation with the incoming data can take place.

In Quesnell, Jr., a clock generator is used to drive a counter. The counter is cleared and loaded with a variable count, depending upon the data rate being used. A pulse-width gate generates enabling signals to the clock gener ator depending upon the input signal and a sample flip flop device which indicates the present state of the output data. Thus, the command pulse is enabled by the state of the prior output data, as controlled by the sample flip flop.

The present invention, as distinguished from the Quesnell, Jr. system, uses a masking circuit to mask or block the input signal recognition for a particular time period. A counter is used in the instant invention to control the time delay and to control the decoding operation. Within one bit cell time period, or phase shift, the present invention resynchronizes with the incoming data, inde pendently of the prior output state of the decoder.

In contrast to Quesnell, Jr., the present invention requires less components and less complex circuitry. Moreover, resynchronization is facilitated in a shorter time period. The present invention allows for resynchronization at the next phase shift, irrespective of the prior state of the output data. Only two open ing flag bytes at the beginning of the data packet are required for use with this present system, as compared to three flag bytes for use with the Quesnell, Jr. system In the present invention, a clock generator is not required, since the counter is driven from the system clock and the clock signal is not gated. Because data rates are intended to be fixed in the present invention, the value loaded into the counter is also fixed, and there is no neeed to actuate the clear input during the decoding operation.

Finally, in the present invention a configuration of cascaded flip flop devices is used in the same manner as a shift register. This configuration, coupled with the sampling of outputs via an exclusive OR function, detects level changes and produces a transition detection pulse for any transition, not merely a selected transition, as contemplated by the Quesnell, Jr. system.

The use of masking technique in the present invention, as opposed to the integratedump technique used in Quesnell, Jr., thus reduces the number of components and circuit complexity required for decoding Manchester encoded data.

By using various distinctive characteristics of Manchester encoded data, a decoder built in accordance with the present invention can also retrieve non-return to zero (NRZ) formatted data and associated clock signal by simple all digital means without exacting synchronism to the incoming Manchester signal.

Synchronism with the system occurs, however, and the incoming signal can be sampled. Thus the decoder in such self-synchronizing systems need not be exactly synchronous with the Manchester data, but need be only synchronous enough to retrieve reliable NRZ formatted data and to generate a clock signal used for synchronizing the decoder with the system.

A decoding circuit of this sort interfaces the network system to a respective work station system when the station is monitoring communications activities.

In accordance with the present invention, a network communications systems circuit is provided for use in a word processing system which includes a network channel. The circuit has a system communications bus for transferring data and address information and a processor connected to the bus for directing the transfer of data over the bus. Connected to the network channel is protocol control means for controlling protocol of information.

State controlling means is connected to the protocol control means for controlling data packet formation and conversion. Multiplexing means is connected to the bus, to the protocol control means and to the state controlling means for selectively allowing the processor and the state controlling means to access the protocol control means.

A complete understanding of an embodiment of the present invention may be obtained by reference to the accompanying drawings, when taken in conjunction with the detailed description thereof and in which: Figure 1 is a block diagram showing the components of an embodiment of the present invention; Figure 2 is an interconnection diagram of Figs. 2a through 29, which when taken together are a circuit diagram of the decoding circuitry of the present invention; Figure 3 is a timing diagram of the decoding operation of the present invention; Figure 4 is a timing diagram of the encoding operation of the present invention; and Figure 5 is a flow chart for use with the present invention.

The circuit of the present invention is used to handle parallel information and convert it, with the correct protocol, to serial data. The serial data is then transmitted to a tap transceiver and thence onto a network channel.

Referring to the drawings in which identical components are numbered in separate figures identically, Fig. 1 is a block diagram of local network circuitry for use in a word processing system. A microprocessor 6 such as Model No. 8085 manufactured by the Intel Corp., is connected to a data communications bus 34 (hereinafter called a system bus), consisting of an address bus and a data bus, as more particularly shown and described hereinbelow.

To the system bus 34 is also connected a direct memory access (DMA) controller 7, such as Model No. 8237 manufactured by Intel Corp., and dynamic random access memory (RAM) 8, such as Model No. 8202 or S4354 manufactured by Intel Corp. A control bus 5 is also connected to the microprocessor 6, the DMA controller 7 and the memory 8.

A A network channel, such as a coaxial cable as is well known in the art, is shown at reference numeral 3. A tap transceiver is provided at reference numeral 4 and is adapted to be connected to the network channel 3. An encoder/decoder 9 is provided to translate data into or convert data from socalled Manchester format, as is described in more detail hereinbelow.

Connected to the encoder/decoder 9 is a multi-protocol communications controller (her einafter called an MPCC) 10, such as Model No. 2652-1 manufactured by the Signetics Corp. The MPCC 10 is also connected to the system bus 34 via an MPCC local bus 44 and multiplexing circuitry 36 and 38, described in more detail herebelow.

A transmitter state controller 12 is connected both to the MPCC local bus 44 and to an MPCC access controller 26. The MPCC access controller 26, in turn, is connected to the control bus 5, to the microprocessor 6, to the DMA controller 7, and to the multiplexing circuitry 36 and 38.

Referring now also to Fig. 2, a basic component of the circuit is the Model No.

2652-1, MPCC 10 which handles the various protocol, such as station address recognition, to convert the information from the microprocessor 6 and from other processor support devices, and likewise to convert the information to and from a serial data stream of the network channel 3.

The components that support the MPCC 10 are two algorithmic state machine devices, one of them being the transmitter state controller shown generally at reference numeral 12. The transmitter state controller 12 includes a PROM 14 such as one manufactured by the Texas Instruments Vorp. as Model No.

74S472. Latches 16, 18 and 20, supplied by the Texas Instruments Corp. as Model No.

74LS273, synchronize the inputs and outputs of the transmitter state controller 12. Programmable array logic 22 supplied by Monolithic Memories, Inc. as Model No. PAL 10L8.

expands the amount of output control signals of the PROM 14. (PAL is a registered trademark of Monolithic Memories, Inc.) A flip flop 24 is controlled by latch 16 for recognizing a transmit done (TXDONE) signal which is generated by the direct memory access (DMA) controller 7 upon the completion of a data packet transfer to or from the MPCC 10 and memory 8.

Another state machine, referred to as an MPCC access controller shown generally at reference numeral 26, handles control signal synchronization and conversion from the control signals used by the system (the microprocessor 6, the DMA controller 7, the memory 8, and the transmitter state controller 12) and converts data for intelligible use by the MPCC 10. The MPCC access controller 26 consists of a PROM 28 and two latches 30 and 32 used for synchronization.

As previously mentioned, the system bus 34 is connected to the microprocessor 6, the DMA controller 7 and memory 8. The system bus 34 applies data to the MPCC 10 via multiplexing transceiver circuitry, comprising an 8-bit bus transceiver 36, a multiplexer 38 and two OR gates 40 and 42. This circuitry locks out the system bus 34 from a local bus 44 connected to the MPCC 10 for transmitter state controller state controller access of the .MPCC 10 via the local bus 44. The multiplex ing transceiver circuitry 36 and 38 is thus controlled by the MPCC acess controller 26, which in turn is controlled by the transmitter state controller 12 when access by the MPCC 10 is required.

A bus driver 46 is part of the transmitter state controller driver which drives the local bus 44 when the transmitter state controller 1 2 is active. Data is transmitted from the MPCC 10 as a transmit data (TXDATA) signal.

This data is in serial form going to the tap 4.

The information transmitted is in a non-return to zero (NRZ) format which is encoded to Manchester format.

Similarly, Manchester format data is de coded into NRZ format data. A transition detection pulse or signal 48 is sent to carrier detection circuitry shown generally at refer ence numeral 50 which eventually triggers an interrupt of the microprocessor 6. The carrier detection circuitry 50 consists of a one-shot 52 for indicating that data is present and a shift register 54 for comparing the carrier state to determine any change. A decoder 56 controls various registers used for supervising the functional components in the circuit.

In operation, data from the network channel 3 is sent from the tap transceiver 4 to a Model No. 8820 line receiver 58. The receive data (RCVR DATA) signal from the network channel 3 is received by the line receiver 58 and transferred to decoding circuitry including a cascade array of JK flip flops, such as Model No. 74276, shown as reference numerals 62 and 64 respectively. These flip flops 62 and 64 receive the information and synchronize it with the system clock ZP (called "phi") 5 MHz signal.

A A counter such as Model No. 74LS163, shown at reference numeral 66, is also part of the decoding circuitry. It delays recognition of the incoming data signal. The counter 66 establishes a time window or mask, as herein below described, during which it does not sample data from the flip flops 62 and 64.

Data is synchronized by flip flop 62 and after one clock cycle is sent to flip flop 64, thus propagating the received (Q) signal and delay ing it a few clock cycles, so that a compari sion can be made between the current signal level and the signal level of the previous clock cycle interval. If there has been a change of data since the previous clock cycle, a high level signal will be output from one flip flop (for example, flip flop 62) and a low level signal will be output from the other flip flop (for example, flip flop 64). These signals are sent to an exclusive OR gate 68 to produce the transition detection pulse 48 one clock cycle long which can be used by both the carrier detect circuitry 50 and the remainder of the decoder circuitry for transition detec tion.In other words, the cascaded set of flip flops 62, 64 acts as a shift register synchro nous with the system. Their outputs are sensed for a level transition in Manchester data via the exclusive OR function via gate 68.

The transition detection pulse 48 is applied to a NAND gate 70. The other input of the NAND gate 70 supplies a signal generated by the counter 66. The NAND gate 70 controls the initiation of the counter 66 which discontinues sampling of the receive data signal until a given count is reached. When the counter 66 begins to count. it strobes data in through an output latch 72 from the output line of the counter 66. The counter 66 also generates a receive clock (RXC) signal at pin 12, labeled QB which, together with the data signal, was required as part of the NRZ format, and is sent to the MPCC 10. The signal which is output from the latch 72 is data in NRZ format which is sent to the MPCC 10, pin 3, receive serial input line (RXSI).

The data sampling via gate 72, transition recognition, clock pulse timing, and other control timing of the decoder is controlled by the synchronous counter 66. In the generation of a time window, the counter 66 counts three b clock cycles. On reaching the fourth cycle, the counter 66 ceases to count and generates an output signal on its RC line, pin 15, connected to an inverter 74. The output signal of the inverter 74 disables the counter 66, which waits for the next transition. During this time, the counter 66 ignores any transition which may occur between bit cells. A description of bit cells is presented hereinbelow.

Referring still mainly to Fig. 2, the multiplexing transceiver circuitry 36, 38, 40 and 42 isolates the system bus 34 from the MPCC 10 and also isolates three of the address lines (AO-A2) that access eight registers in the MPCC 10. Control lines are generated by the MPCC access controller 26 used to control the MPCC 10 and to isolate the system bus 34 from the local bus 44 which is connected to the MPCC 10. The system bus 34 is isolated by the two integrated circuits 36 and 38.

The multiplexer 38 switches back and forth between two sets of address input lines: AO-A2 from the microprocessor 6 and address lines from the MPCC access controller 26. The outputs (Y lines) of the multiplexer 38 switch back and forth between the sets of data inputs depending on the level of a select line(s) ffrom the MPCC access controller 26, to provide both a register address for data input and output for the MPCC 10 and a data buffer enable (DBEN) signal, used to strobe in data.

The MPCC access controller 26 handles transfers coming from the microprocessor 6, the DMA controller 7 and the transmitter state controller 12 for read or write (I/O) operations. There are therefore a number of mutually exclusive operations with which the MPCC controller 26 is involved, each operation having its own wait state and synchronizing signals which affect data transfer to the MPCC 10.

The MPCC access controller 26 allows the transmitter state controller 12 to asynchronously access the MPCC local bus 44. Software is coordinated so as not to attempt to access the MPCC 10 at certain times.

The address accessed by the MPCC 10 is manipulated by OR gates 40 and 42 and input to the multiplexer 38 to control data input to the MPCC 10. One of the inputs (pin 2A) is tied to a known state (e.g., ground).

Other inputs are ORed by gates 40 and 42 and strobed in with an I/O write (I/O WRT) signal from the microprocessor 6.

A bus access (BACCESS) line 76 is connected to the transmitter state controller 12, the MPCC access controller 26 and the multiplexer 38. This bus access line 76, when active, allows asynchronous access of the MPCC via the MPCC local bus 44 by directing the MPCC acces controller 26 to isolate the local bus 44 from the system bus 34. The address manipulation circuitry 38 is also driven by the bus access line 76 to produce the correct MPCC register address for access by the transmitter state controller 12.

The local bus 44 is driven by the bus driver 46, as hereinabove mentioned. Half of the bus driver 44 has four input lines, two of which (Al and A2 are set to drive logical zeros into appropriate MPCC control register bits (DB03 and DB02, respectively). The two other signals (A3 and A4) are generated by the transmitter state controller 12. These two signals (A3 and A4) set bits in registers DBOl and DBOO, respectively in the MPCC 10 for both the transmit end of message (TEOM) bit and the transmit start of message (TSOM) bit.

Either one of these bits DB01 and DBOO, set one at a time, signifies to the MPCC 10 that serial data transmission either is about to start or is to be terminated. Accordingly, the MPCC 10 sends appropriate flags and protocol bytes at the beginning and at the end of the data packet being transmitted. This operation would otherwise be performed by the microprocessor 6.

Upon completion of the data packet transmission, the transmitter state controller 12 generates a trap interrupt (TRAP) signal to interrupt the microprocessor 6. Signals from the transmitter state controller 12 and the MPCC 10 are sent to the DMA controller 7 to start transferring data after protocol byte transmission at the beginning of the data packet.

An OR gate 78 directly generates the trap interrupt (TRAP) signal propagated through flip flop 80 to indicate that the transmission has been completed. The interrupt gate 78 is also used to OR in an interrupt signal indicating a change in receiver status information. A receiver status available (RXSA) signal from the MPCC 10 (pin 7), applied to the OR gate 78, indicates new receiver status information such as that data packet reception has been completed or has ceased.

Device 81 generates a data request (DRQ1 signal to the DMA controller 7, requesting that a byte of data be transferred to the MPCC 10 for eventual transmission to the network channel 3. Another data request (DRQ0) signal is generated by the MPCC 10 (pin 6, RXDA) to request the DMA controller 7 to retrieve a byte of data sent to it by the MPCC 10, which byte of data was received by the MPCC 10 from the network channel 3. Only one signal, DRQ0 or DRQ1, is used at a given time, depending upon whether the system is receiving or transmitting, respectively.

During transmission, pin 35 of the MPCC 10 generates a transmit buffer empty (TXBE) signal for requesting the DMA controller 7 to transfer a byte of data to the MPCC, through the DRQ1 signal.

The microprocessor 6 initiates transmission by setting a register 82. The PROM 14 of the transmitter state controller 12 is connected to the register 82 by means of a transmit go (TxGO) signal 83. An initiating signal 84 from the microprocessor 6 is generated on the system bus 34. Driver circuitry, such as a Model No. 8830 line driver 60 is provided for driving the line. Connected to the line driver 60 via an encoder GO signal 61 is device 63.

This device 63 also applies a DATA SYNC signal 65 to the line driver 60 via gates 67 and 69 and device 71. The device 63 is connected to the MPCC 10 via another data sync line, DATA NSYNC 73.

The transmitter state controller 12 begins to prepare the MPCC 10 to transmit. When the register 82 is set, the local bus 44 is isolated from the system bus 34 by the transmitter state controller 12. The bus access signal 76, from output 7Q of latch 16, is connected to the MPCC access controller 26 and that, as mentioned hereinabove, isolates the system bus 34 from the local bus 44 to the MPCC 10 and allows the transmitter state controller to drive bus driver 46 to set the TSOM bit.

The TSOM bit resides in a register internal to the MPCC 10. At that point, the MPCC 10 begins to transmit flag bytes. After two flags have been sent, the transmitter state controller 12 resets the TSOM bit.

Upon resetting the TSOM bit, the data block is to be transmitted by the MPCC 10.

The first byte of the data block is station address information. After the data block is sent by the DMA controller 7 to the MPCC 10, the DMA controller 7 signals the transmitter state controller 12 to terminate transmission. This operation is accomplished via the transmit done (TXDONE) line in flip flop 24.

The transmitter state controller 12 then sets the TEOM bit in the same manner as the TSOM bit is set or reset. After the TEOM bit is set, the MPCC 10 transmits a cyclic redundancy check (CRC) signal for error detection and two closing flags to the network channel 3.

The transmitter state controller 12 then resets the TEOM bit to terminate transmission.

During this time the transmitter state controller 12 sets the trap interrupt via gates 78 and 80 to indicate to the microprocessor 6 that the MPCC 10 and the DMA controller 7 have completed transferring the data packet. The microprocessor 6 can then access the MPCC 10 and reset the DMA controller 7 for the next packet transfer.

Referring now also to Fig. 3, which is a timing diagram representing the signals used by the decoder circuit components 62, 64 and 66, during a decoding operation, the top line represents the system clock. The system clock operates at 5 MHz. In this example, five clock cycles are equivalent to one bit cell; each clock cycle is 200 nanoseconds. The decoder uses both the positive going edge and the negative going edge of the system clock.

The next line in Fig. 3 represents incoming data in Manchester format. In the example shown in Fig. 3, two "1" bits are transmitted, then two "0" bits are transmitted, then one "1" bit is transmitted. In the first bit cell the Manchester data goes from a low state (zero) to a high state (one). In the middle of the bit cell, a transition is made, thus being a logic "1" bit.

The third line of Fig. 3 represents the first synchronization of the flip flop 62 output. The input to this flip flop 62 is data generated indirectly from the network channel 3. Therefore, the flip flop 62 synchronizes on the negative-going edge of the system clock.

The output of flip flop 62 is also applied to the input of the second synchronizing flip flop 64. At the next negative-going edge of the system clock, 200 nanoseconds (one system clock cycle time) later, the output of flip flop 64 goes high upon sampling its inputs. When the two outputs 62 and 64 for one clock cycle time are not the same, this condition is sensed by the exclusive OR gate 68 whose transition detection pulse 48 output is active for one cycle time, and is applied to the NAND gate 70. When enabled, the NAND gate 70 initializes the counter 66 for a new count sequence.

The next line below the transition detection pulse 48 in Fig. 3 represents an output buffer enable line, generated by the counter 66 and also applied to the NAND gate 70. The NAND gate 70 disables the transition detection pulse 48, thus preventing initialization of the counter 66 so that certain transitions are ignored.

The output buffer enable line becomes active (active low) approximately 100 nanoseconds from the time at which the transition detection pulse signal becomes active.

The output buffer enable line is the ripple carry output of the counter 66. The output buffer enable line goes low for three states and then high, waiting in the high state, enabling the counter 66 (pin LD) to be initialized by the transition detection pulse 48 via the NAND gate 70. When the counter 66 is initialized, it has received a desired transition.

A transition that is detected during the middle of a bit cell (not one that is to be ignored, which may occur on bit cell partitions) is considered a desired transition.

When the counter 66 begins a counting sequence. one of the binary output bits is the correct pulse length for operating the data output clock, shown on the last line on Fig. 3.

The data output clock line drives the RxC line of the MPCC 10 which uses positive transitions of this R x C line of the MPCC 10 which uses positive transitions of this RxC line to strobe in data on input RxSI of the MPCC 10.

The next line below the output buffer enable line in Fig. 3 represents the data output line. That is the signal generated by the output latch 72 of the decoder. This data is clocked into the output latch 72 by the output buffer enable line. Upon reception of a valid transition, the output latch 72 clocks in data, sampling the data input when valid. The transition detection signal 48 requires a short time interval after being applied to the first flip flop 62 before it becomes active. Therefore the correct data is sampled from the output of the first synchronizing flip flop 62.

Correct NRZ data output is generated by the output latch 72.

The vertical arrows below the data output line on Fig. 3 indicate when the MPCC receiver status serial input (R x SI) line is sampled by the MPCC 10. The vertical arrows below the first synchronizing flip flop 62 output lines indicate when data is sampled by the output latch 72.

Below the data output line on Fig. 3, which represents data in NRZ format, is the counter state which represents the binary count present at the outputs of the counter 66. The counter 66 always counts up in binary format, read from the right hand side. The counter 66 will count only three states. The fourth state is its final state. The counter 66 sets the RC line (pin 15) and then disables itself, thus reenabling future intialization.

Referring now also to Fig. 4, which is a timing diagram representing the signals used by the encoder circuit, including the line driver 60, the top line represents a 2 MHz clock. The line below the 2 MHz clock in Fig 4 represents a transmit (TX) clock signal, below which is shown the TRANSMITTER ACTIVE (TxA) signal. Below the TxA signal is shown the encoder GO signal 61. The NRS code data synchronism NSYNC and SYNC signals 73 and 65, respectively, are then shown. One signal is the synchronized signal of the other. The last line of Fig. 4 represents data to be transmitted in Manchester code format, via the DATA line (block 8), driven by the line driver 60.

Referring now also to Fig. 5, there is shown a flow chart describing the program loaded in the transmitter state controller 12.

The first loop, shown generally at step 100, represents the functions that the transmitter state controller 12, or sequencer, performs while idling or waiting for the signal from the microprocessor 6 to start a transmission.

Upon receiving the start signal (TxGO) 83, the sequencer accesses the MPCC local bus 44 and sets the TSOM bit.

The next loop the system reaches is shown generally at step 102. The system waits for the synchronization signal from the MPCC 10 via the transmit buffer empty (TxBE) line.

After it receives that first synchronization pulse from the MPCC 10, indicating that the first flag byte has been sent, the sequencer sends redundant signals to the MPCC 10 to set the TSOM bit, ensuring that an underrun or overrun error is not generated. Each time the synchronization pulse is sent to the MPCC 10, the sequencer responds.

The next TxBE signal is received at step 1 04. The sequencer enables the DMA controller 7 to start the DMA transfer of the data block. The DMA controller 7 then sends its first byte when the TxBE signal becomes active. The transmitter state controller delays a a short while, step 1 06, for the DMA operation to be completed.

After the DMA operation is complete, the sequencer proceeds to lock out the system bus 34 and then resets the TSOM bit. Data is then transmitted by the DMA controller 7 for succeeding requests from the MPCC 10 via the TxBE signal. The sequencer then enters a loop, step 108, and waits for a transmit done (TxDONE) signal from the DMA controller 7 to indicate that the DMA controller 7 is working on the last byte of data to be transferred.

After it has received the TxDONE signal, the sequencer proceeds to the loop at step 110, where it waits for the byte indication that work is being performed on the last DMA byte to be transferred to the MPCC 10.

The sequencer then executes the loop at step 112, which is provided to wait for the DMA controller 7 to complete transfer of the byte of data to the MPCC 10. At that time the TEOM bit is set, instructing the MPCC 10 to cease transmitting. The DMA is disabled. The system then executes the loop at step 114 twice, waiting for the MPCC 10 to complete transmission of the protocol bytes, such as the CRC check byte and the closing flag to be transmitted.

The sequencer is then ready for another byte of data. At this point the TEOM bit is reset. One more flag is transmitted. The se quencer then returns to execution of the loop at step 100 and awaits the next transmission.

Since other modifications and changes varied to fit particular operating requirements and environments will be apparent to those skilled in the art, the invention is not considered limited to the examples chosen for purposes of disclosure, and covers all changes and modifications which do not constitute departures from the true spirit and scope of this invention.

Claims (27)

1. .1. A network communications system circuit adapted for use in a word processing system including a network channel, comprising: a) a system communications bus for transferring data and address information; b) a processor operatively connected to said bus for directing the transfer of data thereover;

   c) protocol control means for controlling protocol of network channel information; d) state controlling means operatively connected to said protocol control means for controlling signal synchronization and conversion, and e) multiplexing means operatively connected to said bus, to said protocol control means and to said state controlling means for selectively allowing said processor and said state controlling means to access said protocol control means.
2. 2. A network communications system circuit according to claim 1 further comprising: f) encoding means operatively connected to said protocol control means and to the network channel for encoding data into suitable format for use with the network channel.
3. 3. A network communications system circuit according to claim 1 or 2 further comprising: g) decoding means operatively connected to said protocol means and to the network channel for decoding data from network channel format for use by said processor.
4. 4. A network communications system circuit according to claim 2 or 3 wherein said format is a Manchester code.
5. 5. A network communications system circuit according to claim 2 or claim 3 or 4 as dependent upon claim 2, wherein data in nonreturn to zero code format is converted into Manchester code format.
6. 6. A network communications system circuit according to claim 3 or claim 4 or 5 as dependent upon claim 2 wherein data in Manchester code format is converted into non-return to zero code format.
7. 7. A network communications system circuit according to claim 3 or claim 4, 5 or 6 as dependent upon claim 3, wherein said decoding means comprises a counter operatively connected to said multiplexing means for delaying recognition of data from the network channel and for establishing a time window during which incoming data is not sampled by said decoding means.
8. 8. A network communications system circuit according to claim 7 wherein said counter operates asynchronously relative to incoming data.
9. 9. A network communications system circuit according to claim 7 or 8 wherein said multiplexing means includes means for detecting level transitions operatively connected to said counter for initiating a count sequence therein during which count sequence incoming data is not sampled by said decoding means.
10. 10. A net communications system circuit according to claim 9 wherein said count sequence is time dependent.
11. 11. A network communications system circuit according to claim 9 or 10 wherein said count sequence is terminated after a predetermined time interval.
12. 12. A network communications system circuit according to claim 2 or 3 or any one of claims 4 to 11 as dependent upon claim 2 or 3 further comprising: h) data storage means operatively connected to said bus for storing said data to be transferred thereover.
13. 13. A network communications system circuit according to any one of claims 1 to 12 wherein said protocol control means comprises a multi-protocol communications controller access controller.
14. 14. A network communications system circuit adapted for use in a word processing system including a network channel, comprising: a) a system communications bus for trans ferring data and address information: b) a processor operatively connected to said bus for directing the transfer of data thereover;

    c) protocol control means for controlling protocol of network channel information; d) a direct memory access controller oper atively connected to said bus for trans ferring data to said protocol control means upon request thereof; e) state controlling means operatively con nected to said protocol control means for controlling signal synchronization and con version; and f) multiplexing means operatively con nected to said bus, to said protocol control means and to said state controlling means for selectively allowing said processor, said direct memory access controller and said state controlling means to access said pro tocol control means.
15. 15. A network communications system circuit according to claim 14 further comprising: 9) encoding means operatively connected to said protocol control means and to the network channel for encoding data into suitable format for use with the network channel.
16. 16. A network communications system circuit according to claim 14 or 15 further comprising: h) decoding means operatively connected to said protocol control means and to the network channel for decoding data from network channel format for use by said processor.
17. 17. A network communications system circuit according to claim 15 or 16 wherein said format is a Manchester code.
18. 18. A network communications system circuit according to claim 15 or claim 16 or 17 as dependent upon claim 15 wherein data in non-return to zero code format is converted into Manchester code format.
19. 19. A network communications system circuit according to claim 16 or claim 17 or 18 as dependent upon claim 16 wherein data in Manchester code format is converted into non-return to zero code format.
20. 20. A network communications system circuit according to claim 16 or claim 17, 18 or 19 as dependent upon claim 16 wherein said decoding means comprises a counter operatively connected to said multiplexing means for delaying recognition of data from the network channel and for establishing a time window during which incoming data is not sampled by said decoding means.
21. 21. A network communications system circuit according to claim 20 wherein said counter operates asynchronously relative to incoming data.
22. 22. A network communications system circuit according to claim 20 or 21 wherein said multiplexing means includes means for detecting level transitions operatively connected to said counter for initiating a count sequence therein during which count sequence incoming data is not sampled by said decoding means.
23. 23. A network communications system circuit according to claim 22 wherein said count sequence is time dependent.
24. 24. A network communications system circuit according to claim 22 or 23 wherein said count sequence is terminated after a predetermined time interval.
25. 25. A network communications system circuit according to claim 15 or 16 or any one of claims 17 to 24 as dependent upon claim 15 or 16 further comprising:

    i) data storage means operatively con nected to said bus for storing said data to be transferred thereover.
26. 26. A network communications system circuit according to any one of claims 14 to 25 wherein said protocol control means comprises a multi-protocol communications controller access controller.
27. 27. A network communications system circuit substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.