GB2102230A - A pulse drive circuit - Google Patents
A pulse drive circuit Download PDFInfo
- Publication number
- GB2102230A GB2102230A GB08121942A GB8121942A GB2102230A GB 2102230 A GB2102230 A GB 2102230A GB 08121942 A GB08121942 A GB 08121942A GB 8121942 A GB8121942 A GB 8121942A GB 2102230 A GB2102230 A GB 2102230A
- Authority
- GB
- United Kingdom
- Prior art keywords
- circuit
- input
- coupled
- output
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
- H03F3/3081—Duplicated single-ended push-pull arrangements, i.e. bridge circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0266—Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
- H04L25/0268—Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling with modulation and subsequent demodulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/33—Bridge form coupled amplifiers; H-form coupled amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/541—Transformer coupled at the output of an amplifier
Abstract
A pulse drive circuit comprises a first input (4) for a pulse signal and a second input (3) for a high frequency clock signal. A logic circuit (1C1b) is coupled with the first and second inputs (4, 3) and is arranged to provide a combined signal output of the form of the clock frequency modulated by the pulse signal. A comparator (1C3a) has one input coupled with the combined signal output and another input coupled with the second circuit input and is arranged to demodulate the output from the modulator (1C1b) and provide an output signal which is representative of the pulse signal. Either a true or complementary output may be obtained depending on the state of a binary sense signal at a further input (2). The invention finds application in circuits where well regulated variable pulse drives are required and is particularly suitable for driving inverters and in the production of class D (pulse) amplifiers. <IMAGE>
Description
SPECIFICATION
A pulse drive circuit
This invention relates to a pulse drive circuit and more particularly but not solely to a pulse drive circuit suitable for driving a mosfet bridge circuit to form an inverter or class D power amp.
It is difficultto produce a linear class D power amplifier (i.e. pulse width modulated) which is responsive to pulses of duration from D.C. down to several hundred nanoseconds and which provides sufficient isolation between input and output signals. The use of straight transformer techniques has the disadvantage that the drive level varies with mark to space ratio. This results in a loss of efficiency of drive when a mosfet bridge power amplifier is driven by such an arrangement as the transistors are not always driven at their optimum voltage to ensure low onresistance. In addition straight transformer drive will necessarily have a low frequency cut off.
The use of opto-isolator drives is not subject to the above disadvantages but has the disadvantage of a low upper frequency response and requires a separate isolated power supply.
The present invention seeks to provide an improved drive circuit in which at least some of the before mentioned disadvantages are obviated.
According to the invention there is provided a pulse drive circuit comprising a first input for a pulse signal, a second input for a high frequency clock signal, logic circuit means coupled with said first and second inputs and arranged to provide a combined signal output of the form of the clock frequency modulated by the pulse signal and comparator means having an input coupled with said combined signal output and another input coupled with said second circuit input which comparator is arranged to be non-responsive to the common clock signal components and to provide an output signal which is representative of the pulse signal.
The comparator means is preferably coupled with said combined signal output via a transformer.
The second input may be coupled with the comparator means via a transformer.
In order that the invention and its various other preferred features may be understood more easily, embodiments thereof will now be described, by way of example only, with reference to the drawings, in which: Figure 1 is a schematic circuit diagram of a pulse drive circuit constructed in accordance with the invention;
Figure 2 is a waveform diagram showing signals which occur at different points in the circuit of Figure 1;
Figures 3a and 3b show pulse conditioning circuits for use with the circuit of Figure 1;
Figure 4 is a circuit diagram of a power amplifier employing a voltage fed inverter driven by the pulse drive circuit of Figure 1; and,
Figure 5 is a circuit diagram of a power amplifier employing a current fed inverter driven by the pulse drive circuit of Figure 1.
Referring now to Figures 1 and 2. Waveforms at points A to K in Figure 1 are shown in Figure 2.
The drive circuit comprises four integrated circuits 1C1, 1C2, 1C3,and 1C4. 1C1 and 1C3 are type
MM74C86 CMOS circuits each comprising four exclusive OR gates. 1 C2 and 1 C4 are type
DS0026CG MOS circuits each comprising two inverting amplifiers. One of the exclusive OR gates 1 Cl c has one input connected to a negative supply line An and its other input biased via a resistor R2 from the positive supply line A+ and connected to a circuit input 3 for a clock signal.
The clock signal is a square waveform as shown in Figure 2A and its frequency is not critical e.g.
10 KHz to 5 MHz. The output of the gate 1 C 1 c is a replica of the clock signal and is connected to one input of each of two exclusive OR gates 1 Cl a and 1C1b.Theotherinputofgate Claims connected via a resistor R1 to the positive supply line A+ and also optionally to an input 2 which forms a sense input. The sense input 2 provides a selectible logic "0" (as in waveform 2D) or "1" input. The output of 1 Cl a therefore provides the clock waveform as in waveform 2E when the sense input is "O" or an inverted clock waveform if the sense input is "1".
The other input of gate 1 Cl b is coupled to the positive supply line A+ by a resistor R3 and also to an input 4 for a pulse drive waveform B. The output waveforms of 1 Cl b is ullustrated as waveform C and is the combination of the clock waveform and pulse drive waveform. The outputs of the two gates 1 C 1 a and 1C1b are routed via capacitance/resistance circuitry C1/R4 and
C2/R5, inverting amplifiers 1C2 and 1C2b and capacitors C3 and C4 to the primary windings of transformers T1 and T2 respectively. The secondaries of the transformers are each provided with a bridge rectifier circuit BR1 and BR2 the d.c.
outputs of which circuits are combined to provide an isolated d.c. supply B+, B- for a differential drive circuit.
The secondaries of the transformers are also connected to different inputs of a comparator formed by an exclusive OR circuit 1 C3a via resistors R6 and R7 respectively so that the two inputs are transformed versions of waveforms E s C and the output waveform F is provided by the gate. This waveform is a replica of the pulse drive waveform B. If the sense input is logic "1" then the waveform is inverted as is waveform G. The carrier voltage at T1 and T2 secondary determines the drive voltage, which remains virtually independant of the drive waveform. Drive pulses from d.c. down to 400 nanoseconds width have been obtained. The output of 1 C3 is coupled via resistor R8 to one input of each of two exclusive OR gates 1 C3b, 1 C3c.The resistor forms with the input capacitance of the two gates a low pass filter which smooths at glitches due to propagation errors and provides the waveform H or J. The other input of 1 C3b is connected via a resistor R9 to supply line B+ and the other input of 1 C3c is connected to supply line B-. The output waveforms from 1 C3b and 1 C3c in the case of waveform H are shown as J and K respectively and as can be seen they provide differential waveforms. The differential states would be inverted in the case of waveform I.
The outputs of 1 C3b and 1 C3c are coupled via resistance/capacitance circuits R 1 0/C6 and
R1 1/C7 and inverting amplifiers IC4a and IC4b to differential output lines 6 and 7 respectively.
Accordingly the output between 6 and 7 is a differential waveform which is representative of the pulse drive waveform on input 4 and is erect or inverted in dependence upon whether the sense input 2 is "O" or "1". The input 4 and the output 6/7 are isolated by virtue of the transformers T1 and T2 and separate supplies A+/A-- and B+/B-- and the output amplitude is substantially independent of the pulse drive frequency. The circuit has applications in any situation requiring well regulated, variable width, isolated pulse drives e.g. switch mode power supply configurations and inverters, d.c.
converters and power amplifiers and has immediate application in class D sonar transmitter output stages. Instead of employing the external clock drive an internal clock may be employed which may be derived using the spare element of 1C1 to form an oscillator.
In some circumstances it is useful to have a different switching delay when changing between one differential state and the other as compared with switching in the opposite direction. One such circumstance is in switching applications where the driver is to feed switches in which an overlapping condition has to be avoided (e.g.
voltage fed bridge inverter) or guaranteed (e.g.
current fed bridge inverter) as hereinafter described. In these circumstances the circuits of
Figures 3a and 3b can be employed depending upon which transition direction is to be extended in time. In these circuits resistor R8 is bridged by a diode and a resistor in series. This results, in the case of Figure 3a, in a reduced delay of a positive going pulse as the diode D is forward biased and effectively connects resistor R8a in parallel with R8 causing an effective reduction in resistance of the circuit. In the case of a negative going pulse the diode is reverse biased and the resistance of the circuit is substantially equal to R8.
Referring now to a particularly advantageous extension of the invention, Figures 4 and 5 show power drive circuits comprising a bridge inverter and rectifier circuit driven by drive circuits as hereinbefore described. Figure 4 is a voltage fed inverter comprising four semiconductor switches 11, 12, 13, 1 4 e.g. mosfet or thyristor switches.
Switches 11 and 12 are connected in series between positive and negative lines of a power source as are also switches 13 and 14. The junctions of switches 11/12 and 13/14 are coupled via the primary winding of a transformer
T3. Each of the switches 11 to 14 are provided with a differential voltage drive input from outputs 6 and 7 of a different drive as illustrated in Figure 1. Alternatively the circuit part of Figure 1 following the transformers T1 and T2 can be repeated four times, the transformers T1 and T2 would then be provided with four secondary windings, one for each subsequent circuit, and the circuitry prior to the transformers would be common thereby reducing the overall drive circuit cost for this application.The differential voltage drives to the switches are arranged such that switches 11 and 14 are on when switches 12 and 13 are off and vice versa.
The secondary of the transformer T3 is coupled via a rectifier 1 5 to outputs 1 6 and 17 where high power replica of the pulse drive waveform is available. Such a power output is suita-ble for driving for example a sonar transducer. The drive circuit used with the circuit of Figure 4 preferably employs the circuit of Figure 3a so that any risk of switches 1 1/14 and 12/13 being on simultaneously is obviated.
The circuit of Figure 5 is identical with that of
Figure 4 except that the positive supply line includes an inductor L i.e. the inverter is current fed. Where this circuit is employed the drive circuit of Figure 1 preferably includes the circuit of
Figure 3b to ensure that there is an overlap between the ON conditions of switches 1 1/14 and 1 2/1 3 to avoid the generation of voltage spikes.
It will be appreciated that the circuits of
Figures 4 or 5 can be employed without the rectifiers and driven by drivers 1 which are fed with a repetitive pulse waveform input e.g.
square wave to form an inverter which provides an isolated alternating current power source.
Such an arrangement is intended to fall within the scope of this invention. Suitable use of the sense inputs enables inversion of the output of the inverter with no extra components required.
Claims (20)
1. A pulse drive circuit, comprising a first input for a pulse signal, a second input for a high frequency clock signal, logic circuit means coupled with said first and second inputs and arranged to provide a combined signal output of the form of the clock frequency modulated by the pulse signal and comparator means having an input coupled with said combined signal output and another input coupled with said second circuit input, which comparator is arranged to be non-responsive to the common clock signal components and to provide an output signal which is representative of the pulse signal.
2. A circuit as claimed in claim 1, wherein the comparator means is coupled with the combined signal output via a coupling transformer.
3. A circuit as claimed in claim 2, wherein the second input is coupled with the comparator via a transformer.
4. A circuit as claimed in any one of the preceding claims, wherein the logic circuit means comprises an exclusive OR gate having a first input arranged to receive the pulse signal, a second input arranged to receive the clock frequency and an output for said combined signal.
5. A circuit as claimed in any one of the preceding claims wherein the second input is coupled with one input of an exclusive OR gate which has a second input coupled with an input for a control signal, the logic value of which determines whether the output of the exclusive
OR gate is in erect or inverted form.
6. A circuit as claimed in any one of the preceding claims, wherein the output of the comparator is coupled with one input of each of two exclusive OR gates, one of which gates has its other input coupled with one supply line of a d.c. supply source such that the two exclusive OR gates provide differential output drive signals.
7. A circuit as claimed in claim 6 when dependent directly or indirectly from claim 2 or 3, wherein the or each transformer has its secondary winding coupled with a bridge rectifier arranged to provide said d.c. supply source, which source is d.c. isolated from the previous circuitry.
8. A circuit as claimed in claim 6 or 7, wherein the output of the comparator is coupled with the input of said two exclusive OR gates via a resistor arranged to form with the input capacitance of the OR gates a low pass filter which blocks glitches caused by ringing and propagation errors.
9. A circuit as claimed in claim 6 or 7, wherein the output of the comparator is coupled with the input of said two exclusive OR gates by a delay circuit arranged to introduce an increase in delay in triggering of said two exclusive OR gates between first and second states but not in the reverse direction.
10. A circuit as claimed in claim 9, wherein the delay circuit comprises a resistor in series with a diode which series arrangement is connected in parallel with another resistor.
11. A pulse drive circuit substantially as described herein with reference to Figures 1 and 2 and as illustrated in Figure 1 of the drawings.
12. An inverter circuit, comprising four semiconductor switches connected in bridge configuration with the primary winding of a transformer, the secondary of which transformer provides an inverter output signal, wherein the semiconductor switches are each actuated by the output signal of a pulse drive circuit as claimed in any one of the preceding claims.
1 3. An inverter circuit, comprising four semiconductor switches connected in bridge configuration with the primary winding of a transformer, the secondary of which transformer provides an inverter output signal, the amplifier being provided with a drive circuit as claimed in claim 2 or any one of claims 3 to 11 when dependent from claim 2 wherein four separate comparators and subsequent circuits are provided each coupled with said combined signal via a different secondary winding of said coupling transformer and the semiconductor switches are each actuated by the output signal of a different comparator.
14. An inverter as claimed in claim 12 or 13, wherein the semiconductor switches are mosfets.
1 5. An inverter circuit as claimed in claim 12, 1 3 or 14 when dependent from claim 9 or 10, wherein the bridge circuit is of voltage fed configuration and the delay circuits are arranged to delay the ON transition of the semiconductor switches to avoid a simultaneous on condition of the switches.
1 6. An inverter circuit as claimed in claim 12, 13 or 14 when dependent from claim 9 or 10, wherein the bridge circuit is of a current fed configuration and the delay circuits are arranged to delay the off transition of the semiconductor switches to avoid a simultaneous off condition of the switches.
1 7. A class D power amplifier including an inverter circuit as claimed in any one of claims 12 to 16 wherein the inverter output signal is coupled via a rectifier circuit to an output to provide d.c. pulse power in response to a pulse input on said first input of the pulse drive circuit.
18. An inverter substantially as described herein with reference to the drawings.
19. A class D power amplifier substantially as described herein with reference to the drawings.
Amendments to Claims filed on 30 June 82.
Amended Claims: Claim 2. A circuit as claimed in claim 1 including a clock frequency generator coupled with said second input for providing a self generated clock signal.
Appendant claim 2 renumbered 3 and made appendant to claims 1 or 2.
Appendant claims 3-19 renumbered 4-20 and appendancies correspondingly renumbered.
1. A pulse drive circuit, comprising a first input for a pulse signal, a second input for a high frequency clock signal, logic circuit means coupled with said first and second inputs and arranged to provide a combined signal output of the form of the clock frequency modulated by the pulse signal and comparator means having an input coupled with said combined signal output and another input coupled with said second circuit input, which comparator is arranged to be non-responsive to the common clock signal components and to provide an output signal which is representative of the pulse signal.
2. A circuit as claimed in claim 1, including a clock frequency generator coupled with said second input for providing a self generated clock signal.
3. A circuit as claimed in claim 1 or 2, wherein the comparator means is coupled with the combined signal output via a coupling transformer.
4. A circuit as claimed in claim 3, wherein the second input is coupled with the comparator via a transformer.
5. A circuit as claimed in -any one of the preceding claims, wherein the logic circuit means comprises an exclusive OR gate having a first input arranged to receive the pulse signal, a second input arranged to receive the clock frequency and an output for said combined signal.
6. A circuit as claimed in any one of the preceding claims wherein the second input is coupled with one input of an exclusive OR gate which has a second input coupled with an input for a control signal, the logic value of which determines whether the output of the exclusive
OR gate is in erect or inverted form.
7. A circuit as claimed in any one of the preceding claims, wherein the output of the comparator is coupled with one input of each of two exclusive OR gates, one of which gates has its other input coupled with one supply line of a d.c. supply source such that the two exclusive OR gates provide differential output drive signals.
8. A circuit as claimed in claim 7 when dependent directly or indirectly from claim 3 or 4, wherein the or each transformer has its secondary winding coupled with a bridge rectifier arranged to provide said d.c. supply source, which source is d.c. isolated from the previous circuitry.
9. A circuit as claimed in claim 7 or 8, wherein the output of the comparator is coupled with the input of said two exclusive OR gates via a resistor arranged to form with the input capacitance of the OR gates a low pass filter which blocks glitches caused by ringing and propagation errors.
10. A circuit as claimed in claim 7 or 8, wherein the output of the comparator is coupled with the input of said two exclusive OR gates by a delay circuit arranged to introduce an increase in delay in triggering of said two exclusive OR gates between first and second states but not in the reverse direction.
1 A circuit as claimed in claim 10, wherein the delay circuit comprises a resistor in series with a diode which series arrangement is connected in parallel with another resistor.
12. A pulse drive circuit substantially as described herein with reference to Figures 1 and 2 and as illustrated in Figure 1 of the drawings.
1 3. An inverter circuit, comprising four semiconductor switches connected in bridge configuration with the primary winding of a transformer, the secondary of which transformer provides an inverter output signal, wherein the semiconductor switches are each actuated by the output signal of a pulse drive circuit as claimed in any one of the preceding claims.
14. An inverter circuit, comprising four semiconductor switches connected in bridge configuration with the primary winding of a transformer, the secondary of which transformer provides an inverter output signal, the amplifier being provided with a drive circuit as claimed in claim 3 or any one of claims 4 to 12 when dependent from claim 3 wherein four separate comparators and subsequent circuits are provided each coupled with said combined signal via a different secondary winding of said coupling transformer and the semiconductor switches are each actuated by the output signal of a different comparator.
1 5. An inverter as claimed in claim 13 or 14, wherein the semiconductor switches are mosfets.
1 6. An inverter circuit as claimed in claim 13, 14 or 1 5 when dependent from claim 10 or 11, wherein the bridge circuit is of voltage fed configuration and the delay circuits are arranged to delay the ON transition of the semiconductor switches to avoid a simultaneous on condition of the switches.
1 7. An inverter circuit as claimed in claim 13, 14 or 1 5 when dependent from claim 10 or 11, wherein the bridge circuit is of a current fed configuration and the delay circuits are arranged to delay the off transition of the semiconductor switches to avoid a simultaneous off condition of the switches.
1 8. A class D power amplifier including an inverter circuit as claimed in any one of claims 13 to 17 wherein the inverter output signal is coupled via a rectifier circuit to an output to provide d.c. pulse power in response to a pulse input on said first input of the pulse drive circuit.
1 9. An inverter substantially as described herein with reference to the drawings.
20. A class D power amplifier substantially as described herein with reference to the drawings.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08121942A GB2102230A (en) | 1981-07-16 | 1981-07-16 | A pulse drive circuit |
| NL8202850A NL8202850A (en) | 1981-07-16 | 1982-07-14 | IMPULSE SEND CIRCUIT. |
| FR8212397A FR2509930A1 (en) | 1981-07-16 | 1982-07-15 | IMPULSE PILOTAGE CIRCUIT FOR POWER CONVERTERS AND AMPLIFIERS |
| DE19823226535 DE3226535A1 (en) | 1981-07-16 | 1982-07-15 | PULSE SIGNAL DRIVER CIRCUIT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08121942A GB2102230A (en) | 1981-07-16 | 1981-07-16 | A pulse drive circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2102230A true GB2102230A (en) | 1983-01-26 |
Family
ID=10523288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08121942A Withdrawn GB2102230A (en) | 1981-07-16 | 1981-07-16 | A pulse drive circuit |
Country Status (4)
| Country | Link |
|---|---|
| DE (1) | DE3226535A1 (en) |
| FR (1) | FR2509930A1 (en) |
| GB (1) | GB2102230A (en) |
| NL (1) | NL8202850A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0211210A1 (en) * | 1985-07-20 | 1987-02-25 | Licentia Patent-Verwaltungs-GmbH | Switching amplifier |
| EP0319085A1 (en) * | 1987-11-30 | 1989-06-07 | AT&T NETWORK SYSTEMS NEDERLAND B.V. | Digital transmission with galvanic separation in video circuits |
| WO1999048272A1 (en) * | 1998-03-16 | 1999-09-23 | Midcom, Inc. | Digital isolation apparatus and method |
| WO2000030333A1 (en) * | 1998-11-16 | 2000-05-25 | Conexant Systems, Inc. | Modem having a digital high voltage isolation barrier |
| US6359973B1 (en) | 1998-11-16 | 2002-03-19 | Conexant Systems, Inc. | Data access arrangement utilizing a serialized digital data path across an isolation barrier |
| EP1633046A2 (en) * | 2004-09-01 | 2006-03-08 | Kabushiki Kaisha Toshiba | Digital signal transfer device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CH477785A (en) * | 1968-02-05 | 1969-08-31 | Hasler Ag | Electronic relay |
| GB1398237A (en) * | 1971-05-07 | 1975-06-18 | Cambridge Consultants | Liquid crystal display means |
| JPS5728966B2 (en) * | 1973-08-22 | 1982-06-19 | ||
| US4170740A (en) * | 1978-02-24 | 1979-10-09 | International Telephone And Telegraph Corporation | High voltage switch and capacitive drive |
-
1981
- 1981-07-16 GB GB08121942A patent/GB2102230A/en not_active Withdrawn
-
1982
- 1982-07-14 NL NL8202850A patent/NL8202850A/en not_active Application Discontinuation
- 1982-07-15 FR FR8212397A patent/FR2509930A1/en not_active Withdrawn
- 1982-07-15 DE DE19823226535 patent/DE3226535A1/en not_active Withdrawn
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0211210A1 (en) * | 1985-07-20 | 1987-02-25 | Licentia Patent-Verwaltungs-GmbH | Switching amplifier |
| EP0319085A1 (en) * | 1987-11-30 | 1989-06-07 | AT&T NETWORK SYSTEMS NEDERLAND B.V. | Digital transmission with galvanic separation in video circuits |
| WO1999048272A1 (en) * | 1998-03-16 | 1999-09-23 | Midcom, Inc. | Digital isolation apparatus and method |
| US6169801B1 (en) | 1998-03-16 | 2001-01-02 | Midcom, Inc. | Digital isolation apparatus and method |
| WO2000030333A1 (en) * | 1998-11-16 | 2000-05-25 | Conexant Systems, Inc. | Modem having a digital high voltage isolation barrier |
| US6351530B1 (en) | 1998-11-16 | 2002-02-26 | Conexant Systems, Inc. | Modem having a digital high voltage isolation barrier |
| US6359973B1 (en) | 1998-11-16 | 2002-03-19 | Conexant Systems, Inc. | Data access arrangement utilizing a serialized digital data path across an isolation barrier |
| US6647101B2 (en) | 1998-11-16 | 2003-11-11 | Conexant Systems, Inc. | Data access arrangement utilizing a serialized digital data path across an isolation barrier |
| EP1633046A2 (en) * | 2004-09-01 | 2006-03-08 | Kabushiki Kaisha Toshiba | Digital signal transfer device |
| EP1633046A3 (en) * | 2004-09-01 | 2009-10-21 | Kabushiki Kaisha Toshiba | Digital signal transfer device |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2509930A1 (en) | 1983-01-21 |
| NL8202850A (en) | 1983-02-16 |
| DE3226535A1 (en) | 1983-02-03 |
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