GB2101458A - Squelch circuitry for receivers - Google Patents

Abstract

Squelch circuitry squelches 48 an incoming signal IN when speech detecting means, which responds to the values of a plurality of parameters related to speech, indicates the absence of speech in the signal. One of the parameters is the amplitude asymmetry of the signal while others include the zero crossing point frequency and energy content of the signal. The amplitude asymmetry is monitored by circuitry including a plurality of phase shifters 14 which phase shift the signal by differing amounts including zero, a plurality of peak detectors 16 coupled to the outputs of the phase shifters for sensing the positive and negative amplitude peaks of the phase shifter outputs, comparator circuitry for determining the difference between the positive and negative amplitude peak of the phase shifter outputs, and threshold apparatus for providing an output indication when the difference between the positive and negative amplitude peaks exceeds a given threshold for at least one of the phase shifter outputs. The outputs of the speech detecting means are multiplexed to a digital microprocessor 44 which controls squelching. <IMAGE>

Description

SPECICIFICATION Squelch circuitry for receivers The present invention is concerned in general with communication apparatus and more particularly with squelch circuitry used in radio receivers.

Squelch circuitry has been in use for a long time with receivers to inhibit the incoming or received signals in the absence of speech signals.

The incoming signals contain noise signals generated, for example, by atmospheric conditions or machine generated noise, along with speech signals. If there are no speech signals detected then the incoming signal is squelched or inhibited. If speech signals are detected then the received signal is allowed to pass through the receiving circuitry to the sound transducers such as loud-speakers or earphones. Known squelch circuitry merely used filters to filter out speech signals from the noise signals to thereby determine when speech signals were present.

As the circuitry became more sophisticated, various characteristics or parameters of speech have been used for determining that speech signals are actually present. Some of the prior art circuitry tried to use the amplitude asymmetry in superimposed frequency dependent phase shifted waveforms of speech signals to distinguish the speech from noise per "Positive voice operated transmitter control" Technical Report AFAL-TR 67-86.

The approach taken was not found to be satisfactory, however, because of perceived phase shifts induced by the receiver circuitry such as the microphone and signal processing circuitry which often prevented detection of the amplitude asymmetry even during the presence of voice signals. A voice detector based on detection of the amplitude asymmetry of the voice of speech signals was therefore rejected and abandoned as impracticable.

Circuitry for detecting speech, in general, encounters inherent problems. One of the problems is the false detection of speech signals, that is the speech detector picks up signals which it interprets as speech when there are, in fact, no speech. signals present on the incoming lines. The other problem Is the misdetection of speech. That is, the actual speech signals are not detected: When actual speech signals are not detected, the incoming received signal is squelched and the speech is missed. A graph of false detection against misdetection is a hyperbolic function. The object of squelch circuitry is to bring the hyperbola as close as possible to the axes, i.e. to detect the speech with a minimum of false detections and a minimum of misdetections.

The problem of speech detection is especially acute when there is a high noise level. The higher the noise level relative to the level of speech the harder it is to detect speech signals.

According to one aspect of the invention, there is provided, squelch circuitry for use in receivers having high noise levels to squelch the incoming received signals in the absence of speech signals, comprising: squelch means; speech detecting means for detecting the speech signals among noise signals, the speech detecting means comprising parameter examining means for examining parameters of a plurality of speech characteristics to obtain values; means for using the values for determining whether speech is present in the incoming signals; and means responsive to the detection of speech for inhibiting the squelch circuitry to enable the passage of the incoming signals through the squelch means.

According to another aspect of the invention, there is provided voice detection circuitry for operation in a high voice environment, comprising: at least one phase shifter arranged to phase shift a received signal by a selected amount; a plurality of peak detectors, each receiving an input signal which is phase shifted by a different amount, selected from the received signal or the outputs of the at least one phase shifter, for sensing the positive and negative amplitude peaks of the respective input signal; and comparator circuitry for determining the difference between the positive and negative peaks of the peak detector inputs and for comparing the difference with a predetermined threshold to provide an output indication when the threshold is exceeded.

It is thus possible to provide speech detectors for use with squelch circuitry in receivers.

It is also possible to provide electronic circuitry for detecting speech signals by examining the signals under the control of control processing units to determine whether or not any characteristics of speech signals are present.

It is further possible to provide reliable squelch circuitry for receivers based on the detection of amplitude asymmetry in the superimposed frequency dependent phase shifted waveforms of the speech signal.

It is also possible to detect a multiplicity of characteristic speech parameters in the incoming signals.

It is further possible to determine whether or not there are parameters indicating voice or speech signals in the incoming signals and weighing each of the discovered parameters, summing the weighted parameters and then using the sum of the weighted parameters for finally determining whether or not speech signals are present.

It is also possible to utilize a multiplicity of voice characteristic detection circuits under the control of control processor units which also controls hang-over circuitry to assure that there is no chopping of the incoming speech.

It is further possible to provide a delay for the incoming signal to assure that there is no chopping at the beginning of the speech.

In a preferred embodiment of a squelch circuit for a receiver, the incoming signals from the receiver of known or conventional construction are supplied through automatic gain control circuitry to control squelching means. The incoming signals are also supplied through a delay circuit to the squelching means. The squelching means is controlled by a multiplicity of speech characteristic parameter detectors.

There is thus provided in accordance with an embodiment of the present invention voice detection circuitry for operation in a high noise environment and comprising a plurality of phase shifters operative to phase shift a received signal by differing amounts, a plurality of peak detectors coupled to the outputs of the phase shifters for sensing the positive and negative amplitude peaks of the phase shifter outputs, comparatory circuitry for determining the difference between the positive and negative amplitude peaks of the phase shifter outputs, and threshold apparatus for providing an output indication when the difference between the positive and negative amplitude peaks exceed a given threshold for at least one of the phase shifter outputs.

Another of the characteristics which may be examined is the number of times the incoming signal crosses the zero axis in the amplitude vs.

time mode. It is known that noise and speech have different zero crossover characteristics.

Another characteristic which may be examined by the circuitry of the preferred embodiment is the energy content of the first formant of the incoming signal in the amplitude vs. frequency mode.

Further circuitry may be provided in the preferred embodiment to examine the energy content of the first derivative of the first formant to determine whether or not speech signals are present among the noise signals of the incoming signals.

Yet another characteristic which may be examined is the energy content of the second formant of the incoming signal as shown in the amplitude vs. frequency graph of the incoming signals.

The outputs of the circuits used in examining the signal for each of the characteristics may be provided with weighted values, determined by statistical tables, showing the likelihood of voice signals being present. The weighted characteristics are summed. The sum is used for finally making a determination of whether or not speech signals are present in the incoming signals. The output signal indicating that speech has been detected passes through hang-over circuitry prior to operating the squelching means, to pass the incoming signal. The incoming signal is delayed prior to arriving at the squelching means to avoid chopping the beginning of the speech signals, pending detection of voice.

Such circuitry enables extremely reliable determinations of whether or not speech signals are present in the incoming signal so that false detection and missed detection are both minimized. The described circuitry is especially useful in the presence of noise signals having an amplitude of the order of the speech signals. The circuitry is fast, efficient, lightweight and economical, and is therefore particularly suited to field operations.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a simplified block diagram of squelch circuitry for use with receivers, constituting a preferred embodiment of the invention: Figure 2, comprising Figures 2/1 and 2/2 is a schematic illustration of a portion of the squelch circuitry of Figure 1 including the circuitry used for the amplitude asymmetry detection; Figure 3, comprising Figures 3/1, 3/2, 3/3, and 3/4, is a schematic illustration of another portion of the squelch circuitry of Figure 1; Figure 4 is a schematic diagram of zero crossover detection circuitry; Figure 5 is a schematic diagram of circuitry used for the detection of the energy content of the first formant;; Figure 6 is a schematic diagram of circuitry for detecting the energy content of the differential change of the first formant; Figure 7 is a schematic diagram circuitry used for the detection of the energy content of the second formant; and Figure 8, comprising Figures 8/1, 8/2, 8/3, and 8/4, shows C.P.U. program flow charts.

The block diagram of Figure 1 shows the signal coming from any well known receiver such as a single side band receiver to an automatic gain control unit 10, described hereinafter in detail.

The output of the automatic gain control circuit 10 goes to a band pass filter 12 of conventional construction having a pass band of 300-700 Hz.

The output of band pass filter 1 2 is supplied in parallel to a plurality of phase shifters 14, typically five in number. Each phase shifter shifts the phase of the output of the band pass filter 12 by a predetermined different amount. The five phase shifts are differing functions of the frequency of the input signal. The construction of the phase shifters 1 4 will be described hereinafter in detail.

The output of each phase shifter 14 is supplied to a respective peak detector 1 6. A sixth peak detector 1 8 receives an input directly from the output of band pass filter 12 without phase shift.

The outputs of the peak detectors 1 6 and 1 8 are supplied to a multiplexer 40, is supplied to an A/D converter 42 and the digital output of the A/D converter is supplied to a Central Processing Unit 44 comprising an Intel 8080 chip embodied in an SDK-80 card, manufactured by Intel.

The CPU 44 output is connected to a hangover circuit 46 and the output of hangover circuit 46 is supplied as a control input to a switch 48. The switch 48 receives the received signal from the receiver which first passes through a delay circuit 50 and selectably couples it to the output circuitry, such as an amplifier and loudspeaker, in response to the control input. The switch is closed in response to voice detection and for a time following such detection determined by the hangover circuit 46.

The circuitry described hereinabove is based on the fact that voice is comprised at a basic frequency, termed the pitch frequency, typically in the range of 120-200 Hz. and harmonics thereof. It is known that the combined waveform illustrating the sum of the pitch frequency and the harmonics of normal human speech displays a noticeable asymmetry, in that there is a difference in the peak amplitudes of the positive and negative peaks which occur during each cycle of the pitch frequency. This asymmetry enables voice to be detected over noise of approximately the same amplitude level as the voice signal, since the noise, being random, does not display the noticeable asymmetry.

In contrast to the unsuccessful abandoned prior art attempt which involved analysis of a single phase shifted channel, the received signal is analyzed to detect the voice asymmetry at a number of phase shifts in order to take into account possible phase shifts caused by microphones or other portions of the transmission apparatus.

Also, the use of digital circuitry enables efficient and accurate operation of the voice detection apparatus to produce high reliability which was absent in the prior art and which is required for successful operation of the squelch apparatus.

The hangover circuitry 46 is operative to maintain the switch 48 in a closed condition for a predetermined amount of time following voice detection. The predetermined time duration is selected to correspond to a normal expected time separation between voice detection during a normal conversation and is intended to prevent chopping of the conversation due to normal pauses in voice transmissions in the course of the conversation.

The delay circuit 50 has two functions. One is to delay the received signal by a time duration equal to the decision time required by the remainder of the circuitry to determine whether voice is present and to close switch 48. The second function is to provide a sufficient delay of the signal to take into account an initial failure to detect the voice thereon and nevertheless to enable the subsequent detection to result in closing of switch 48 in time to transmit the received voice signals to the output.

The output of the automatic gain control circuit also is coupled to zero crossing detection circuitry 11. The output of the zero crossing detection circuit 11 is coupled to the input of the C.P.U. unit 44.

The output of automatic gain control circuitry 10 also is shown directed to means for determining the energy content of the signal; more particularly another pair of band pass filters is shown. The band pass filter 13 has a band extending from 300 Hz. to 900 Hz. The other band pass filter 15 has a band extending from 1300 to 1800 Hz.

The band pass filters 1 3 and 1 5 are coupled to absolute value circuits 1 7 and 22 respectively, where the absolute value of the signal received from the band pass filters is obtained. The absolute values are then integrated by integrator networks 21 and 23, respectively. The output P, of the integrator 21 is the energy content in the first formant and the output P2 of the integrator 3, is the energy content of the second formant. The values P1 and P2 are supplied to the multiplex circuit 40 and from there through the analog-todigital converter 42 to the CPU 44 for analysis against a statistical table in the CPU memory.

The table provided to the CPU takes into consideration the differences in the energy distribution in speech signals and in noise signals.

Thus, the amount of energy obtained from the first and second formants are used with tables in the CPU to obtain weighted value numbers to use in the final determination of whether or not speech is present.

Yet another parameter is used to aid in determining whether or not speech signals are present in the incoming signals. More particularly, as shown in Figure 1 , the output of the bandpass filter 1 3 is also supplied to a differentiator circuit 31. The output of the circuit 31 is the slope of the first formant of the incoming signal which is then operated on by an absolute value circuit 32. The output P3 of an integrator 33 is the energy level of the different values of the amplitude values of the first formant at succeeding times.

Reference is now made to the schematic iilustration of Figure 2. AGC circuitry 10 receives a signal from a receiver (not shown) at an analog input 100. The input is supplied across a 6.8 K resistor 102 and a 68 nF capacitor 104 and a 51 ohm resistor 106 to the drain of a 2N4392 FET 1 36. The change in resistance of the FET is essential to the operation of the AGC. Resistors 102 and 106 and capacitor 104 define a voltage divider which is series coupled to the FET. The junction of capacitor 104 and resistor 106 is coupled to the non-inverting input of a 4558 operational amplifier 110. When an analog input voltage at terminal 100 increases, the output of operational amplifier 110 also increases.

Operational amplifier 110 is provided with negative feedback via a 1 60 K ohm resistor 11 2.

The output of the operational amplifier is also supplied across a 1 00 ohm resistor 114 to a junction 116 which defines an AGC output terminal. Junction 11 6 is connected via a 200 ohm resistor 118 and an 1 N91 4 diode 120 to the emitter of a 2N2907 transistor 122 whose base is coupled to ground across a 2.61 K resistor 124, and is coupled to a 1 5 V positive voltage source across a 10 K resistor 126. The collector of transistor 122 is connected via a 1 5 microfarad capacitor 128 and a 470 K resistor 130 connected in parallel to a -15 Volt source. The collector of transistor 1 22 is also connected via a 1 N5233 diode 132 to ground and is coupled across a 470 K resistor 134 to the gate of the FET 136. The gate of FET 136 is connected to the drain thereof by a 470 K resistor 1 38 and by a 3 nF capacitor 140. The source of the FET is coupled directly to ground.

When the voltage level at terminal 11 6 increases above a predetermined level, the transistor 1 22 is turned on which causes charging of capacitor 128. As the capacitor 128 is charged, the voltage at the gate of FET 1 36 increases, decreasing the resistance between the drain and the source of the FET and consequently lowering the voltage at the non-inverting input to the operational amplifier 11 0.

The voltage threshold at which the transistor 1 22 is turned on is determined by the base voltage of the transistor which is pegged at 3.1 0 volts in the illustrated embodiment. In order for the transistor to turn on, the voltage at terminal 11 6 must be at least the base voltage plus the voltage drop from the emitter to the base and the votage drop across diode 120.

A pair of 1 N473 1 Zener diodes 142 and 144 are arranged in opposite polarity series arrangement between terminal 11 6 and ground for limiting the maximum voltage at terminal 11 6.

It may be appreciated that, when the voltage at the analog input 100 decreases, the AGC operates to increase the output at terminal 116. A 9.1 K resistor 107 connected between the noninverting input to operational amplifier 110 and ground serves to provide a lower limit to the input voltage and thus limit the amount of amplification that is produced by the operational amplifier.

The output at terminal 11 6 is supplied to the band-pass filter 12. As noted above in connection with Figure 1, the output of the band pass filter is supplied to five phase shifters 14, of identical construction except for capacitor values. One phase shifter will now be described in detail. The phase shifter comprises a 4558 operational amplifier 1 50 whose non-inverting input is connected to the output of the band pass filter via a capacitor 1 52 of capacitance C, determined in accordance with a table set forth below. The inverting input to operational amplifier 1 50 is coupled across a 100 K resistor 1 54 to the output of the band pass filter.

A 50 K resistor 1 56 is connected between the non-inverting input of the operational amplifier 1 50 and ground to peg the maximum resistance to ground. The output of the operational amplifier 1 50 is fed back to the inverting input thereof via a parallel combination of a 100 K resistor 1 58 and a capacitor 1 60 also of capacitance C.

The values of C for the capacitors in each of the five phase shifters are selected to be as follows Phase shifter Capacitance C 14 a 0.03 microfarad 14b 0.012 microfarad 14 c 0.006 microfarad 14 d 0.0033 microfarad 14 0.001 microfarad As noted above in connection with Figure 1, the outputs of the frequency dependent phase shifter 1 5 are supplied to respective peak detectors 1 6. An additional peak detector 18 receives a non phase shifted output from the band pass filter. Peak detectors 1 6 and 1 8 are identical and for the sake of conciseness only one of the peak detectors will now be described in detail.

Peak detector 1 6 may be divided into two separate operating portions, one including operational amplifiers 1 70 and 1 80 for detecting the positive peak and the other including operational amplifiers 1 90 and 200 for detecting the negative peak. The output of a phase shifter 14 or, in case of peak detector 18, the output of the band pass filter, is supplied in parallel to the respective non-inverting inputs of operational amplifiers 1 70 and 190.

Operational amplifiers 1 70, 1 80, 1 90 and 200 may all be embodied in a 4136 chip. Operational amplifier 1 70 is provided with negative feed back via a 1 N9 14 diode 1 72 and the inverting input thereof is connected via a 10 K resistor 1 78 to the inverting input of operational amplifier 1 80 and to the output thereof.The output of operational amplifier 1 70 is connected to the non-inverting input of operational amplifier 1 80 via a 1 N914 diode 182 and via a 1 K resistor 1 84. The junction between diode 182 and resistor 1 84 is coupled to a parallel combination of an analog switch 185, such as a 4053 type, a 0.47 mf capacitor 1 86 and a 500 K resistor 1 87 to ground.

Operation of the "positive" portion of the peak detector will now be briefly summarized. As the voltage at the non-inverting input to operational amplifier 1 70 increases, so too does the voltage at the non-inverting and inverting inputs and output of operational amplifier 180, causing charging of capacitor 186: When the voltage level at the non-inverting input to operational amplifier 1 70 decreases, diode 1 82 prevents a current flow from the non-inverting input of operational amplifier 180 to operational amplifier 170 and the voltage at operational amplifier 180 remains at its positive peak level due to the charging of capacitor 186.

The "positive" portion of the peak detector is reset at the end of each cycle of the pitch frequency by a control signal from the CPU 44 which closes analog switch 185, thereby discharging capacitor 1 86.

The "negative" portion of the peak detector is identical to the positive portion described above except for diode polarities. Operation thereof also is identical but for negative voltages. Operational amplifier 1 90 is provided with negative feedback via a 1 N9 14 diode 192. The inverting input to operational amplifier 1 90 is coupled via a 10 K resistor 1 94 to the output and inverting input of operational amplifier 200. The output of operational amplifier 1 90 is coupled via a 1 N9 14 diode 204 and a 1 K resistor 207 to the noninverting input of operational amplifier 200. The junction of resistor 207 and diode 204 is coupled across a parallel combination of a 4053 analog switch 209, a 0.47 mf capacitor 210 and a 500 K ohm resistor 212 to ground.

The outputs of respective operational amplifier 1 80 and 200 are connected via respective 5 K resistors 222 and 224 to a common output terminal 225 which is coupled to an input of multiplexer 40 (Figure 1). The voltage at terminal 225 is the difference between the peak negative and peak positive voltages measured during each cycle of the pitch frequency of the voice signal.

Multiplexer 40 and the associated circuitry is illustrated schematically in Figure 3. The A B and C control inputs of multiplexer 40 are supplied from the QO, Q,, and Q2 outputs of a 74161 counter 230 which counts up to six. Counter 230 receives a clock pulse input from the PC 6 terminal at pin 25 to the SDK 8- card containing the CPU 44, and also receives a reset pulse from the Q output of a 74LS74 flip flop 232 which receives an oscillator input from an external oscillator (not shown) which provides a pulsed signal at the expected pitch frequency, which is predetermined, and is typically between 120 and 200 Hz.

Each time that the oscillator input, which is typically a pulse wave, goes positive, flip flop 232 provides a Q output to the PC 3 terminal of the SDK 80 card at pin 22. When the Q output is high, also expressed by a flag 1 being up, clock pulses are supplied from terminal PC 6 to the clock input of counter 230, operating the counter and causing the multiplexer to operate. The first of the clock pulses supplied from terminal PC 6 is supplied to flip flop 232 via an inverter and immediately resets the flip flop to Q.

A total of seven pulses are provided by terminal PC 6 during each cycle. The first six of these operate the multiplexer and the seventh is supplied to an AND gate 234 together with the TC output of counter 230. The output of AND gate 235 is supplied via an inverter 236 to the analog switches 1 85 and 209 of the peak detectors for resetting thereof at the end of each cycle.

The output of the multiplexer 40 is supplied via a 4558 buffer 250 to an analog input of a A-D converter 42, typically an ADC-60-10. The eight bit output of the A-D converter is supplied to terminals PB O--PB 7 of the SDK 80 card.

Delay 50 receives the analog received signal via a preamplifier 258 comprising a 741 operational amplifier 260 having negative feedback via a variable resistor 262 and receiving the received signal from the SSB receiver via a 5 K resistor 261. Delay 50 is a modular delay line comprising typically five identical delay circuits connected in series in order to provide an additive delay. Each of the delay modules 26 comprises a SAD 1024 chip which is a Charge Coupled Device, CCD, manufactured by Reticon, and indicated by a reference numeral 270. The SAD 1024 is operated by clock pulses supplied from a two phase clock such as a 4013 chip 268 which in turn receives a clock input.

The input of the SAD 1024 chip from preamplifier 258 is supplied via a capacitor 264 and is coupled across a potentiometer 268 to a source of +15 V in order to provide a desired DC level at the input of the SAD 1 024. The two outputs of the SAD 1024 are supplied to summing circuitry. A 1 K resistor 280 regulates the load at the output of the SAD 1024. The output of the summing circuitry is supplied to the next module for further delay and the output of the last module is supplied as a signal input to an analog multiplexer 280, such as a 4053 type.

Analog multiplexer 280 receives an enable input from hangover circuitry 46.

When a decision pulse indicating voice detection is supplied by the CPU 44 at a terminal PC 7 identified by reference numeral 300, the hangover circuitry is operative upon termination of the decision pulse, indicating that voice is no longer detected, to maintain switch 48 closed for an additional period of time which is predetermined.

The input at terminal 300 is supplied to differentiator circuitry 310 which indicates when the decision pulse terminates and comprises a parallel combination of inverters 31 2 and 314.

The output of inverter 312 is supplied to an input of a NANO gate 31 6 while the output of inverter 314 is supplied via a second inverter 31 8 to a second input of AND gate 31 6 and via a capacitor 320 to ground.

The input at terminal 300 is also coupled to an inverter 322 whose output is supplied across an 0.005 microfarad capacitor 203 to ground and is also supplied as an input to a NAND gate 324 which also receives an input directly from terminal 300. Inverter 322 and NAND gate 324 together define circuitry 330 which detects the beginning of a voice detection signal at terminal 300.

The outputs of NAND gates 316 and 324 are supplied to an input 2 of a 555 monostable multivibrator 340 which also receives a timing signal from timing circuitry 342. The output of monostable multivibrator 340 is supplied across an inverter 341 to a NOR gate 346. The output of NOR gate 346 is supplied to a B input of analog multiplexer 280. NOR gate 340 provides an input to the analog multiplexer whenever a voice detect signal is present at terminal 300 or when the voice detect signal terminated not earlier than the hangover time. A light emitting diode 350 is connected to the B input of the multiplexer 280 to indicate when voice signals are being transmitted by multiplexer 280 which embodies switch 48.

In Figure 4 details of the zero crossing detection circuitry are shown. Means are provided for determining when the characteristic voltage vs. time curve of the incoming signal crosses the zero axis. More particularly, a comparator 51 is shown having its input connected through conductor 52 to the automatic gain control circuit 1 0. The non-inverting input of the comparator circuit 51 is connected to a voltage divider that leads from positive five volts through a 1 meg ohm resistor R51 and through a 1 5 K ohm resistor R52 to the ground. The junction point of resistors R51 and R52 is coupled to the noninverting input.

Feedback through 10 meg ohm resistor R53 couples the output of the comparator 51 to the junction of resistors R51 and R52. The values were selected to provide an output each time the characteristic wave form of the voltage vs. time graph crosses the time axis or is at zero voltage.

Means are provided for doubling and differentiating the output of comparator 51. More particularly the output of comparator 51 is coupled through the 270 ohm coupling resistor R54 to the negative input of a differentiating and doubler amplifier 53. The junction of inputs 54 and resistor R54 is coupled to ground through diode D51. The diode D51 couples negative signals directly to ground. Input 54 is also connected to the positive input of amplifier 53 through 100 ohm resistor R56. The junction of resistor R56 and the positive input of amplifier 53 is coupled to ground through a 68 manofarad doubling and differentiating capacitor C51.

The output of the differentiating and doubler circuit is a sharp pulse having double the amplitude of the input. Means are provided for counting the sharp pulses. The pulses are carried to one input 56 of a NAND gate 57. The other input to NAND gate 57 is the Q terminal of a 74LS123 mono-stable circuit 58. When the mono-stable 58 is not operated to provide the low, the pulses are delivered to the counters.

Means are provided for inhibiting the count to allow transferring the count to the latches and to reset the counters. More particularly, the B input of the mono-stable 58 is tied directly to positive 5 volts. The A input is tied to an XOR gate 59 which receives a signal at its negative terminal from the control processing unit in the form of a pulse series used for resetting the counters; in the preferred embodiment 10 millisecond pulses are used. The positive input of the gate 59 is grounded. The output of gate 59 goes to operate the mono-stable 58. Positive 5 volts is tied to terminal 15 of the mono-stable through an 8.2 K ohm reistor R57. The junction of R57 and terminal 1 5 is connected to terminal 14 of the mono-stable circuit 58 through a 22 manofarad capacitor C52.

Responsive to each downward going portion of the pulses, a low is supplied to input 60 of NAND gate 57 for a discrete time fixed by resistor R57 and capacitor C52 to inhibit gate 57. When there is no low in input 60, then responsive to the high on 56, the gate 57 is inhibited. The pulses from the differentiator and doubler are connected to a counter circuit made up of two 74LS93 four output counters 62, 63 thereby providing weight outputs, i.e. outputs 00, Q1, Q2, 03 for each of the two counters.

The outputs of the counters are tied into latching circuits 64, 66 made up of two 74LS1 75 latches. The latch circuits provide means for storing the count until it is read by the control processor unit. Thus the outputs of the latching circuits 64 and 66 are tied directly to zero crossing terminals 67 which are tied to the control processor unit.

The counters 62 and 63 are reset responsive to reset pulse signals which in the embodiment described occur every 10 milliseconds. The output of XOR gate 59 is supplied to NAND gate 68. As shown in Figure 4, the output of gate 59 passes through 470 ohm resistor R58 into one input of the NAND gate 68. The junction of resistor 58 and the input of NAND gate 68 is tied to ground through a 33 manofarad capacitor C3.

The resistor and capacitor determine the time of the delay between the inhibiting of zero crossing signal and the latch enabling signal.

The other input to the NAND gate 68 is tied to a high positive five volts. As the capacitor charges, 2 highs are provided to NAND gate 68.

Therefore, the output of NAND gate 68 is a low.

The output of NAND gate 68 is tied to the clock terminal of each of the latching networks 64 and 66. The output of NAND gate 68 is also supplied directly to one input of NAND gate 70. The other input to NAND gate 70 is tied to a high, or positive 5 volts. Thus, when capacitor C3 charges, there is a high going pulse that operates the latching circuits 64 and 66.

Similarly, the reset signal is delayed until after the counter is read into the latching circuits. Gate 71 is connected to the output of NAND gate 70 through a delay network including a 470 ohm resistor R59 tied directly into one of the inputs of gate 71. That input is tied to ground through a 6.8 manofarad capacitor C4. The other input to NAND gate 71 is tied directly to positive 5 volts. As the capacitor charges, the output of NAND gate 71 is the high going pulse shown at an input of monostable circuit 72.

The mono-stable circuit 72 is connected in the same manner as mono-stable circuit 58 except that the A input of circuit 72 is grounded and the B input receives the output of NAND gate 71. The output of the mono-stable 72 that is used is the Q or high output rather than the Q output. Thus a positive pulse is transferred from mono-stable 72 to reset counter circuits 62 and 63 after the delays inserted by the delay circuitry including gates 68 and 71. The resistor-capacitor combination determines the pulse width of the outputs.

The counters 62 and 63 count the number of crossovers occurring during a set period of time.

This number is set into the latches until read by the CPU. Thus, the zero crossing detector detects the number of times the characteristic curve crosses the zero axis for a given period of time.

The number of times that zero axis is crossed is used by the CPU to obtain a weighted value.

The reset pulse is delayed to enable the eight count and then the counters 62 and 63 are reset by mono-stable 72. The eight outputs of the latching circuitry are read by the CPU from terminal 67. The output of the zero crossing circuitry is digital and therefore, no analog to- digital conversion is required.

Figure 5 illustrates means for providing the measurement of the total energy of the first formant in the incoming signal. It is known from past research that speech signals have a different energy distribution than do noise signals.

Accordingly, circuitry is provided to measure the energy content of the amplitude vs. frequency characteristics of the incoming signals to detect the voice speech having most of its energy in the first formant.

More, particularly as shown in Figure 5, means are provided for obtaining the energy of the first formant divided by the energy of the receiver channel. As shown, the output of the band pass filter 13, which in the preferred embodiment extends over a band pass range of 300 Hz. is supplied via conductor 81 to full wave precision rectifying circuitry including a 20 K ohm resistor R61, conductor 82 to the inverting input of operational amplifier 83. The non-inverting input of the operational amplifier 83 is grounded.

The output of operational amplifier 83 is connected back to the inverting input through a negative going diode D21 and also through a possitive going diode D22, resistor R62 and conductor 82. The junction of the anode of diode D22 and resistor R62 are tied through a 10 K ohm resistor R63 to the inverting input of operational amplifier 84. The positive input of operational amplifier 84 is grounded. The output of operational amplifier 84 is coupled back to the inverting input of operational amplifier 84 through 20 K ohm feedback resistor R64.

Resistor R65 is connected between the conductor 81 and the inverting input of the amplifier 84. The amplifiers 83 and 84, the diodes D21 and D22, and the resistors R61-R65 for a conventional precision full-wave rectifier circuit whose output represents the sum total energy of the positive and negative portion of the first formant.

It should be noted that the circuit examines the energy content of the first formant because of the limitations of the band pass filter which extends between--300 Hz. and 900 Hz. It has been found that more accurate determination of speech signals can be made when-the first peak formant is examined in this range.

The output of amplifier 84 is negative signal and consequently it is directed through 20 K ohm resistor R66 to the inverting input of the inverting operational amplifier 86; The non-inverting input of amplifier 86 is tied to ground-through resistor R67..A 20 K ohm feedback resistor R68 ties the output of inverter amplifier 86 to the inverting input. The output therefore, of inverter and amplifier circuit 86 is the positive absolute. value of the first formant of the incorning.signal taken between 300 and 9.00 Hz.

Means are provided for integrating the output of an amplifier -86 and the-reby providing a. value representing the total energy the first peak. The operational a-mplifier, utilized in a preferred embodiment, is shown as a 4558 operational amplifier. The output-of amplifier 86 is coupled to the inverting input of amplfier 87 through R69 which is 100 K ohm resistor. The non-inverting input of integrator 87 is coupled to ground through resistor R7 1. The output of integrator 87 goes through an analog to digital converter to the CPU unit.

The feedback provides the integrating function, more particularly capacitor C61 connects the output of integrator 87 to the inverting input. As the capacitor charges and reaches full charge, it provides an analog value that is equivalent to the total energy under the first formant of the incoming signal when examined in the voltage vs.

frequency characteristic.

Means are provided for resetting the integrator.

This is shown as reset switch SW6l, used to short out the 1 microfarad capacitor C61 which provides the integrating function. Thus when a timing signal is provided from the CPU, switch SW61 is closed, to discharge the capacitor C61 prior to the next examination of the first formant.

The circuitry described in conjunction with Figure 5 thus is used to examine the parameters and characteristics of the energy content of the first formant. These characteristics are unique to speech signals and can be used to distinguish speech from noise since speech has a different distribution of energy than does noise.

The examination of the parameters and characteristics of the energy content of the second formant of the characteristic frequency curve of the incoming signal is done the same way as the first as can be noted from the circuitry shown in Figure 6. In the preferred embodiment the second peak is examined at a frequency range of 1300 to 1 800 Hz. This is provided by any well known band pass filter.

Figure 7 shows the details of circuitry for measuring the total energy content of the first derivative of the first formant. As the incoming signal is received, points are periodically examined in the frequency band conforming to the first formant of speech, the differences determined and then the energy content of the first derivative is calculated.

In the process, an absolute value circuit, a difference circuit and. an integrator are used. More particularly, the output of band pass filter 13 is connected to the non-inverting input of a buffer amplifier 91. The non-inverting input of buffer amplifier 9-1 is also connected to ground through 13 K resistor R9 1. The output of the buffer amplifier 91 is connected to the inverting input of buffer amplifier 91.

The output of buffer amplifier 91 is also connected to a summing amplifier through 100 K ohm resistor R90. The resistor R92 is part of a voltage divider circuit that also includes 100 K ohm resistor R93 coupled between ground and the non-inverting input of the summing amplifier 93.

Further the output of the buffer amplifier 91 is coupled through switch means 94 to a sample and hold operational amplifier 96. The output of switch 94 is connected to the non-inverting input of the sample and hold amplifier 96. A 33 manofarad capacitor C91 is coupled between the non-inverting input and the ground to hold the signal that passes through switch 94.

The output of the sample and hold amplifier 96 is fed back to the inverting input through a 2 K ohm resistor R92 bridged by a 0.1 microfarad filtering capacitor C92. A further filtering capacitor C93 which has a 56 picofarad value is coupled between terminals 1 and 8 of amplifier 96.

The output of amplifier 96 is connected to the non-inverting input of summing amplifier 93 over a circuit that includes conductor 97 and 100 K ohm resistor R94. Conductor 97 is coupled to ground through a 2 K ohm resistor R95.

The output of summing amplifier 93 is fed back to the inverting input through 100 K resistor R96.

Thus, when switching means 94 closes, then the signal comes from the buffer amplifier to the sample and hold amplifier where it is held. The output of the hold amplifier 96 is fed to the inverting input of the summing amplifier along with the original output of amplifier 91. Each time the switching means 94 is operated, a new sample is taken which is also sent to the summing means after going through the sample and hold amplifier. In the meantime, the output of the buffer amplifier 91 is continuously sent to the non-inverting inputs of the summing amplifier.

Therefore, the output of the summing amplifier comprises the absolute sum of the continuous output of the buffer amplifier along with the steps of the sampled outputs. The sum of the samples taken in this manner is the slope or differential of the curve.

The output of the summing amplifier 93 is coupled to a second switching means 98 through 470 ohm resistor R97. The output of switching means 98 is coupled directly to the non-inverting input of a second sample and hold amplifier 99 through conductor 101. Conductor 101 is tied to ground through a 3.3 manofarad hold capacitor C94 and also through a 10 megohm resistor R98.

The output of the second sample and hold amplifier 99 is tied directly to the inverting input of the amplifier. A 56 picofarad capacitor C96 is connected between terminal 1 and 8 of amplifier 99.

The output of the second sample and hold amplifier 99 comprises the output of the summing amplifier 93 taken at periodic predetermined time spans.

Means are provided for measuring predetermined times and operating the switch means according to those predetermined time periods. More particularly, two time period generators G1 and G2 are shown in Figure 7. The first time period generator or clock operates first switch means 94 and also initiates the operation of the second time period generator G2. The second time period generator operates the second switching means 98.

Generator G1 comprises the one-half of a 4528 integrated circuit. Terminal 4 is coupled to ground, terminals 3 and 1 6 are coupled to plus five volts directly. Terminal 2 is connected to plus 5 volts through a 4.7 K ohm resistor R101 and terminal 2 is connected to terminal 1 through a 4.7 manofarad capacitor C97.

Terminal 5 receives down going pulses generated by the output of the other half of the G1 circuit. The Q terminal 10 is connected directly to terminal 5 through conductor 100.

Terminal 5 is also connected to the junction of a 6.8 microfarad polarized capacitor C98 and a 100 K ohm resistor R102 through diode D101.

The capacitor C98 is connected between positive voltage and one side of resistor R102. The other side of resistor R102 is connected to ground. The Q output of 1 00A is connected to terminal 11.

Terminal 12 is connected to ground. The Q output is also connected to a generator G2 which also comprises a 4528 integrated circuit 120A, B.

Returning now to generator Gl the timing components comprise resistor R103 having 100 K ohm value and capacitor C99 having a 1.5 manofarad value. These components are connected in series between positive 5 volts and terminal 1 5. The junction of the capacitor and the resistors C99 and R103 are connected to terminal 14.

The Q output is coupled through a zener diode Z1 to the gate of an FET used to control switch means 94. The drain of the FET is connected to positive 5 volts through a 15K resistor R104. The source of the FET is connected directly to negative 5 volts and through a 15 K resistor R106 to the anode of zener diode Z1. Accordingly responsive to the 0 output of G 1 the FET is operated to conduct and a negative voltage is applied to switch means 94 through conductor 102.

The wave form is shown next to the conductor 1 02. The switch means is closed as per the wave form shown and the sampling time is 10 microseconds out of every 100 microseconds.

Similarly, switch means 98 is operated responsive to the output of generator G2.

Generator G2 also has a ten microsecond time period as indicated by the components R106 and C100 which are 4.7 K ohms and 4.7 manofarads respectively. The output of the unit 1 20A has a 70 second microsecond pulse width as controlled by components R107 and capacitor C101 which are 100 K ohm and 1.5 manofarads respectively.

The low output of G2 is connected through zener diode Z2 to the gate G of FET transistor Q102.

The low output is also connected through a 1 5 K ohm resistor R 108 to a negative 5 volts at the source of the transistor Q102. The drain of transistor 0102 is coupled through 15 K ohm resistor R109 to positive 5 volts. The negative voltage at the source is coupled to the drain responsive to the low output through the zener diode Z2. The negative voltage on the drain is coupled to operate switching means 98 through conductor 103 by the output wave form shown next to conductor 103. Switch means 98 is thus operated for 10 microseconds every 70 microseconds to sample and hold the output of summing amplifier 93.

The output of the sample and hold amplifier 99 is connected to absolute value circuit means shown as block 112 through conductor 113. The absolute value circuit is similar to that previously described and also includes a summing amplifier inverter and integrator which operate in the same manner as the previously described summing amplifier 84, inverter 86 and integrator 87. Thus, the total energy of the first derivative of the first formant is provided through the circuit, the analog to digital converter to the CPU where the digital number obtained is checked against a table in the CPU to provide a weighted number which is used to determine whether or not speech signals are present. Each of the parameters can be used alone without the other parameters in many instances to detect speech. However, a combination of parameters gives the most reliable results.

Figure 3/4 shows the connections to the multiplex circuit to provide access for the output of the first formant total energy determinating circuitry, second formant total energy determining circuitry and the energy of the first derivative of the first formant determining circuit. Thus, as shown the total energy P 1 of the first formant is fed into terminal 6 of Mux 1 and.the total energy P2 of the second formant is fed into terminal 7 of Mux 1 while an auxiliary Mux, Mux II, is used to receive the output of the total energy P3 of the first derivative of the first formant. These inputs are multiplexed through the buffer amplifier into the analog to digital conversion circuit.

The modified program for the SDK-ACPU is shown in the flow chart of Figure 8. The CPU memory instructions are as follows: The present invention is not limited to what has been specifically shown and described hereinabove. It is appreciated that the particular circuits, components and their values given are merely exemplary as is the program for the CPU and are presented in the interests of the fullest disclosure of an operative embodiment of the present invention. The scope of the present invention is defined only by the claims which follow.

Claims (29)

Claims

1. Squelch circuitry for use in receivers having high noise levels to squelch the incoming received signals in the absence of speech signals, comprising: squelch means; speech detecting means for detecting the speech signals among noise signals, the speech detecting means comprising parameter examining means for examining parameters of a plurality of speech characteristics to obtain values, means for using the values for determining whether speech is present in the incoming signals; and means responsive to the detection of speech for inhibiting the squelch circuitry to enable the passage of the incoming signals through the squelch means.

2. Squelch circuitry as claimed in claim 1, wherein the means for using the values comprises means for providing a probability number of each of the parameters examined based on the value obtained from the examination of the parameters, and means for adding the probability numbers and using the sum to determine the presence of speech.

3. Squelch circuitry as claimed in claim 2, wherein means are provided for changing the values based on the results of prior examinations of the parameters of speech characteristics in the incoming signals.

4. Squelch circuitry as claimed in any one of the preceding claims, wherein the parameter examining means includes means for examining the amplitude asymmetry of the incoming signals.

5. Squelch circuitry as claimed in any one of the preceding claims, wherein the parameter examining means includes means for examining the zero crossing points of the incoming signals.

6. Squelch circuitry as claimed in any one of the preceding claims, wherein the parameter examining means includes means for examining the total energy in the first formant of the frequency response characteristic of the incoming signals.

7. Squelch circuitry as claimed in any one of the preceding claims, wherein the parameter examining means includes means for examining the total energy in the second formant of the frequency response characteristic of the incoming signals.

8. Squelch circuitry as claimed in any one of the preceding claims, wherein the parameter examining means includes means for examining the total energy of the first derivative of the first formant of the frequency response characteristic of the incoming signals.

9. Squelch circuitry as claimed in claim 5, wherein the zero crossing examining means comprises: zero crossing detector means including a comparator for comparing the incoming signal at the output of an automatic gain control circuit to zero to determine when the zero axis is crossed; means for supplying a counting pulse to a counter for each crossing of the zero axis; and means responsive to the total of the counted pulses for providing a weighted number to be used in determining whether or not speech is present in the incoming signal.

10. Squelch circuitry as claimed in claim 6 or 7, wherein the means for examining the total energy in the first or second formant comprises, band pass filter means for obtaining the frequency of the first or second formant, absolute value circuit means for obtaining the absolute value of the form ant, and integrator means for obtaining the total energy in the examined formant.

11. Squelch circuitry as claimed in claim 8, wherein the means for examining the total energy of the first derivative of the first formant comprises band pass filter means for isolating the frequencies of the formant being examined, means for differentiating the amplitude value of the formant being examined at time periods, clock means for obtaining the time periods, absolute value circuit means for obtaining the absolute value of the differential of the amplitude, and integrating means for summing the absolute values of the differentiated values.

12. Squelch circuitry as claimed in claim 11, wherein the differentiating means comprises sampling means for obtaining the amplitude value of the frequency response characteristic in the band pass at fixed time periods, and means for taking the difference between the amplitude values to obtain the differential.

13. Squelch circuitry as claimed in claim 10, wherein the band pass filter has a pass-band which extends from 300 to 900 Hz.

14. Squelch circuitry as claimed in claim 10, wherein the band pass filter has a band-pass which extends from 1 300 to 1 800 Hz.

1 5. Squelch circuitry substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

1 6. A receiver including squelch circuitry as claimed in any one of the preceding claims.

17. Voice detection circuitry for operation in a high noise environment, comprising: at least one phase shifter arranged to phase shift a received signal by a selected amount, a plurality of peak detectors, each receiving an input signal which is a phase shifted by a different amount, selected from the received signal or the outputs of the at least one phase shifter, for sensing the positive and negative amplitude peaks of the respective input signal; and comparator circuitry for determining the difference between the positive and negative peaks of the peak detector inputs and for comparing the difference with a predetermined threshold to provide an output indication when the threshold is exceeded.

1 8. Voice detection circuitry as claimed in claim 17, wherein the at least one phase shifter comprises a frequency-dependent phase shifter.

19. Voice detection circuitry as claimed in claim 17 or 18, wherein the plurality of peak detectors and the comparator circuitry are arranged to examine a plurality of operating cycles for determining amplitude asymmetry therein, there being provided means for providing an output indication of voice detection when the threshold is exceeded a predetermined number of times during the plurality of operating cycles.

20. Circuitry as claimed in any of claims 1 7 to 19, further comprising: hangover circuitry for receiving the output indication from the comparator circuitry and for providing an output signal for the duration of the output indication and for an additional predetermined time; and a switch arranged to receive the output of the hangover circuitry as a control input and to connect the received signal to output circuitry in response to the received output of the hangover circuitry.

21. Circuitry as claimed in claim 20, further comprising delay means for delaying the received signal and providing an output to the switch.

22. Circuitry as claimed in any one of claims 17 to 21, wherein the plurality of peak detectors includes a peak detector arranged to receive a non-phase shifted input signal.

23. A method of operating squelching means to squelch incoming noise signals when speech is not present in radio receiver systems having high noise to speech signal levels and to enable passing of the incoming signals to sound transducers when speech is present, the method including the steps of: automatically controlling the gain of the incoming signal; delaying the incoming signals on a path that extends through the squelching means to the sound transducers; examining the incoming signals for parameters of speech characteristics to obtain numerical values for the parameters; using the numerical results to obtain probability numbers that are functions of the statistical probability that speech signals are present; summing the numbers obtained; using the sum to determine if speech signals are present; and operating the squelching means to squelch noise when speech signals are not present and to pass the signals when speech signals are present.

24. A method as claimed in claim 23, including the steps of changing the probability numbers based on prior examinations of the signal.

25. A method as claimed in claim 23 or 24, including the step of examining the incoming signals for a plurality of parameters of speech characteristics to obtain numerical values for each of the parameters.

26. A method as claimed in claim 25, including the steps of examining the incoming signal to determine the amplitude asymmetry of the incoming signals, the examination including the steps of: phase shifting the incoming signal buy a plurality of different amounts; sensing the positive and negative peaks of the phase shifted signals; determining the differences between the positive and negative peaks for each of the phase shifted signals; and obtaining the numerical value from the differences.

27. A method as claimed in claim 25 or 26 including the steps of examining the incoming signals to determine the number of zero crossings during a given time period, and obtaining the numerical value from the number of zero crossings.

28. A method as claimed in any of claims 25 to 27, including the steps of: examining the incoming signal to determine the energy contents of the signal formants; filtering the incoming signal to select desired formants; converting the filtered signal to the absolute values of the formants; integrating the absolute values to obtain the total energy; and obtaining a number equivalent to the absolute values.

29. A method as claimed in any one of claims 25 to 28, including the steps of: filtering the incoming signals to select a desired formant; finding the absolute value of the first derivative; integrating the absolute value of the first derivative to find the total energy of the first derivative of the desired formant of the incoming signals; and converting the total energy to a number.