GB2100029A - Multi-channel time-switched controller - Google Patents

Abstract

A controller is provided for controlling, on a time basis, the switching ON and OFF of a number of a energy- utiliser channels (C1 to C8). The controller stores a number of control programs in respective program memories (31 to 34). The controller is so arranged that one control program is set to control the energy-utiliser channels (C1 to C8) during each 24-hour period, the pattern of program utilisation for successive 24-hour periods being predetermined. The controller divides each 24-hour period into m time slots during each of which the required state of the energy- utiliser channels (C1 to C8) is determined by a corresponding control data word of the selected control program. A real time clock (25) is used to control the output, from the appropriate memory (31 to 34), of the data word corresponding to each successive time slot during a 24-hour period. <IMAGE>

Description

SPECIFICATION Multi-channel time-switched controller The present invention relates to a multi-channel time-switched controller for controlling, on a time basis, the switching ON and OFF of a number of energy utilisers in a domestic, commercial or industrial environment.

According to one aspect of the present invention, there is provided a controller comprising n output channels for independently controlling a corresponding number of energy utilisers, a plurality of program memories each with m addressable locations, each said location being arranged to store a respective n-bit channel-state data word in which each bit represents a required state of a corresponding one of the output channels, memory enabling means arranged to selectively enable said program memories such that only one memory is enabled at any one time, clock means operative to time successive 24-hour periods and to divide each such period into m time slots during each of which the clock means addresses a respective one of them memory locations of the enabled program memory, and output control means arranged to set the state of each output channel in dependence on the state of the corresponding bit of the data word stored in the currently addressed location of the enabled memory, said memory enabling means including a day count unit for counting successive said 24-hour periods, memory means for storing for each day count holdable by said day count unit, the identity of the program memory the channel-state data of which it is desired to implement during the 24-hour period represented by said day count, and means arranged to enable the program memory indicated by the stored memory-identity corresponding to the current day count.

In this manner, the controller implements for each 24-hour period the control program made up of the data words stored in the program memory enabled for that day, the enabled program memory being set in a predetermined manner by the current day count.

Preferably, the day count unit counts up from 1 to 7 and then starts again so that the day count can be equated to the days of the week (for example, day count one equates to Monday). The controller thus operates on a seven day cycle in which it implements certain programs on certain days and then repeats this pattern of programs for successive weeks.

Preferably m is equal to 288 so that each time slot is of five minutes duration which gives sufficient control resolution for most applications.

To facilitate reprogramming of the controller both in terms of the data words in the program memories and of the program memory required to be enabled on a particular day, both the program memories and the the said memory means are advantageously formed by RAM memory chips. Furthermore, the clock means are preferably controllable to run fast so as to enable successive memory locations to be addressed during programming, for the purpose of writing data therein, in a time span much less than real time.

Programming of the program memories can be additionally facilitated by the provision of an autoselect unit which when the controller is to be programmed, is arranged to enable each program memory in turn during successive 24-hour cycles run through by the clock, regardless of the identity of the memory which according to the said memory means, should be enabled.

The controller can further be provided with a holiday control circuit by means of which the normal program utilisation pattern can be over-riden for a number of days as set into the controller by the user.

During the over-ride period, a particular one of the program memories is enabled continuously to the exclusion of the other memories; the enabled memory may, for example, contain a frost protection program which it is desired to run throughout a holiday period. At the end of the holiday period, the controller is arranged to revert to its normal operation as if it had been following through the set program utilisation pattern during the holiday days.

A multi-channel time-switched controller embodying the invention will now be particularly described, by way of example with reference to the accompanying drawings, in which Figure 1 diagrammatically illustrates the connection of the controller to pieces of equipment to be controlled; Figure 2 is a functional block diagram of the controller; Figure 3 is a functional block diagram showing the operative configuration of the controller when in a RUN mode; Figure 4 is a functional block diagram showing the operative configuration of the controller when in a 'PROGRAM SET-IN' mode; Figure 5 is a block diagram of a 'Holiday Control' circuit of the controller; and Figure 6 is a block diagram of one channel of an output control unit of the controller.

The controller 10 shown in Figure 1 is arranged to control the ON/OFF state of eight output channels C1 to C8 throughout successive control cycles each of seven consecutive 24-hour periods (days), the channels being controlled during each of the seven days in accordance with a program preselected for that day from four possible programs P1 to P4 stored in the controller 10. Thus, for example, the controller 10 can be set to control the channels C1 to C8 in accordance with program P1 during day one of its seven-day cycle period, in accordance with program P2 during days two, three and four, in accordance with program P3 during day five, and in accordance with program P4 during days six and seven; thereafter, the controller 10 starts at day one again and effects control in accordance with program P1.

Each program P1 to P4 defines for each fiveminute time slot throughout a day the ON/OFF state required for each channel C1 to C8; for example, during one five-minute time slot channels Cl, C2, and C6 may be progammed to be ON with the remaining channels OFF while during the next time slot channel C2 may be turned OFF and channels C5 and C8 turned ON giving channels C1, C5, C6 and C8 ON and channels C2, C3, C4 and C7 OFF.

Each channel C1 to C8 is arranged to control a respective piece of equipment 11 (for example, a lighting circuit, power circuit, central heating boiler, etc.) via an appropriate auxiliary control unit 12, such as an a.c. contactor, which will normally be located remote from the controller 10 and near the associated piece of equipment 11.

The controller 10 normally operates in a 'RUN' mode in which if effects control over the channels C1 to C8 in the manner outlined above, the state of each channel being indicated by respective pairs of first and second indicator lights 13 and 43 at least one of which is arranged to light when the associated channel is ON.

In the RUN mode, the actual time of day is displayed on a time display 14(which can be set as required by operation of fast and slow advance buttons F and S1 ) while the number of the current day in the seven-day cycle of the controller is displayed on an auxiliary display 15 settable as required by operation of an advance push button D.

The program currently being used to control the channels C1 to C8 is indicated by the illuminated one of a set offour indicator lights 9. The controller 10 can also be set into two programming modes, namely a 'PROGRAM SET-IN' mode and a 'PROG RAM SELECT' mode by appropriate setting of switches 16 and 17 respectively (these switches 16 and 17 are two-state push buttons each settable in either a 'run' position of a 'programming' position in the latter of which an associated indicator light 18 and 19 respectively is arranged to light up).When the controller is in a 'PROGRAM SET-IN' mode, each of the programs P1 to P4 can be written or rewritten into the program memory of the controller using two-state channel push button switches CB1 to CB8 to indicate the required state of the corresponding channels for each of the 288 five-minute time slots of the 24 hour period covered by a program, the time slot being programmed being put up on the time display 14 in place of the actual time and being advanced as required by operation of the buttons F and S1. When the controller 10 is in a 'PROGRAM SELECT' mode the program P1-P4 required for each day of the seven-day control cycle can be set into a selected-program memory of the controller using program select push buttons PB1 to PB4, the number of the day for which a program is to be selected being displayed on display 15 in place of the current day number.

The controller 10 can also be set to operate in a 'HOLIDAY' mode in which it controls the channels C1 to C8 in accordance with program P4 for every day of a holiday period of a duration of one to ninety-nine days as set in on push button H.

A more detailed description of the controller will now be given with reference to Figure 2.

As indicated by the dashed lines in Figure 2, the controller can be notionally divided up into four main sections, respectively a timing section 1 for keeping track of the passage of real time and for providing a program time for use during setting in of the programs P1 to P4, a program memory section II for storing the programs P1 to P4, a selectedprogram memory section III for storing the identity of the particular program selected for each day of the seven days making up the control cycle, and an auxiliary display and control section IV ensuring proper operation of the controller 10.

The timing section I The timing section I comprises a timing pulse generator 20 built around a crystal oscillator and arranged to output pulses at 100 Hz, 50 Hz, and 1 Hz to a gating circuit 24. This circuit 24 controls the supply of pulses to a real time clock 25 and a program clock 26 in dependence on signals from the fast and slow advance buttons F and S1 and on signals R and P which are respectively generated when the switch 16 is in its 'run' position and in its 'programming' position. When the switch 16 is in its 'run' position, the signal R sets the program clock 26 to zero and controls the circuit 24 to pass clocking pulses to the real time clock 25; unless one of the buttons F and S1 is pressed, the pulses supplied to the clock 25 will be the 1 Hz pulse from the pulse generator 20.The real-time clock 25 counts these 1 Hz pulses and provides a minute by minute indication of the time in hours and minutes, this indication being in the form of BCD signals output on a real-time bus 27. These BCD time signals pass via a multiplexer 28, appropriately set by the signal R, and a bus 29 to the display 14to give a visual indication of the currenttime of day.

In order to set the real time clock to the correct time, one or other of the advance buttons F and S1 can be pressed to feed pulses at 100 Hz and 50 Hz respectively to the real-time clock 25 instead of the 1 Hz pulses.

As will be more fully described hereinafter, the BCD time signals on the bus 29, as well as being fed to the display 14, also serve as memory address signals for the program memory section II; however, since the channel-state data held in each program memory location relates to a respective five-minute time slot rather than to a one-minute time slot, before the BCD time signals on bus 29 are fed to program memory section II, the 'units' minute signals are reduced in a circuit 30 to a signal indicative of whether the time is currently within the first or second five minute period of each ten minutes indicated by the 'tens' minute signals.

When the switch 16 is in its 'programming' position, the signal R is removed from the program clock 26 allowing it to start while the signal P causes the circuit 24 to supply the clock 26 either with 1 Hz pulses or, if one of the advance buttons F and S1 is pressed, with 100 or 50 Hz pulses. Like the real-time clock 25, the program clock 26 is arranged to provide BCD time signals in hours and minutes except that the program clock 26 only indicates minute changes in steps of five minute periods. The BCD time signals from the clock 26 are output on a bus 21 to the multiplexer 28 which is set by the signal P to allow these BCD time signals to pass onto the bus 29 in preference to the signals on the bus 27. As before, the signals on the bus 29 are both fed to the display 14 (which now displays 'program' time in hours and minutes with changes in five minute steps) and serve as address signals for the program memory section II, the circuit 30 now having no effect since the signals in the bus 29 are already as required.

While the switch 16 is in its 'programming' position, the real-time clock 25 is kept running, being continuously fed with 1 Hz pulses regardless of whether one of the advance buttons F and S1 is pressed.

Both the real-time and program clocks 25 and 26 are arranged to output 'day' signals RD and PD respectively upon transition from 23 hrs. 59 mins. to O0hrs. 00 mins.

The program memory section lI The program memory section II comprises four program memories 31 to 34 each arranged to store a respective one of the programs P1 to P4. At any one time, only one of these memories 31 to 32 will be enabled, this enabling being effected by signals supplied over a four-line enable bus 35.

Each program memory 31 to 34 has 288 addressable locations each arranged to store a channel-state data word of n bits where n is the number of channels to be controlled (in present example, n = 8). The data input/output lines of the memories 31 to 34 are connected to a common data bus 36 which is connected both to an output control unit 37 and to a switch control unit 38 including the channel push button switches CB1 to CB8. These switches control the connection of respective lines of the data bus 36 to corresponding lines of a data bus 41 which extends from the unit 38 to the unit 37.The signals on the lines of the bus 36 control the energisation of corresponding ones of the first indicator lights 13 whereas the signals on the lines of the bus 41 control the energisation of corresponding ones of the second indicator lights 43; the signals on the bus 41 are also used to control the output states of the channels C1 to C8.

The read/write condition of the memories 31 to 34 is set by the signal on a read/write control line R/W, the memories being in a 'read' condition except when the switch 16 is in its 'programming' position and the write button W is simultaneously depressed.

The address lines of the memories 31 to 34 are connected to a common address bus 39 which is connected to receive the BCD time signals from the circuit 30; these signals are utilised as address signals with each of the 288 different possible signal combinations (one for every five-minute time slot throughout a 24-hour period) serving to address a respective one of the 288 addressable locations in each memory 31 to 34. Thus, as time signals on the bus 29 change through a 24-hour cycle, each one of the 288 locations in the enabled memory 31-34 will be addressed in turn resulting in the appearance on the data bus 36 of the channel-state data word appropriate for the five-minute time period running at that time as set by the real time clock 25 (if the switch 16 is in its 'run' position) or the program clock 26 (if the switch 16 is in its 'programming' position).

When the memories 31 to 34 are in their 'read' condition and the switches CB1 to CB8 are set in a state interconnecting the buses 36 and 41, the channel-state data word put on the bus 36 by the enabled memory 31 to 34 is fed to the output control unit 37 both via the bus 36 and the bus 43; this data word is used to effect energisation of the first and second indicator lights 13 and 43 of the channels which according to the data word should be ON in the current five-minute time slot.If at the same time the switch 16 is in its 'run' position, (that is, the controller is in its 'RUN' mode) the signal R fed to the unit 37 enables each of the channels C1 to C8 to be set in a state corresponding to that indicated by the corresponding bit of the data word on the bus 41; however, if the switch 16 is in its 'programming' position, then the channels C1 to C8 are kept in an OFF state regardless of the contents of the data word on bus 41.

During the 'RUN' mode of controller operation, the channel push button switches CB1 to CB8 can be used to override the output of the program memories to put a channel in an ON state when it would otherwise be OFF. This is achieved by arranging for each switch CB1 to CB8 to be operable to both disconnect the two corresponding lines of the buses 36 and 41 and simultaneously cause an 'ON' state signal to be set on the line of the bus 41; as a result, the channel associated with that line will be set 'ON' and the corresponding second indicator light will be continuously energised, regardless of the state of the corresponding data-word bit output from the enabled memory 31 to 34 (the state of this bit still being indicated by the corresponding first indicator light).The setting of an 'ON' state signal on a line of the bus 41 disconnected from the corresponding line of the bus 36, can most easily be achieved in practice by permanently applying a bias to the line via a resistor, this bias corresponding to an ON state signal and being capable of being overriden by an OFF state signal fed to the line from the bus 36 via the appropriate switch CB1 to CB8. A channel set ON by use of its corresponding switch will remain ON until the switch is released.

To program the memories 31 to 34, the switch 16 is put in its 'programming' position setting the controller into its 'PROGRAM SET-IN' mode. The channel push button switches CB1 to CB8 are then set to represent the required channel states for the time slot under consideration (indicated on the time display 14), these states being thereafter written into the memory enabled via the enable bus 35, by depression of the write button Wto produce a write enable signal which passes via a gate 44 (enabled by the signal P) and the line R/W to the write enable inputs of the memories 31 to 34.In the present example, the switches CB1 to CB8 are arranged to fulfill both their memory programming function and their previously-described output override function by arranging for each line of the bus 36 either to be supplied with a logic '1' or '0' bias in dependence on the state of the corresponding switch, these biases being such as to be overriden by the output from the enabled memory when in a 'read' condition but serving to represent the required channel state when the memory is in a write condition. One of these biases is the bias previously described as applied to the bus 41. Various other arrangements are, of course, possible for writing into the memories.

The selected-program memory section III The selected-program memory section III comprises a selected-program memory 50 for storing for each day of the seven-day control cycle, the identity of the particular one of the programs P1 to P4 required for that day. The memory 50 thus has seven addressable locations the addresses of which correspond to respective ones of the seven possible outputs of a real-time day count unit 51 of the section IV. In accordance with the current reai-time day as indicated by signals on the output bus 52 of the unit 50, the memory 50 outputs identifying signals on a bus 53 to identify the program P1 to P4 required forthat day. As will be more fully explained hereinafter, these identifying signals serve during the 'run' mode of controller operation to enale the memory 31 to 34 storing the required program.The program represented by the output signals of the memory 50 is externally indicated by means of the indicator lights 9. Preferably each location of the memory 50 is arranged to store a four-bit word in which only one bit is set, the position of the bit in the word indicating the required one of the programs P1 to P4; the output signals of the memory 50 can then be used without decoding to enable the appropriate program memory and energise the appropriate light 9.

To write the identity of the program required for a particular day into the memory 50, the controller is set into its PROGRAM SELECT mode by putting the switch 17 in its 'programming' position. The appropriate one of the program push buttons PB1 to PB4 is then pressed; simultaneously the write button W is depressed to produce a write enable signal which passes via a gate 54 (enabled by a signal S generated by the switch 17 when in its 'programming' position) to a gate 55 and to the write enable input of the memory 50. Upon receipt of thins enabling signal,the gate 55 allows the outputs of the push buttons PB1 to PB4 to pass onto the bus 53 and be written into the memory 50.

The auxiliary displayand control section IV This section comprises circuitry for controlling the auxiliary display 15 and the signals supplied to the enable bus 35 of the program memory section II.

As already mentioned, section IV includes the day count unit 51. This unit 51 counts real time days as indicated by the signal RD from the real time clock 25, the unit 51 being arranged to count up to seven before restarting whereby to enable the controller to keep track of where it should be, in real-time terms, in its seven day control cycle. The count held by the unit 51 can be advanced as required by operation of the push button D. Signals representing the current day count of the unit 51 are fed via the bus 52 to a multiplexer 60 which, when the controller is in its RUN mode, allows the day count signals to pass via a bus 62 and a second multiplexer 61 to the display 15; as a result the current day count is displayed on the display 15.The multiplexer 61 only prevents passage of signals on the bus 62 during functioning of the holiday control circuit 63 which will be described hereinafter.

As previously mentioned, the current day count signals are also fed to the selected-program memory 50 as address signals. The program-identifying signals output by the memory 50 pass via the bus 53 to a further multiplexer 64 of the section IV; during the RUN mode of controller operation, the multiplexer allows the signals from the bus 53 to pass, via the multiplexer output bus 65 and a circuit 66, to the enable bus 35. The circuit 66 is an override circuit which only operates during functioning of the holiday control circuit 63.

The auxiliary display and control section IV further includes a program auto-select unit 67 which basically comprises a counter arranged to count up to four before starting again. During operation of the controller in its RUN mode, the counter of the unit 67 is in a reset state; however, upon operation of the switch 16to place the controller in its PROGRAM SET-IN mode, this counter is enabled and counts the program day signals PD produced by the program clock 26. The count held by the unit 67 is output via a bus 68 to both the multiplexer 60 and the multiplexer 61, these latter now being set by the signal P to pass the count on the bus 68 in preference to the signals on the buses 52 and 53 respectively. The count held in the unit 67 is thus fed both to display 15 where it is displayed and to the enable bus 35 of the program memory section II.By this arrangement, each of the program memories 31 to 34 is enabled in turn as the program clock is taken through four successive days.

The operation of the controller 10 in its RUN, PROGRAM SET-IN, and SELECT PROGRAM modes will now be described.

RUN mode The functional configuration of the controller 10 in its RUN mode is shown in Figure 3.

The actual time is displayed in the display 14 and the real-time clock supplies addresses corresponding to successive five-minute time slots to the program memories 31 to 34. The day count held in the unit S1 is both displayed on the display 15 and fed as an address to the selected program memory 50. In dependence on the day count, the memory 50 outputs program identifying signals identifying the required program, these signals being used to enable the appropriate one of the program memories 31 to 34. The enabled memory outputs the channel-state data word appropriate to the current five-minute time slot. With the push button switches CB1 to CB8 closed to interconnect the buses 36 and 41, the channels C1 to C8 are set in accordance with the output data word, the channel states being indicated by the lights 13 and 43. In the manner previously described, switches CB1 to CB8 can be used to set any one of the channels C1 to C8 in an ON state independently of the output of the enabled program memory. The push buttons F, S1 and Dare operable to advance the real time clock and the day count as already described.

PROGRAM SET-IN mode The functional configuration of the controller 10 in its PROGRAM SET-IN mode is shown in Figure 4.

The real time clock 25 is kept running but has no controlling function. The program clock is set running and is displayed on the display 14; the time signals output by the program clock 26 are also fed to the program memories 31 to 34 as address signals. The program auto-select unit 67 is set to count the program day signals PD and counts round from 1 to 4, the current count of the unit 67 serving to enable a corresponding one of the memories 31 to 34.

The channels C1 to C8 are inhibited though the would-be states of these channels are indicated by the lights 43.

Upon entry into the PROGRAM SET-IN mode, the program clock 26 is at 00 hers.00 mins and the unit 67 holds a count of one, thereby enabling program memory 31. The push button switches CBl to CB8 are set to represent the required state of the channel outputs in program P1 for the period 00 hr. 00 mins.

to 00 hr. 05 mins. The write button W is then pressed to write this channel-state data into the enabled memory 31. The program clock 26 is then advanced (using the button F or S1) to the next five-minute time slot and the switches CBl to CB8 reset as desired; the write button is again pressed. Programming of the memory 31 continues in this manner until all 288 five-minute time slots of program P1 have been programmed as required; where a number of successive time slots have the same channel states, the programming process can be rapidly carried out by holding down the write button W while advancing the program clock 26 through the relevant time slots.

After the program clock 26 has run through one 24-hour period, it will emit a signal PD which advances the count in unit 67 to two, thereby enabling program memory 32. Channel-state data can now be written into this memory as the clock 26 is advanced through the next 24-hour period. Similarly, the program memories 33 and 34 are programmed in the third and fourth 24-hr. periods run through by the program clock.

SELECT PROGRAM mode In this mode of operation, the identity of the program required for each day of the seven-day control cycle is set into the memory 50. To this end, the switch 17 is put in its 'programming' position.

The functional configuration of the controller in this mode is similar to that in the RUN mode except that the push buttons PB1 to PB4 and Wand the gates 54 and 55 are now functional. As in the RUN mode, the day count held in the unit 51 is displayed on the display 15 and is fed as an address signal to the memory 50. To set the identity of a particular program P1 to P4 into the memory location of the memory 50 corresponding to a particular day, the day count is advanced to the required day using the push button D. Thereafter the push button PB1 to PB4 corresponding to the desired program is pressed simultaneously with depression of the write button W; the identity of the desired program is now stored in the memory 50 and is also indicated by the lights 9.

Holiday control circuit The purpose of the holiday control circuit is to enable the normal running operation of the controllerto be overriden for the duration of a holiday period during which time one preselected program, for example, program P4 is continuously run. At the end of the holiday period, the controller reverts to normal run operation as if it had been doing so throughout the holiday period.

The holiday control circuit 63 is shown in detail in Figure 5 and comprises: a holiday-duration store 70 into which the length of a holiday in days can be fed by depression of a push button H an appropriate number of times; a holiday day counter 71 for counting the days elapsed of the holiday; and a comparator 72 arranged to compare the count held in the store 70 with the count of the counter 71. The comparator 72 has two outputs E and E and is arranged to produce a signal at the output E when the compared counts are equal and at output E when the compared counts are unequal.

When the holiday control circuit 63 is not being used, both the store 70 and the counter 71 will hold zero counts, having been reset over line 73. In this condition, the comparator 72 produces an output signal at its output E; this signal serves to set the multiplexer 61 in a state in which signals on bus 62 are fed to the display 15.

The holiday control circuit 63 further comprises a J-K flip flop 75 which is normally in a first state in which no output signal is produced at its output Q.

This output Q is connected both to an indicator light 76 for indicating the operative state of the circuit 63, and to the circuit 66 which when activated by a signal from the output Q, serves to override the signals fed onto the bus 65 from the multiplexer 64 and replace them with signals operative to enable a predetermined one of the program memories, for example, the memory 34. In the absence of a signal on the output Q of the flip flop 75, the circuit 66 is inactive and allows the free passage of signals along the bus 65.

The output E of the comparator 72 is connected to the enabling input of a gate 77 controlling the supply to the real-time day signal RD to the counter 71. The signal RD is also fed as a clock pulse to the flip flop 75 which has its two state-setting inputs connected to the outputs E and E respectively of the comparator 72; when the comparator 72 produces an output signal at its output E, each clock pulse RD fed to the flip flop 75 sets or reaffirms the flip flop in its first output state.

To use the holiday control circuit, the number of days of a pending holiday period are set into the store 70 using the button H on the day before the holiday commences. As soon as the count in the store 70 is incremented, the signal on the comparator output E disappears while a signal appears at the output E. This latter signal enables the gate 77 and also causes the count value in the store 70 to be fed via the multiplexer 61 to the display 15 which now indicates the number of holiday days set in. Since this setting in operation occurs the day before the holiday commences, the circuit 66 cannot be operated off the signal output from the comparator output E as it is not required to activate the circuit 66 until the following day.

The signal RD appearing right at the start of the first day of the holiday is fed via the enabled gate 77 to the counter 71; in addition, this signal RD causes the flip flop to change into its second state in accordance with the signal fed thereto from the comparator output E. A signal is now produced at the flip flop output Q which illuminates the light 76 to show that the holiday period has begun, and activates the override circuit 66 to enable the program memory 34 throughout the holiday period.

As the holiday period progresses, the counter 71 counts the pulses RD but no other change in the state of the circuit 63 occurs so that the override circuit 66 remains activated and the light 76 energised. Upon the count in the counter 71 becoming equal to that in the store 70, the comparator will change its output signal from output E to E thereby inhibiting the gate 77. The override circuit 66 will, however, remain activated throughout the succeeding 24-hour period until the next RD signal is received at the flip flop 75 to set the latter back into its first state and thus remove the signal from its output Q.

Sensor control of channels The output control unit 37 includes drivers 79 interposed between the lines of the bus 36 and the corresponding lights 13, and drivers 80 interposed between the lines of the bus 41 and the corresponding lights 43. Each line of the bus 41 is also fed to a respective AND gate 81 which is enabled by the signal R so that the channels C1 to C8 are only enabled during the RUN mode of controller operation as previously described.

The outputs of the gates 81 can be used directly as the outputs of the channels C1 to C8, or, as is indicated in Figure 6, can be fed to further gating circuitry enabling sensor control of the channels.

This further gating circuitry includes, for each channel, an AND gate 82 having two inputs connected respectively to the output of the gate 81 and to the output of a control sensor (not shown) associated with that channel. By virtue of its connection to gate 82, each control sensor exerts a controlling influence on the output state of the corresponding channel during periods when the signals supplied via the bus 41 would normally serve to set the channel in its ON state. Where the equipment controlled by the channel concerned is a central heating boiler, then the control sensor would typically be a room temperature thermostat, the thermostat serving to switch off the boiler during a normal run period when the room temperature exceeds a preset value.

The output of the gate 82 is, in the present example, connected to the channel output via an OR gate 83 which is also arranged to receive the output from an override sensor (not shown). In this manner, the channel can be set in an ON state solely in dependence on the state of the override sensor. In the previously mentioned example where the channel concerned controls a central heating boiler, the override sensor may be a thermostat set to bring the boiler into operation when there is a danger of frost damage.

For each channel, the provision of either or both of the sensors and the associated gates 82 and 83 is, of course, optional.

Various modifications to the described controller are, of course, possible. Thus, for example, the number of output channels can be varied with the data-word bit-length being correspondingly adjusted. The number of stored programs P1 to P4 can also be varied by providing an appropriate number of program memories. Furthermore, the controller's processing circuitry (that is, the elements within the outer dashed line in Figure 2) could be complemented by a suitably programmed microprocessor.

Claims (10)

1. A controller comprising: n output channels for independently controlling a corresponding number of energy utilisers, a plurality of program memories each with m addressable locations, each said location being arranged to store a respective n-bit channel-state data word in which each bit represents a required state of a corresponding one of the output channels, memory enabling means arranged to selectively enable said program memories such that only one memory is enabled at any one time, clock means operative to time successive 24-hour periods and to divide each such period into m time slots during each of which the clock means addresses a respective one of them memory locations of the enabled program memory, and output control means arranged to set the state of each output channel in dependence on the state of the corresponding bit of the data word stored in the currently addressed location of the enabled memory, said memory enabling means including a day count unit for counting successive said 24-hour periods, memory means for storing for each day count holdable by said day count unit, the identity of the program memory the channel-state data of which it is desired to implement during the 24-hour period represented by said day count, and means arranged to enable the program memory indicated by the stored memory-identity corresponding to the current day count.

2. A controller according to Claim 1, wherein the day count unit is arranged to count cyclically on a base of seven whereby the controller operates on a seven day cycle with the program memories being enabled during each seven day cycle according to the same sequence of memory identities stored in said memory means.

3. A controller according to Claim 1 or Claim 2, wherein m is equal to 288 whereby each said time slot is of five minutes duration.

4. A controller according to any one of the preceding claims, wherein the program memories are read/write memories and the controller is selectively settable into a normal, run mode in which said data words are read from the program memories and used to control the output channels, and a programming mode in which predetermined data words can be written into the program memories by the operation of programming means of the controller, said programming means including memoryselect means operative when the controller is in its programming mode to override said memory enabling means and enable the selection of the program memory into which a data word is to be written, address-select means arranged to address a desired address location in the program memory selected by the memory-select means, and data setting means for setting in a predetermined data word into the selected address location of the selected memory, said address-select means being constituted by said clock means and the latter being advanceable at a faster than real time rate to accelerate the process of address selection during operation of the controller in its programming mode.

5. A controller according to Claim 4, wherein the clock means comprise a real time clock advanced at real time rate during both the run and programming modes of operation of the controller, and a programming clock advanceable at a greater than real time rate during said programming mode, the real time being arranged to address the said enabled program memory during the run mode and the programming clock being arranged to address the said selected program memory during the programming mode.

6. A controller according to Claim 4 or Claim 5, wherein during operation of the controller in its programming mode, the memory-select means of the programming means is arranged to select each program memory in turn during successive 24-hour cycles passed through by the programming clock.

7. A controller according to Claim 1 further comprising holiday control means arranged to override, for a predetermined number of consecutive 24-hour periods, the normal pattern of programmemory enablement effected by the memory enabling means, said predetermined number being preset into a memory of the holiday control means by the user, the holiday control means being further arranged such that during the override period, a particular one of the program memories is enabled continuously to the exclusion of the other memories.

8. A controller according to Claim 7, wherein at the end of the override period, the controller is arranged to revert to its normal pattern of programmemory enablement as if it had been following through this pattern during the override period.

9. A controller according to any one of the preceding claims, implemented by use of a microprocessor.

10. A multi-channel time-switched controller substantially as hereinbefore described with reference to the accompanying drawings.