GB2097618A - Method and apparatus for locking a phase locked loop onto a reference signal - Google Patents

Abstract

A modulated carrier is fed to a balanced demodulator (18) which also receives a reference carrier from a voltage controlled oscillator (34) to produce an error signal representing phase and frequency error between the two carriers. The error signal is sampled in a sampler (22) and the sample integrated in an integrator (30). To prevent the loop locking onto a side-band of the modulated carrier an offset signal is fed by a frequency search system (36) to the integrator (30). The modulated carrier may be a television signal which is sampled by field and line banking pulses, the integrator having a short and long time constants associated with the field and line samples respectively. The offset (40, 42, 38, C150) is removed once locking is achieved. <IMAGE>

Description

SPECIFICATION Method and apparatus for locking a phase locked loop on to a reference signal The present invention relates to method and apparatus for locking a phase locked loop on to a reference signal.

In the "Triax" television camera system, a single double shielded cable (triaxial cable) is used for carrying signals from the camera head (CH) to the central processing unit (CPU) and vice versa. Among several other signals, three wide band video signals containing red, green and blue information of a scene being viewed by the CH have to be transmitted to the CPU. In a particular system the method chosen to do this is frequency multiplexing, with three different crystal controlled carriers on 16.5, 28.5 40.5 MHz respectively. These carrier frequencies can also be chosen differently. Double sideband-suppressedcarrier amplitude modulation is used.

In orderto demodulate such a signal at the CPU, the carrier has to be regenerated with a phase locked loop (PLL) system having a demodulator, integrator and an inductor-capacitor (LC) voltage controlled oscillator (VCO). The video signal during certain of its intervals, such as the line of horizontal and vertical or field blanking periods, can be used as a phase reference for the PLL. The phase reference samples an error signal from the demodulator, which error signal is a sine wave when the PLL is not locked onto the carrier frequency. Consider however, the use of horizontal blanking pulses as sampling pulses in such a sampled system. The pulses can sample nearly equal positive and negative portions of the sine wave error signals when the frequency of the sine wave corresponds to a harmonic of the horizontal sampling frequency.The result is little or no error voltage applied to the integrator in the PLL.

Hence a frequency control voltage for the VCO derived from the integrator remains unchanged, and therefore the PLL may lock onto a sideband of the supressed carrier, which sideband has a frequency that differs from the carrier frequency by the sampling frequency of a harmonic thereof.

Further, a wide frequency pull-in rangeforthe PLL is necessary because of the tolerances and frequency drift of the LC VCO. A more stable crystal controlled oscillator is not possible in the camera system, because at the frequencies involved, the crystals have to work at their third harmonic and can only be pulled over a very limited frequency range (maximum a few hundred hertz), which is not enough to deal with tolerance and temperature drift of the crystals oscillator in the camera head. A wide PLL pull-in range requires a small time constant in the integrator; however, a large time constant is desired for increased noise immunity.

It is therefore desirable to have a PLL which at least avoids false lock ups and which, preferably also has a wide pull-in range and/or high noise immunity.

According to one aspect of the invention, there is provided a method for locking the phase and frequency reference signal of a phase locked loop onto a predetermined phase and frequency associated with an input signal, said method comprising sampling a signal varying in accordance with said input signal to produce samples indicative of phase and/or frequency errors between the signals, and responding to the samples to avoid false lock ups of said loop on other than said predetermined phase and frequency associated with the input signal.

For a better understanding of the invention, reference will now be made by way of example to the accompanying drawings, in which: Figure 1 shows a block diagram of a first illustrative embodiment of the invention for use at the CPU.

Figure 2 shows a detailed circuit diagram of the embodiment of Figure 1; Figure 3 shows a block diagram of a second illustrative embodiment of the invention; and Figure 4 shows a detailed circuit diagram of the embodiment of Figure 3.

Referring to Figure 1, a double sideband suppressed carrier modulated video signal is received at input terminal 10 and applied to first balanced demodulator 12 which demodulator also receives a carrier signal from phase shifter 14. The signal from shifter 14 has a phase arbitrarily called zero degrees.

The video demodulated signal at the output of balanced demodulator 12 is amplified, filtered and clamped in the video processor 16. Also an automatic gain control signal is derived here.

Asecond balanced demodulator 18 receives a carrier signal from phase shifter 14 that has a 90 degree phase shift with respect to the phase of the carrier applied to demodulator 12. Demodulator 18 provides an error signal representing the frequency and phase differences between the suppressed carrier signal and the VCO 34 output signal, which error signal is amplified by amplifier 20. The error signal is sampled during the constant signal amplitude line or horizontal and field or vertical blanking times by a sampler 22 that receives both horizontal and vertical blanking pulses from a sync generator (not shown) that is present in the CPU.

Resistors 24 and 26 provide selected time constants (explained below) for the error signal samples occurring during horizontal and vertical intervals respectively. Thereafter, the error signal samples are fed to the inverting input of amplifier 28 of a "hold" integrator 30, which also comprises a capacitor 32.

The time constant of integrator 30 with resistor 24 is about 20 milliseconds for good noise immunity.

High noise immunity is important for errnr signal samples occurring during horizontal blanking periods, since active video occurs shortly thereafter and any error due to a noisy reference signal will cause picture jitter. The time constant of integrator 30 with resistor 26 is about 4 milliseconds. High noise immunity is not so important during vertical blanking periods, since the horizontal error signal samples occur shortly thereafter to maintain locking of the PLL. Therefore a short time constant is used to ensure a short lock up time of the PLL.

The output of integrator 30 changes the frequency of VCO 34 by use of a voltage variable capacitor (not shown) in VCO 34 in order to minimize the error signal. If the reference oscillator 34 is free-running, which can be the case after switching on the PLL or after disconnection of the incoming video signal, the frequency might be relatively far away from the nominal frequency. Sidebands or spurious signals, e.g., harmonics of the line frequency, in the input signal could upset correct locking. Either no locking is achieved or locking to a spurious frequency may occur. To prevent unwanted locking, a DC offset voltage is introduced at the non-inverting input of amplifier 38 by a frequency search system 36 in accordance with the present invention.

When locked onto a harmonic of the horizontal sampling frequency, the amplitude of the signal at the inverting input of amplifier 28 is low since nearly equal positive and negative portions will be sampled as was explained above. Therefore, the difference between the offset voltage and the error signal is integrated by integrator 30 to cause VCO 34 to frequency sweep either towards or away from the correct lockup frequency. This is true since the sideband amplitude, and therefore the sampled error signal amplitude, is small compared to the offset signal amplitude, thence cannot "override" the offset signal amplitude. Just before locking onto the correct carrier frequency, there is a large amplitude low frequency error signal compared to the amplitude of the offset signal due to the phase differences between the VCO 34 output signal and the carrier signal at input 10.

Again the difference between the error and offset signals is integrated, this time causing locking of VCO 34 onto the carrier frequency. Due to the characteristic of demodulator 18, once frequency locking is achieved, the error signal amplitude decreases as phase locking occurs until it equals the amplitude of the offset signal. Since amplifier 28 amplifies the voltage difference between its inputs, which difference is now zero, no more charge is supplied to capacitor 32. Capacitor 32 now holds a fixed charge, and thus supplies a fixed voltage to VCO 34. Therefore the frequency of VCO 34 is now a constant, i.e., that of the carrier frequency. Since the integrator 30 output level might be at one end of its range due to the offset voltage at its input, VCO 34 may not lock up.This problem can be overcome by reversing the phase of the offset as soon as one end of the integrator output range is reached. How this is accomplished, can be seen from the detailed circuit diagram in Figure 2.

In Figure 2, U108 is the sampler 22. The samples of the error signal during horizontal blanking periods appear at pin 2 and the samples of the error signal during vertical blanking appear at pin 4. U109 is the operational amplifier 28 connected as an integrator 30 by capacitive feedback via C135 (32) and R151 (for stability reasons).

The integrator offset is introduced to the noninverting input of U109, pin 3, and is generated by a Schmitt trigger Us 10 (36). Assuming a positive voltage offset at pin 3 of U109, the voltage at output pin 6 starts to rise (become more positive) until a threshold voltage level (the threshold level of U110, which equals one half of the supply voltage) established by R1 53 and R154 is reached. U110 then quickly changes state and a negative voltage offset is applied to U109. The integrator 30 output voltage then falls until the (changed) threshold is reached.

The output of Us 09 therefore will be a triangle voltage waveform without an input reference signal.

Assuming there is an input signal, VCO 34 will change its frequency in response to the output voltage from U109 until the incoming carrierfrequency is reached. If search system 36 were not present, the error signal would now be zero. However, due to system 36, the error signal voltage will have equal amplitude and the same polarity with respect to the offset voltage, and the PLL will frequency lock. Since the output of integrator 30 is now constant, frequency sweeping by VCO 34 will stop.

In the embodiment of Figures 1 and 2 a small phase error between the signal from VCO 34 and the received input signal does exist because of the DC offset voltage introduced to lock VCO 34 under all conditions. Furthermore this offset can be positive or negative depending from which "side" the search control circuit locks VCO 34. This phase error causes a degradation ofthefrequency response (flatness) of the demodulated video signal from demodulator 12.

The flatness error only is about 0.5 dB across a video bandwidth of 5MHz, but unfortunately is different depending on the direction of the phase error. This may not be acceptable for certain applications.

It is therefore very desirable to switch off the offset voltage as soon as VCO 34 has been locked. Note that this offset only is used to ensure VCO locking.

The solution shown in the embodiment of Figure 3 is to include a comparator 42 and an analog gate shown as a switch 38 to disable the DC offset voltage as soon as VCO 34 has locked up. The control signal for analog gate 38 can be derived from automatic gain control processor 40. The AGC signal reaches its maximum value (e.g. 5V) if VCO 34 is unlocked and reaches less than 4V, if VCO 34 is locked and if level 10 is correct. A Schmitt trigger comparator circuit 42 having a threshold level of approximately 4.5V can therefore be used to switch analog gate 38.

Figure 4 shows a detailed circuit diagram of a portion of the embodiment of Figure 3. The circuit is essentially the same as given in Figure 2, with the exception of C150, U108b, and U120 which were added. If U 1 08b is closed, the offset voltage is present at pin 3 of U109. If U108b is opened the offset slowly disappears as C150 charges. As a result, the error signal at pin 2 of U109 follows the decrease in the offst voltage. Thus the phase error caused by the offset voltage disappears. Comparator U 120 forms comparator circuit 42 which derives the switchoff criteria from the AGC voltage.

Note that C150 provides smooth switchoff of the offset voltage, otherwise the frequency of VCO 34 would jump and phase lock of the PLL might be lost.

Claims (23)

1. A method for locking the phase and frequency of a reference signal of a phase locked loop onto a predetermined phase and frequency associated with an input signal, said method comprising sampling a signal varying in accordance with said input signal to produce samples indicative of phase and/orfrequen cy errors between the signals, and responding to the samples to avoid false lock ups of said loop on other than said predetermined phase and frequency associated with the input signal.

2. A method as claimed in claim 1 wherein said input signal comprises a modulated signal and further comprising demodulating said input signal with a reference carrier to produce a signal representative of phase and/or frequency error between the reference carrier and the carrier of the input signal and, said sampling step comprises sampling the error signal.

3. A method as claimed in claim 1 or 2 wherein said input signal comprises a television signal with which blanking periods are associated, and said sampling step comprises sampling the error signal during at least one type of blanking period.

4. A method as claimed in claim 1,2 or 3 wherein said avoiding step comprises integrating the difference between an offset signal and the said samples to produce a signal controlling the frequency of the reference signal.

5. A method as claimed in claim 4 wherein the error signal is sampled by a first sampling signal at a relatively slow rate and by a second sampling signal at a relatively fast rate, and the samples due to the first signal are integrated with a relatively short time constant and the samples due to the second signal are integrated with a relatively long time constant.

6. A method as claimed in claims 3,4 and 5 wherein said sampling step comprises sampling the error signal during both line and field blanking periods.

7. A method as claimed in claim 4, 5 or 6 further comprising reversing the polarity of said offset signal when a selected amplitude of the integrated signal is achieved.

8. A method as claimed in claim 4,5,6 or 7 further comprising ceasing to apply said offset signal once locking is achieved.

9. An apparatus for locking the phase and frequency of a reference signal of a phase locked loop onto a predetermined phase and frequency associated with an input signal, said apparatus comprising sampling means for sampling a signal varying in accordance with said input signal to produce samples indicative of the phase and/or frequency errors between the signals, and means responsive to the samples for avoiding false lock ups of said loop on other than said predetermined phase and frequency associated with said input signal.

10. An apparatus as claimed in claim 9 wherein said input signal comprises a modulated carrier and further comprising means for demodulating input signal with a reference carrier to produce a signal representative of phase and/or frequency error between the carriers and wherein said sampling means samples the error signal.

11. An apparatus as claimed in claim 10 wherein the reference signal is a double side-band suppressed carrier signal modulated by a video signal.

12. An apparatus as claimed in claim 9,10 or 11 wherein said input signal comprises a television signal with which blanking periods are associated, and said sampling means samples the error signal during at least one type of blanking period.

13. An apparatus as claimed in claim 8,9, 10, 11 or 12 wherein said avoiding means comprises means for integrating the difference between an offset signal and said samples to produce a signal controlling the frequency of the reference signal.

14. Apparatus as claimed in claim 13, wherein the sampling means samples the error signal using a first sampling signal at a relatively slow rate and using a second sampling signal at a relatively fast rate, and the integrating means integrates the samples due to the first signal with a relatively short time constant and integrates the samples due to the second signal with a relatively long time constant.

15. An apparatus as claimed in claims 12, 13 and 14 wherein said sampling means samples the error signal during both line and field blanking periods.

16. An apparatus as claimed in claim 13, 14 or 15 wherein said applying means comprises means for reversing the polarity of said offset signal when a selected amplitude of the integrated signal is achieved.

17. An apparatus as claimed in claim 16 wherein said reversing means comprises a Schmitt trigger.

18. Apparatus as claimed in any one of claims 9 to 17 further comprising means for disabling said avoiding means upon achieving correct lock up.

19. An apparatus as claimed in claim 18 wherein said disabling means comprises an automatic gain control means responsive to the demodulated signal for producing a gain control signal controlling the gain applied to the output signal, a comparator coupled to said processor and a switch coupled between said applying means and said integrating means and responsive to the comparator to prevent the application of the offset to the integrating means when the amplitude of the gain control signal exceeds a threshold associated with the comparator.

20. Apparatus for locking a phase locked loop onto a reference signal substantially as hereinbefore described with reference to Figures 1 and 2.

21. Apparatus for locking a phase locked loop onto a reference signal substantially as hereinbefore described with reference to Figures 3 and 4.

22. Method for locking a phase locked loop onto a reference signal substantially as hereinbefore described with reference to Figures 1 and 2.

23. Method for locking a phase locked loop onto a reference signal substantially as hereinbefore described with reference to Figures 3 anc! 4.