GB2095008A

GB2095008A - Complex digital multiplier

Info

Publication number: GB2095008A
Application number: GB8107773A
Authority: GB
Original assignee: Standard Telephone and Cables PLC
Current assignee: STC PLC
Priority date: 1981-03-12
Filing date: 1981-03-12
Publication date: 1982-09-22
Also published as: GB2095008B

Abstract

To multiply complex numbers each complex quantity is stored in a memory location (1, 2 and 3, 4) of a processor in the format W1=2<N>A+B and W2=2<N>C+D: that is, the real part is in the more significant half of the memory location. The two words W1 and W2 are then applied to a multiplier to give a product: W1W2=2<2N>AC+2<N)<AD+BC)+BD. Then the middle byte (AD+BC) is applied to an output latch (9) as the imaginary portion of the product. The third byte (BD) is subtracted from the first byte (AC) by a subtractor (7) the output of which is placed in another latch (8) as the real portion of the product. This reduces the number of processing steps, and current of equipment needed, as compared with conventional approaches. In an alternative, the positions of real and imaginary parts of one of the complex numbers are interchanged, in which case the words in the memory locations are in the format W1=2<N>B+A and W2=2<N>C-D. The product is then: W1W2=2<2N)<BC)+2<N)<AC-BD)-(AD). In this case the difference between the first and third bytes gives the imaginary part of the product and the second byte gives the real part. <IMAGE>

Description

SPECIFICATION Complex digital multiplier This invention relates to electrical multiplication circuits, such as are used, inter alia, for signal processing in certain radar and sonar systems.

In such systems it is sometimes necessary to multiply two complex quantities of the form N,=A+jB and N2=C+jD, where A, C and B, D are respectively the real and the imaginary parts. The product of two such quantities is: N1N2=(AC-BD)+j(AD+BC) Since most minicomputers and microprocessors have machine instructions dealing exclusively with real numbers, the normal practice to find such a product is to form four real quantities AC, BD, AD and BC, and get the real and imaginery components by the appropriate addition or subtraction. Thus four real multiplications and two real additions are involved.The same applies to hardware implementations as practically all multiplier chips on the market deal with real numbers, so that for a complex multiplication either four such chips have to be used, or one or two chips have to be arranged for sequential operation.

An object of the invention is to provide a method of and apparatus for multiplying two complex quantities which is more economical than the above methods.

According to the invention there is provided an electrical multiplication arrangement for multiplying two complex numbers expressed in the form N1=A+jB and N2=C+jD, in which the four number portions A, B, C and D are stored in a working memory in such a way as to form two computer words in the format W1=2N+B and W2=2NC+D, in which the two computer words thus formed are multiplied to give a product defined by the expression W1W2=22N(AC)+2W(AD+BC)+(BD) in which the first byte AC and the third byte BD are applied to a subtractor the difference output of which forms the real part of the product of the numbers N, and N2, and in which the second byte (AD+BC) forms the imaginary part of the product of the two numbers N1 and N2.

In another aspect of the invention the real and the imaginary parts of one of the complex numbers are interchanged, i.e. the complex numbers are stored in the memory in the form W1=2NB+A and W2=2NC#D, in which case the multiplication of the two memory words give the result W1W2=22N( BC) +2N(AC~BD)~(AD).

In this case the difference between the first and third bytes AC and AD gives the imaginary part of the product while the second byte (AC-BD) gives the real part.

Embodiments of the invention will now be described with reference to #the drawings, in which Fig.

1 is a flow sheet explanatory of the mathematical basis of our method, while Fig. 2 represents schematically a hardware implementation of the method.

If we take the four given numbers A, B, C and D as four bytes and form two new computer words, such that W1=2NA+B, - - - - - - andW2=2NC+ D, where N (equal to 8 in this case) is half the word length, then the product is W1W2=22N(AC)+2N(AD+BC)+BD.

The three bytes of the product can thus be- separated readily, with the difference of the first and third bytes giving the real part, and the second byte the imaginary part of the product.

The operation is illustrated diagrammatically in the flow sheet which forms Figure 1.

Two main points to consider to ensure the validity of the method are how to deal with negative numbers, and how to prevent the product bytes from overflowing.

Negative numbers With quantities being handled in the 2's complement number system, joining the real and imaginary bytes, A and B, to form a single word is an implementation of 2NA+B only if B is positive. For negative B's, the combined word when thus represented becomes 2N(A+1)+B since a string of l's preceding the lower input byte is being neglected. This gives, if left uncorrected, an error of 1 resolution bit in the upper input byte. Often, depending on the accuracy of the input quantities, this can be tolerated, and simplifies the circuit or algorithm. If it cannot be tolerated, to correct for this 1 bit error we use the input rule that when the real and imaginary bytes are joined to form a compound word, decrement the higher byte by one if the lower bytes is negative.

After the compound product word is formed, the bytes have to be separated into three independent quantities. Here the mechanism is the reverse of the previous process, so that an error of 1 bit is introduced into a particular byte if the immediately lower byte is negative. Again the bytes could be left as they are if acceptable, saving in execution time or circuit complexity. Otherwise we use the output rule that when a compound product word is decomposed into individual bytes to recover the real and imaginary parts, a particular byte has to be incremented by one if the next lower byte is negative. This process is done starting with the highest byte of interest.

Byte overflow For the byte decomposition process to produce valid output values, overflow from a lower byte to a higher byte during multiplication has to be prevented. This restricts the range of input values that we can use. Thus if we are dealing with output bytes of 8-bit precision, which implies a maximum resolution of +127 levels, the maximum multiplier or multiplicand value that can be used is 127 + +8.

2 That is, we can use input values of up to +8 levels, or 1 7 levels including zero, making each bit 6% of the total dynamic range. With this precision, a 5-bit input is necessary and sufficient to provide an unambiguous coverage for every number within the range, the peak position input value being: 01000=+8at and the peak negative input value: 11O00=-81c.

The maximum positive output value is given by: 01000x01000 or 1 1000x1 1000=01000000.

This gives a 50% of the total available output range.

The following table shows the number of bits of input value required for a specified output word length. For every choice of input word, there are two corresponding output word lengths, depending on the percentage of usage of the input word.

Table 1 No. of No. of %-age. No. of o/p bits max. i/p reso. of 1 i/p bits needed levels i/p bit needed 6 +4 11.1 4 7 +5 9.1 4 8 +8 5.9 5 9 +11 4.3 5 10 +16 3.0 6 11 +22 2.2 6 12 +32 1.5 7 13 +45 1.1 7 14 +64 0.78 8 15 +90 0.55 8 16 +128 0.39 9 17 +181 0.28 9 Error analysis In a particular realisation, it would be attractive if we could avoid using the rules for negative numbers at all, so we now examine the amount of error introduced if we leave the numbers uncorrected.

The combined multiplier is N,=2N(A+1)+B if B is negative and left uncorrected. Similarly, the combined multiplcand is N2=2N(C+1 )+D if D is negative and left uncorrected.

Thus the product becomes: N1N2=22N (AC+A+C+1)+2N(AD+BC+D+B)+BD.

Taking into account any possible uncorrected errors in the output decomposition, we have Maximum error in in-phase component=A+D+ 1, and Maximum error in quadrature component=B+D+1.

If the maximum input value allowed is m, the maximum output value is 2m2, and the 2m+ 1 Maximum percentage error= =~, 2m2 m which is of the same order as the error introduced by the uncertainty of the input values.

We can reduce this error by a factor of two if we offset the input value in the analogue to digital conversion process preceding input by half the quantisation level. That is, instead of allowing binary zero to represent an analogue value between +0.5 to -0.5, we let it represent a value between 0 and 1. The error thus introduced into the multiplier is N,=2N(Ai2)+B depending on whether B is negative or positive, and N2=2N(Ci1) + D, depending on whether D is negative or positive.

The product becomes N, N2=22N(ACiTAiiCi+) +2N(AD+BC+Di;B) +BD.

The maximum percentage error becomes m+ Tim 2m2 Another advantage of this offset is the more symmetrical distribution of errors about zero. Thus, if the multiplication is used in a correlation process for a long number sequence, the accumulation of errors would tend to zero for a truly random set.

Special purpose circuit Figure 2 shows an example of a hardware implementation using a 16-bitx 16-bit multiplier chip with output word length of 31 bits. We assume in this example that offset has already been introduced into the input values, and that any error due to uncorrected negative numbers can be tolerated.

In Figure 2 we see at the top the word organisation used: in view of the preceding description this is felt to be clear, bearing in mind that the shaded areas are blank (or ignored in the case of the product). From the clock schematic it will be seen that the four six bit words are present in the four latches 1, 2, 3, 4, from which they are applied to appropriate inputs of a 16 bit multiplier 5. This derives the four byte product mentioned above of which as can be seen two bytes are applied to the inputs of a subtractor 7, whose output is the real portion of the product, and is staticized in the latch 9 so that the outputs of these two latches give the required product. The 31 sot bit output is not used, as indicated by the letter NC.

From the Table 1, we see that if we chose an input resolution of 6 bits with each quantisation level equal to 2.2% of the full dynamic range, the minimum output resolution required is 10 bits. Thus, the three required output bytes will occupy 30 bits in total, making nearly full use of the available word length. The fourth byte, which is redundant, is lost in the overflow.

For each input word, the in-phase and quadrature components have to be combined with a separation of N bits, where N=1 0. Thus, the two values each of 6-bit precision, will occupy the two ends of the word, with a guard band of 4 null bits in the centre.

Compared with a conventional implementation, we are using one 16-bit multiplier and one adder instead of four 8-bit multipliers and two adders, together with the associated benefits of smaller board size and lower power consumption. The price we pay is that we can only operate on 6-bit input values instead of 8.

Claims

1. An electrical multiplication arrangement for multiplying two complex numbers expressed in the form N,=A+jB and N2=C+jD, in which the four number portions A, B, C and D are stored in a working memory in such a way as to form two computer words in the format W,~2NA+B and W2=2NC+D, in which the two computer words thus formed are multiplied to give a product defined by the expression W1W2=22NAC +2N(AD+BC)+BD in which the first byte AC and the third byte BD are applied to a subtractor the difference output of which forms the real part of the product of the numbers N, and N2, and in which the second byte (AD+BC) forms the imaginary part of the product of the two numbers N, and N2

2.An arrangement as claimed in claim 1, in which each of the four number portions A, B, C and D has a maximum number N of bits when expressed in binary form, in which portions A and B are stored in one memory location which can accommodate at least 2N bits with portion A in the more significant digit region of the location, and in which portions C and D are similarly stored in another similar memory location.

3. An electrical multiplication arrangement for multiplying two complex numbers expressed in the form N,=A+jB and N2=C+jD, in which four number portions respectively representing the portions A, B, C and D are stored in two locations of a working memory, each said memory location having a capacity of at least 2N bits, in which number portions A and B are stored in one of said memory locations with portion A in the more significant digit region of the location so that the complex number N, is stored in the format W1=2NA+B, in which number portions C and D are stored in the other of said memory locations with portion C in the more significant digit region of the location so that the complex number N2 is stored in the format W2=2NC+D, in which the two computer words W, and W2 are applied to an electronic multiplication circuit which derives therefrom a product defined by: W,W2=22N(AC)+2N(AD+BC)+(BD) in which the first byte AC and the third byte BD of the above expression are applied from the outputs of the multiplication circuit to a subtraction circuit the difference output (AC-BD) from which forms the real part of the product of the two complex numbers N, and N2, and in which the second byte (AD+BC) forms the imaginary part of the product of the two complex numbers.

4. An arrangement as claimed in claim 1, modified in that the four number portions A, B, C and D are stored in the working memory in such a way as to form two computer words in the format W,=2NB+A and W2=2NC#D, so that when the used words are multiplied the product is defined by the expression: W,W2=22N(BC)+sN(AC~BD)~(AD) in which the difference between the first byte BC and the third byte AD gives the imaginary part of the product of the two numbers while the second byte (AC-BD) forms the real part of the two numbers.

5. An arrangement as claimed in claim 4, in which each of the four number portions A, B, C and D has a maximum reading N of bits when expressed in binary form, in which portion A and B are stored in one memory location which can accommodate at least 2N bits with portion B in the more significant digit region of the location, and in which portions C and D are similarly stored in another similar memory location.

6. An electrical multiplication arrangement for multiplying two complex numbers expressed in the form N,=A+jB and N2=C+jD, in which four number portions representing the portions A, B, C and D are stored in two locations of a working memory, each said memory location having a capacity of at least 2N bits, in which number portions A and B are stored in one of said memory locations with portion B in the more significant digit region of the location so that the complex number N, is stored in the format W1=2NB+A, in which number portions C and D are stored in the other of said memory locations with portion D in the more significant digit region of the location so that the complex number N2 is stored in the format W2=2NC#D, in which the two computer words W, and W2 are applied to an electronic multiplication circuit which derives therefrom a product defined by: : W1W2=22N(BC)+2N(AC#BD)#(AD) in which the first byte BC and the third byte AD of the above expression are applied from the outputs of the multiplication circuit to a subtraction circuit the difference output (BC-AD) from which forms the imaginary part of the product of the two complex numbers N, and N2, and in which the second byte (AC-BD) forms the imaginary part of the product of the two complex numbers.