GB2094084A

GB2094084A - Level shifting circuit

Info

Publication number: GB2094084A
Application number: GB8106347A
Authority: GB
Original assignee: Tokyo Shibaura Electric Co Ltd
Current assignee: Toshiba Corp
Priority date: 1981-02-27
Filing date: 1981-02-27
Publication date: 1982-09-08
Also published as: DE3107581A1; GB2094084B; DE3107581C2

Abstract

An output circuit (OUT 10) and a biasing circuit (B1) for biasing an oscillation circuit (10) comprise a current mirror circuit the current of which is controlled by the bias voltage (62). The DC level of the output signal from the oscillation circuit (10) is level shifted in dependence on the relative numbers of diodes (D1,..Dn+1; D1..Dm) and the resistances of the resistors (R11, R12) in the two arms making up the current mirror circuit.The biasing circuit (B1) of the oscillation circuit (10) may thus be utilized as the level shifting circuit, the DC level of the output signal of the oscillation circuit (10) may be set to a predetermined level, and fluctuations in the duty ratio of the oscillation output may be suppressed. <IMAGE>

Description

SPECIFICATION Level shifting circuit This invention relates to a level shifting circuit. When transmitting the output of an oscillation circuit to a circuit of the next stage, the DC level of the oscillation output signal must correspond with the optimal driving condition of the circuit of the next stage. That is to say, it may be necessary to DC level shift the oscillation output signal so that it may correspond with the optimal driving condition of the circuit of the next stage. When the DC level is lowered by this level shifting, the oscillation signal is also attenuated. This results in a disadvantage in that the predetermined signal may not be obtained as the output of the next stage when there are fluctuations in the amount of the DC level shift.Accordingly, it is necessary to level shift the oscillation output signal to amplify the attenuated signal and then to DC level shift to transmit the output of the oscillation circuit to the circuit of the next stage.

When DC level shifting the output of the oscillation circuit, the attenuated oscillation signal must be amplified. A level shifting circuit for raising the DC level of the output of the oscillation circuit to a predetermined value is thus desired.

It is an object of the present invention to provide a level shifting circuit which includes a biasing circuit of a signal generating circuit and which is capable of constantly providing a predetermined level shifting amount for every level shifting operation.

It is another object of the present invention to provide a level shifting circuit which is of the circuit configuration wherein a current equal to the current flowing through the biasing circuit for biasing the signal source circuit is supplied to the output stage of the signal generating circuit by a current mirror circuit; and which is capable of suitably transmitting the output signal of the signal generating circuit to the circuit of the next stage by determining the current value to flow through the current mirror circuit.

This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figure 1 is a circuit diagram illustrating an embodiment of the level shifting circuit of the present invention; Figure 2 is a circuit diagram illustrating another embodiment of the level shifting circuit of the present invention; Figure 3 is a circuit diagram illustrating a case wherein the first embodiment of the level shifting circuit of the present invention is applied to an oscillation circuit; Figure 4 is a block diagram for showing the mode of operation of the oscillation circuit shown in Figure 3; Figure 5 is a vector model diagram for showing the mode of operation of the oscillation circuit shown in Figure 3; and Figure 6 is a circuit diagram for showing the mode of the level shifting operation in the case wherein the level shifting circuit of the present invention is applied to the oscillation circuit.

The present invention relates to a level shifting circuit of the circuit configuration in which the biasing circuit of the signal generating circuit is used for shifting the DC level of the output signal.

When transmitting the signal of the signal generation circuit to the circuit of the next stage, the DC output level of the signal generating circuit must correspond with the predetermined operating point of the circuit of the next stage. That is, a level shifting circuit is required for the signal generating circuit to shift the DC level of the output signal of the signal generating circuit according to the DC operating point of the circuit of the next stage. When the level shifting is performed on the output of the signal generating circuit to lower the DC level, the signal component is also attenuated. Accordingly, a level shifting circuit is desired with which the adverse effects provided to the output signal by the DC level shifting operation are eliminated.

The present invention has been made to overcome the problems associated with DC level shifting of the signal by utilizing, in the level shifting circuit, a biasing circuit of the signal generating circuit. The various features and advantages of the present invention will become apparent from the detailed description of the invention to follow.

Figure 1 is a circuit diagram illustrating an embodiment of the level sh#ifting circuit of the present invention.

Referring to Figure 1, reference numeral 10 denotes a signal generating circuit for generating signals, which is biased by a voltage source Eel. A voltage source E2 provides a voltage depending on the biasing voltage source El and biases one biasing circuit B1 among the-9iasing circuits of the signal generating circuit 10.The biasing circuit B1 comprises a transistor Q11 whose base is biased by the voltage source E2 and whose collector is biased by the voltage source El; and diodes1 to Dn+l and a resistor R11 connected to the emitter side of the transistor 011. A node T1 of the resistor R1 1 and the diode Dn of the biasing circuit B1 is connected to a terminal T10 of the signal generating circuit 10 in such a manner that a biasing voltage is supplied to the signal generating circuit 10. The signal genecating circuit 10 outputs an output signal from a terminal T20 with the DC level E2.A node T2 of the diode Dn+1 and the resistor R11 of the biasing circuit B1 is connected to the base of a transistor 013 connected in series with a transistor Q12 forming an output circuit OUT10 which functions as an output stage circuit for the signal generating circuit 10, thus comprising a current mirror circuit. A series circuit of diodes numbering m and a resistor R12 is connected between the emitter of the transistor 012 and the collector of the transistor 013. The resistances of the resistors R11 and R12, the number of diodes in the biasing circuit B1, and the number of diodes in the output circuit OUT10 are so selected that the DC level across a node P10 between the resistor R12 and the collector of the transistor 013 of the output circuit OUT10 becomes VF (forward voltage of the diodes).

In Figure 1, it is to be noted that the biasing circuit B1 and the output circuit OUT1 0 for the signal generating circuit 10 comprise a current mirror circuit and a level shifting circuit at the same time. With this construction, the DC level across the output terminal P10 of the output circuit may be held at a constant voltage VF, as will be described hereinafter.

Describing the mode of operation of the level shifting circuit of the present invention shown in Figure 1, the collector current 10 of the transistor Q11 whose base is biased by the voltage source E2 may be represented by the following equation: lO=E2##(n1)2)Vf Vf where it is assumed that the characteristics of the diodes numbering (n + 1) of the biasing circuit B1 are the same as those of the diode formed by the base and the emitter of the transistor (111.

The terminal voltage (VF + RI 110) across the terminal T1 of the biasing circuit B1 through which the current 10 represented by equation (1) flows is applied to the terminal T10 of the signal generating circuit 10 as a biasing voltage.

Since the diode Dn+1 of the biasing circuit B1 and the transistor 013 of the output circuit OUT10 are connected to form a current mirror circuit, the collector current of the transistor Q13 is equal to the current represented by equation (1) (provided that the characteristics of the diode Dn+1 are equal to the base-emitter characteristics of the transistor Q13).From this, the level shifting amount AVl by the diodes D1 to Dm, the resistor R12, and the transistor 013 of the output circuit OUT10 may be represented by the following equation: R12 AV = mVf + R11 - (n + 21VF} When it is assumed that an AC signal is superposed on the DC voltage E2 at the output terminal T20 of the signal generating circuit 10, the DC level VP10 across the terminal P10 of the output circuit OUT10 may be represented from equations (1) and (2) as follows:: VP10 = (E2 - VF) - AV R12 R12 R11 (1~R11)E2~(m + 1)~{R~(n + 2)}VF ...(3) If R11 = R12, and m = n, VP10 = VF ...(4) It thus follows from this that the DC voltage level across the terminal P10 of the output circuit OUT10 may be held at VF if the resistances of the resistors R1 1 and R12 are equal to each other and if the number of diodes connected between the emitter of the transistor 011 and the resistor R11 of the biasing circuit B1 is equal to the number of diodes connected between the emitter of the transistor Q12 and the resistor R12 of the output circuit OUT10. The DC level across the terminal P10 of the output circuit OUT10 is not affected by fluctuations in the DC level across the terminal T20 of the signal generating circuit 10. Therefore, a drive transistor 014 of the circuit of the next stage may be driven in a stable manner without being affected by fluctuations in the biasing power source of the signal generating circuit.

Figure 2 is a circuit diagram illustrating another embodiment of the level shifting circuit of the present invention. The basic configuration is the same as that of the circuit shown in Figure 1. The same parts are denoted by the same reference numerals as in Figure 1. The circuit shown in Figure 1 is different from that shown in Figure 2 in that a plurality of diodes KD1 to KDn2 are connected between the terminal T2 of the biasing circuit B10 and the ground potential, a resistor R30 is connected at the emitter side of the transistor (113, and diodes MD1 to MDm-1 are connected to the drive transistor 014 of the circuit of the next stage.

Although the potential of the terminal P10 was VF in the circuit shown in Figure 1, in the circuit shown in Figure 2, the DC level of the terminal P10 is set at a voltage which is different from VF.

Describing the mode of operation of the circuit shown in Figure 2, the voltage across the terminal T2 of the biasing circuit B10, that is, the base voltage V1 of the transistor 013 of the output circuit OUT20, may be represented by equation (5) below: V1= R11+R20 E2+ {n2 - R11 + R20 (ni+n2+1)}VF (5) where n1 is the number of diodes connected between the emitter of the transistor Q11 and the resistor Rl 1, and n2 is the number of diodes connected between the terminal T2 and the ground potential.

The voltage across the terminal T1 of the biasing circuit B10 is applied to the terminal T10 of the signal generating circuit 10 as a biasing voltage. Taking into account that the AC signal is superposed on the DC level E2 across the terminal T20 of the signal generating circuit 10, the voltage V2 across the collector of the transistor Q13 of the output circuit OUT20, that is, the DC voltage level across the terminal P10, may be represented by equation (6) below:: R40 V2=E2-(n3+i)VF-(Vl VF)R3O R20 R4O R11 + R12 R30) { R40 R20 (n1 + N2 + 1) - R40(n2 - 1)} (6) R30R11+R20 R30 If the resistors R11, R20 and R30 have such resistances as would satisfy the following equation (7), the DC level variation at the terminal T20 of the signal generating circuit 10 will not affect the DC level at the terminal P10 of the output circuit OUT20.

R20 R20 = 1 R11 + R20 R30 If equation (7) is satisfied, equation (6) will be transformed as follows: R40 R40 V2={(R30 - 1)n - (n1 + n3 + R30)}VF The DC level at the terminal P10 of the output circuit OUT20 is expressed by equation (8). Voltage necessary for operating the drive circuit of the next stage is determined by various factors such as voltage ratio of the resistors R40 and R30, the number nl of diodes to be connected between the emitter of the transistor Q11 and the terminal T2, the number n2 of diodes to be connected between the terminal T2 and the ground potential and the number n3 of diodes to be connected between the emitter of the transistor 012 and the terminal P10.Here, it is necessary to select the resistance ratios R40/R30 and nl, n2 and n3 - all in equation (8)--in order to satisfy equation (7).

In the circuit of Figure 2 it is sufficient to choose the DC level at the terminal P10 to be mVF in order to drive the signal generating circuit 10 and the transistor 014 of the next stage circuit. That is, if R4O/R3O and nl, n2 and n3 appearing in equation (8) are of such values as satisfy equation (7) and as provide DC level of mVF at the terminal P10, the DC level of the output circuit P20 will be mVF, now matter how the change of the DC level at the terminal T20 of the signal generating circuit 10.

Examples of constants which satisfy the conditions of equations (7) and (8) in Figure 2 will be shown below: (i) when m = 2, R11 = 1 k#,R2O= 1 kQ, R30 = 1 k#,R30 = 1 k#,R4O=2k#,V2=2VFifnl =O,n2=4,andn3=O (ii) when m 3 R11 = 1k#,R20 = 1k#,R30 = 1k#,R40 = 2k#,V2 = 3VFifn1 = 1,n2 = 6,and n3 = 0 Figure 3 is a circuit diagram illustrating a case wherein the level shifting circuit of the present invention is applied to an oscillation circuit. In this circuit diagram, the signal generating circuit 10 in Figure 1 is replaced by an oscillation circuit.

Referring to Figure 3, E10 is a voltage source. The collector of a transistor 021 is connected to the voltage source El 0 and the base of it is connected to the voltage source El through a resistor R21. The emitter of the transistor 021 is connected to the ground potential through a series circuit of a resistor R22 and a diode D21 as well as to the base of a transistor Q22. The circuit consisting of the transistor 021, the resistors R21 and R22, and the diode D21 comprise the biasing circuit B20 for biasing the base of the transistor Q22.

An oscillation circuit 20 surrounded by a broken line in Figure 4 corresponds to the signal generating circuit 10 in Figure 1. This oscillation circuit 20 comprises a differential amplifier including transistors Q22 to Q27, resistors R23 and R24, and a constant current source 10, a resonance circuit consisting of a capacitor connected to a common terminal of the collectors of the transistors 022 and Q24, and a coil L21; a phase shifting circuit consisting of a capacitor C22 and a resistor R25; a transistor 028 whose base is connected to this phase shifting circuit and whose emitter is connected to the ground potential through a resistor R27 and a diode D22 as well as to the bases of the transistors 023 and 024; and a resistor R26 connected between the collectors of the transistors 022, 024 and the terminal T20.A control voltage for controlling the oscillation frequency is applied between the base electrodes of the transistors 026 and 027.

An output circuit OUT30 comprises a transistor Q29 whose base is connected to the terminal T20, a transistor Q30 making up a current mirror configuration together with the diode D21 of the biasing circuit B20, and a resistor R28 connected between the collector of the transistor 030 and the emitter of the transistor 029. A transistor 031 is the drive transistor of the circuit of the next stage.

An equivalent circuit for the oscillation circuit 20 of the configuration described above is shown in Figure 4.

Referring to Figure 4, symbols Al and A2 are transconductance amplifiers, comprising differential amplifiers and having transconductances gml and gm2, respectively. The transconductances gml and gm2 are differentially controlled by the control voltage applied to the bases of the transistors Q26 and 027 shown in Figure 3. The resonance circuit (C21, L21) and the phase shifting circuit (C22, R25) shown in Figure 3 are connected in an equivalent circuit with the transconductance amplifiers Al and A2 in the manner shown in Figure 4.

In Figure 4, the values of the respective elements of the phase shifting circuit (C22, R25) are so determined that ot0C22 = 1/R25 where the resonance frequency of the resonance circuit is wO. The voltage vector and the current vector across the output terminal of the resonance circuit are represented as Vb and 10; and the voltage vector across the resistor R25, V'1; the voltage vector across the capacitor C22, V2 These voltage vectors V 1 and V2 are fed back to the transconductance amplifiers Al and A2, respectively, to control the values of the transconductances gml and gm2. The transconductances gml and gm2 are controlled by the control voltage vc described above.Referring to Figure 5, when oscillating at the central angle frequency wO, the vector 1 is advanced by #4 with respect to the reference Vband the vector V2 is out of phase by #4 with respect to the reference vectors These voltage vectors V1 and v2 are fed back to the transconductance amplifiers Al and A2, respectively, to be converted into the current vectors 11 and 1'2as shown in Figure 5(a).

When the control voltage vc is O at this time, the absolute values of these vectors 11 and 12are equal to each other so thatthe oscillation is performed at the central angle frequency wO. When control is performed such thatvc > 0 and gml > gm2, oscillation is capacitive (Figure 5(b). When the control voltage vc < 0 and gm1 < gm2, the conditions for inductive oscillation are satisfied (Figure 5(c)). The oscillation frequency may thus be varied by varying the control voltage.

The output of the oscillation circuit 20 is level shifted by the output circuit OUT30 through the resistor R26.

This will now be described in more detail.

As has already been described, the diode D21 of the biasing circuit B20 and the transistor Q30 of the output circuit OUT30 comprise a current mirror circuit. The current 110 flowing through the biasing circuit B20 and the collector current of the transistor 030 are equal to each other. Since the current flowing through the resistor R21 is extremely small, when the base voltage of the transistor Q21 is approximately equal to the voltage of the voltage source El 0, current 110 flowing through the biasing circuit may be represented by the following equation: 110 = E10 - 2VF ...(9) R22 The approximation used to obtain equation (9) corresponds to an approximation of El =. E2 in Figure 2.

The voltage (E20 - VF) across the terminal T10, to which is connected the resistor R22 through which the current 110 represented by equation (9) flows, is utilized as a voltage for biasing the transistor 022 of the oscillation circuit 20.

As has already been described, the collector current of the transistor Q30 of the output circuit OUT30 is represented by equation (9), and the collector voltage V3 of the transistor Q30 is represented by equation (10) below. It may be approximated that the voltage of E10 is applied to the base of the transistor 029, neglecting the voltage drop across the resistor R26. Therefore, the voltage V3 at the terminal P10 may be represented by the following equation: R28 R22 R28 2R28 = (1~R22)E10~(1~ R22)VF ...(10) When the values of the resistors R22 and R28 are so selected to satisfy R22 = R28...(1 1) in equation (10), the DC level across the output circuit P10 may be held at the constant voltage VF, regardless of fluctuations in the DC level across the base of the transistor 029.The drive transistor 031 of the circuit of the next stage may thus be driven in a stable manner.

It has already been described that one of the features of the level shifting circuit of the present invention is that the biasing circuit also functions as the level shifting circuit. For the sake of simplicity, the mode of operation for level shifting alone is illustrated in Figure 6.

According to Figure 6, the output circuit OUT30 is biased by the voltage source E10, and the output signal of the oscillation circuit 20 is superposed on the DC level of E20. Since El 0 was approximated by the DC level across the terminal T10 which is the base of the transistor 029 when obtaining equation (10), the DC level E20 holds the relation, Eel 0 . E20. As has been described, in Figure 6, the DC level of the terminal P10 is level shifted to the constant DC level VF. Therefore, it is seen from Figure 6 that the level shifting circuit of the present invention is capable of level shifting the DC level to a predetermined DC level compatible with the drive circuit of the circuit of the next stage, even when there are voltage fluctuations in the DC level of El O before level shifting.

Claims

1. A level shift circuit comprising: a signal processing circuit for producing as output a signal for DC level shifting; a biasing circuit for biasing a predetermined active element in said signal processing circuit with a predetermined voltage; a current generating circuit for generating current corresponding to the amount of current flowing through said biasing circuit; an output circuit for rendering the DC level of the output signal of said signal processing circuit to a predetermined level by making use of the current generated by said current generating circuit; and an output terminal for delivering a signal the DC level of which is shifted in said output circuit.

2. A level shift circuit according to claim 1, wherein the DC level of the output signal of said signal generating circuit is shifted in dependence upon the level of current flowing through said output circuit by said current generating circuit and also in dependence upon the number of diodes and the resistance of resistor consisting of said output circuit.

3. A level shift circuit according to claim 1, wherein said current generating circuit for generating current corresponding to the level of current flowing through said bias circuit includes a current mirror circuit having a transistor with the collector connected to said output terminal and the emitter connected to a reference potential terminal and constituting said output circuit and one of diodes connected between the base of said transistor and said reference potential terminal and constituting said bias circuit.

4. A level shift circuit according to claim 1, wherein: said bias circuit includes a transistor biased at the base with a predetermined voltage, a diode and a resistor connected between the anode of the diode in said current generating circuit for determining the bias current; said output circuit includes a transistor having the base upon which the output signal of said signal processing circuit is impressed and a series circuit of a diode and a resistor connected between the emitter of said transistor and the collector of a transistor having the base energized through a bias diode in said current generating circuit; and the number of diodes and resistance of said bias circuit are equal respectively to the number of diodes and resistance of said output circuit.

5. A level shift circuit according to claim 1, wherein: said bias circuit includes a series circuit of a transistor having the base energized with a predetermined voltage, nl series diodes connected in the emitter circuit of said transistor and a first resistor, n2 diodes and a second resistor forming said current generating circuit;; said output circuit includes a transistor constituting said current generating circuit and having the base biased by the terminal voltage across a series circuit of the n2 diodes and resistor constituting said bias circuit, a third resistor connected between the emitter of said transistor and a reference potential terminal, a transistor having the base which the output of said signal generating circuit is impressed upon, and a series circuit of n3 diodes and a fourth resistor connected between the emitter of said transistor and the collector of a transistor constituting said current generating circuit; and the resistances of said first resistor, the second resistor, the third resistor and the fourth resistor are set to satisfy a relation R20 R40 - 1 Rq, + R20 R30

6.A level shift circuit comprising: a signal processing circuit for producing as output a signal for DC level shifting; a transistor having the base biased by a voltage of a level substantially equal to the DC voltage level at the output terminal of said signal processing circuit; a first impedance circuit connected to the emitter of said transistor; a diode connected between said first impedance circuit and a reference potential terminal; a transistor having the base which the signal from the output terminal of said signal processing circuit is impressed upon; a second impedance circuit connected in the emitter circuit of said transistor; a transistor having the collector connected to said second impedance circuit, the emitter connected to said reference potential terminal and the base energized by the forward voltage across said diode; and an output terminal connected to the collector of said transistor, a signal obtained by DC level shifting of the output signal of said signal processing circuit being provided from said output terminal.

7. A level shift circuit according to claim 6, wherein the impedance of said first impedance circuit is made equal to the impedance of said second impedance circuit.

8. A level shift circuit according to claim 6, wherein said first impedance circuit includes nl diodes and a first resistor, and said second impedance circuit includes n2 diodes and a second resistor, the resistance of said first resistor being equal to the resistance of said second resistor, and the number of the diodes nl being equal to n2.

9. A level shift circuit comprising: a signal processing circuit for producing an output signal for DC level shifting; a first transistor having the base biased by a voltage substantially equal to the DC voltage level at the output terminal of said signal processing circuit; a series circuit of first and second impedance circuits connected between the emitter of said first transistor and a reference potential terminal; a third impedance circuit connected to the emitter of said transistor; a third transistor having the collector connected to said third impedance circuit, the base energized by the terminal voltage across said second impedance circuit and the emitter connected through a fourth impedance circuit to said reference potential terminal; and an output terminal connected to the collector of said third transistor, a signal obtained through the DC level shifting of the output signal of said signal processing circuit being provided from said output terminal.

10. A level shift circuit according to claim 9, wherein said first impedance circuit includes nl diodes and a first resistor, said second impedance circuit includes n2 diodes and a second resistor, said third impedance circuit includes n3 diodes and a third resistor, and said fourth impedance circuit includes a fourth resistor, the resistance of said first resistor, the resistance of said second resistor, the resistance of said third resistor and the resistance of said fourth resistor being set to satisfy a relation R20 R40 1 R11 + R20 R30 11.A level shift circuit comprising: a bias circuit including a first impedance circuit connected in series with a diode forming a current mirror circuit; a signal generating circuit including an active element biased by said bias circuit and generating an output signal of a predetermined DC level at the output terminal; an output circuit including a first transistor having the base which the output signal from said signal generating circuit is impressed upon, a first impedance circuit connected to the emitter of said transistor, and a second transistor having the collector-emitter path connected between said first impedance circuit and said reference potential terminal and forming a current mirror circuit together with said diode; and an output terminal connected to the collector of said second transistor, a signal obtained through the DC level shifting of the output signal from said signal generating circuit being provided from said output terminal.

11. A level shifting circuit, substantially as hereinbefore described with reference to the accompanying drawings.