GB2093648A - Phase detector circuit - Google Patents

Abstract

Horizontal sync signal is applied to a phase detector (23) as well as to a gate circuit (25). The output of a VCO (27) is applied via a divider (28) to a second input terminal of the phase detector (23) which outputs a pulse having a pulse width proportional to the phase difference. This phase detection pulse is applied through a buffer (24) to a gate circuit (25). In the gate circuit (25), the current path from the phase detection pulse input terminal to the gate output terminal is held conductive during the period of the gating pulse, and an output pulse whose duty ratio varies according to the pulse width of the phase detector output is obtained. This output pulse is smoothed through a filter (26) to be applied as an oscillation frequency control voltage input to the VCO (27). <IMAGE>

Description

SPECIFICATION Phase detector circuit This invention relates to phase detector circuits. This sort of the circuits are used for, for example, color signal processing circuits in video tape recorders and the like.

In the recording to NTSC video signals of magnetic tape with a video tape recorder, the luminance signal and chrominance signal are separated from the video signal to be recorded.

The luminance signal is frequency modulated at a frequency modulator, while the chrominance signal is converted into a signal with a low frequency subcarrier in a color signal processing circuit. The frequency modulated luminance signal and the converted chrominance signal are combined in a mixing circuit, and the resultant signal is recorded on a magnetic tape by a magnetic head. In the color signal processing circuit, the subcarrier frequency of the chrominance signal is converted from fSc = 3.58 MHz to (44 - OfH (fH denotes the frequency of the horizontal sync signal). The color signal processing circuit includes a converting signal generator for converting the original chrominance into the converted chrominance signal.The converting signal has a frequency of the sum of the original subcarrier frequency (3.58 MHz) and the converted subcarrier frequency (688 kHz), and is synchronized to the horizontal sinc signal. The converting signal is also controlled such that it can be used a burst signal. An automatic frequency control circuit (abbreviated as AFC circuit) synchronizes the converting signal frequency 175 (3.58 MHz + 688 kHz = fsc + --fH) 4 to the horizontal sync signal frequency.The automatic frequency control circuit includes a voltage-controlled oscillator (abbreviate as VCO), a frequency divider for dividing the frequency oscillated from the VCO output, an integrating circuit for integrating the frequency divider output and resultingly generating a sawtooth wave signal, and an AFC detector to which the sawtooth wave signal (which is a compared pulse signal) and the horizontal sinc signal (which is a reference pulse signal) are coupled. The AFC detector provides an output which voltage corresponds to the phase difference between the sawtooth wave signal and the horizontal sync signal. This output is applied to a frequency control terminal of the VCO. The output of the VCO is thus synchronized in frequency to the horizontal sync signal. The circuit described above is termed an AFC loop.

In the AFC loop described above, it is important that the sawtooth wave signal generated from the integrating circuit has steady slant portions, that is, the slant portions of the sawtooth wave signal have good linearity. However, the characteristics of resistors and capacitors that are employed in the integrating circuit are susceptible to temperature changes, which causes the slant portions of the sawtooth wave signal to fluctuate.

The sawtooth wave signal output from the integrating circuit is given as a function Ao which is RC A0 = E0(1 - e ), E,: the amplitude of the pulse input to the integrating circuit, t: time in second, RC: the time constant of the integrating circuit.

The slope q of the sawtooth wave signal is thus

where 0 ' t ~ T ( being the pulse width of pulse input to the integrating circuit). It will be seen from the above equation that the slope of the output sawtooth wave signal is influenced by changes of the time constant with temperature change. This means that the sensitivity of the AFC detector circuit is also changed with temperature change. Under the constant sensitivity of the AFC detector circuit, an output voltage from AFC detector circuit, is in proportion to a phase difference between the sawtooth wave signal and the horizontal sync signal always changes linearly in accordance with the change of the phase difference.

Where the sensitivity of the AFC detector circuit varies with temperature change in the above described conventional AFC detector circuit which employs an integrating circuit, accurate output signal can no longer be obtained. Besides, the slant portions of the output of conventional integrating circuit employing the time constant circuit is non-linear, so that the draw-in frequency and the hold frequency of the AFC loop with respect to the centre frequency cannot be equalized. Further, in case of fabricating the AFC loop employing the conventional integrating circuit on IC chip, the capacitor for the time constant circuit cannot but the constructed in an external circuit to the IC chip, so that the large number of connection pins cannot be reduced.

An object of the invention is to provide a phase detector circuit, which alleviates the adverse effects of temperature changes and has for steady and stable sensitivity of phase difference detection when detecting phase difference among a plurality of signals and also reduces the number of required terminal pins in case of implementing itself on an IC circuit.

For achieving the above object, the phase detector circuit according to the present invention comprising: a phase detector including a first differential amplifier and a second differential amplifier, a reference pulse signal and a comparison pulse signal being applied to first input terminals of said respective first and second differential amplifiers, preset bias voltages of first and second DC bias voltage sources being applied to second input terminals of said respective first and second differential amplifiers, said second differential amplifier providing from an output terminal thereof a phase detection pulse of a pulse width proportional to the phase difference between the reference pulse and comparison pulse, a buffer circuit connected to the output terminal of said second differential amplifier, for extracting said phase detection pulse output, a gate circuit connected to an output terminal of said buffer circuit, a current path of said buffer circuit between a phase detection pulse input terminal and an output terminal being onoff controlled by said reference pulse signal, said buffer circuit providing an output pulse while said current path is in the "on" state, the pulse duty of said output pulse varying according to the pulse width of said phase detection pulse, and a filter for receiving the output of said gate circuit.

This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram showing a color signal processing circuit to which the present invention is applied; Figure 2 is a circuit diagram showing an embodiment of the present invention; and Figure 3 is a waveform diagram showing signal waveforms at various parts of the circuit of Fig. 2.

Fig. 1 shows a color signal processing circuit for a video tape recorder (VTR), particularly a circuit for recording operation. The color signal (with subcarrier having a frequency of 3.58 MHz) separated from the video signal is applied through an input terminal 11 to a first input terminal of a first balanced modulator 1 2 and then converted to a low frequency converted color signal described later in detail. The converted color signal is then filtered out through a filter 1 3 to an output terminal 14.

The original color signal is also applied to an automatic phase control detector (abbreviated as APC detector) 1 5 which constitutes part of an automatic phase control loop (APC loop). In the APC detector 15, so that the burst signal included in the original color signal is compared in phase with the output (at 3.58 MHz) from a first VCO 18 among the gating period according to the burst pulse. The resultant voltage which corresponds to the phase difference between the burst signal and the output of the first VCO 18 is sampled and held by a following sample-andhold circuit 1 6 under the control of the burst gating pulse.The output voltage of the sampleand-hold circuit 1 6 is coupled through a low-pass filter 1 7 to an oscillation frequency control terminal of the first VCO 1 8. Thus, the output of the first VCO 18 is locked in phase to the burst signal.

The output of the VCO is also fed to a first input terminal of a second balanced modulator 1 9.

To a second input terminal of the second balanced modulator 1 9 is fed an output (688 KHz) of a frequency divider 29, which divides the frequency (2.7 MHz) of the output of second VCO 27 to 1/4.

The output of the second balanced modulator 19 thus has a frequency of 3.58 MHz + 688 kHz or roughly 4.2 MHz. This output (4.2 MHz) is applied through a filter 20 to a second input terminal of the first balanced modulator 1 2 as a converting signal. The original color signal is modulated at the first balanced modulator 1 2 with the output or the converting signal from the filter 20. As a result, the low frequency converted color signal is obtained at the output terminal of the first balanced modulator 1 2.

The second VCO 27 is automatically frequency controlled such that its output frequency (175 X fH = 27 lvi Hz) is synchronized to the horizontal sync signal frequency fah).

In the color signal processing system for a video tape recorder, the frequency (688 kHz) of the low frequency converted color signal has to be synchronized to the frequency (fH) of the horizontal sync signal included in the video signal. Accordingly, this is because of the fact that the horizontal sync signal variations have effects upon the color signal phase variations. The circuit that is involved is designed to maintain a constant relation of the low frequency converted color signal frequency and horizontal sync signal frequency to each other.

The video signal is fed through an input terminal 21 to a sync separator 22. The sync separator 22 separates the horizontal sync signal from the video signal. The horizontal sync signal is applied to a first input terminal of a phase detector 23 and also to a gating pulse input terminal of a gate circuit 25 both being included in a second AFC loop. To a second input terminal of the phase detetor 23 is applied the output (5fH) of a frequency divider 28, which divides the output frequency (175 X fH = 2.7 MHz) of the second VCO 27 to 1/35.

The difference between phase detector 23 detects the phases of the horizontal sync signal and the frequency divider output, and provides a phase detection pulse output which corresponds to the deviation from synchronization between the horizontal sync signal (at fH = 15.37 kHz) and the frequency divider output (at 5fH). The phase detector output pulse is applied through a buffer 24 to the gate circuit 25. In the gate circuit 25, the path between its phase detection pulse input terminal and output terminal is enabled, i.e., rendered conductive, during the horizontal sync signal period, thus producing an output pulse of a pulse duty proportional to the pulse width of the phase detection pulse.

The invention can be effectively applied to the circuit composed of the phase detector 23, buffer 24 and gate circuit 25 shown in Fig. 1.

Fig. 2 shows a specific circuit construction of an embodiment of the invention. Referring to the Figure, labeled e1 is a reference pulse signal (for instance the horizontal sync signal) from a first signal source, and labeled e2 is a compared pulse signal (for instance a frequency divider output) from a second signal source (for instance a VCO). Labeled E, is a first DC bias voltage source, and labeled E2 is a second DC bias voltage sorce. The second DC bias voltage E2 is applied to the base of a transistor Q1. The transistor Q has its collector connected to the first DC bias voltage source E1 and its emitter connected in series with resistor R, and R2 to a reference potential terminal. The emitter of the transistor Q, is also connected in series with resistors R3 and R4 to the collector of a transistor 02.The transistor Q2 has its emitter connected to the reference potential terminal and its base upon which the aforementioned reference pulse signal e1 is impressed.

The compared pulse signal e2 is applied to the base of a transistor Q3. The first DC bias voltage sorce E1 is connected through resistors R5 and R6 to the collector of the transistor Q3, and this collector is connected through a resistor R7 to the base of the transistor Q4. The transistor Q4 has its emitter connected to the reference potential terminal and its collector to which the DC bias E, is applied through resistors R8 and R9. The collector of the transistor Q4 is also connected through a resistor R10 and a diode D, to the reference potential terminal. The diode D, is a temperature compensation diode.

The juncture between the resistor R, and R2 is connected to the bases of transistors 0, and Q,3, and the juncture between the resistors RB and R9 is connected to the base of a transistor 0. In other words, the potential at the juncture between the resistors R, and R2 is set as the base bias for the transistors 0, and Q,3, and the potential at the juncture between the resistors R8 and R9 is set as the base bias for the transistor Q8. Transistors Q5 and Q6 form a first differential amplifier A, transistors Q7 and Q8 form a second differential amplifier B, and transistors Q12 and Q13 form a third differential amplifier C.

The reference pulse e1 is applied through the transistor Q2 and resistor R4 to the base of the transistor Q5 of the first differential amplifier A and also to the base of the transistor Q12 of the second differential amplifier C. The compared pulse signal e2 is applied through the transistor Q3 and resistor RB to the base of the transistor Q7 of the second differential amplifier B. The transistors Q5 and Q6 have their emitters commonly connected to the collector of a transistor Qg which forms a current source. The emitter of the transistor Qg is connected through a resistor R12 to the reference potential terminal.The first DC bias voltage source E1 is connected to the collector of the transistor Q5 and the transistors Q7 and Q8 have their emitters commonly connected to the collector of the transistor Q6. The first DC bias voltage source is directly connected to the collector of the transistor Q7 and it is also connected through a resistor R" to the collector of the transistor Q8. The collector of the transistor Og iS also connected to the base of a transistor 010 which is a component element of the buffer 24.

The first differential amplifier A is constituted by the transistors Q5 and Q6 and the second differential amplifier B is constituted by the transistors Q7 and Q8 form the phase detector 23.

The transistor 0,, of the buffer 24 has its collector to which the first DC bias voltage source E, is connected and its emitter connected to the collector of a transistor 011. The transistor Q11 forms a constant current source, and its emitter is connected to the reference potential terminal.

The emitter of the transistor Qrois connected to the output terminal of the buffer 24, and it is connected through a resistor R,4 to the base of a transistor 014.

The transistors Q,,, Q,2 and Q,3 form the gate circuit 25. The collector of the transistor Q,2is connected to the base of the transistor Q,,, which has its emitter connected to the collector of the transistor Q,3. The first DC bias voltage source E, is connected to the collector of the transistor Q14. The transistors Q12 and Q,3 have their emitters commonly connected to the collector of a transistor Cl15 which forms a constant current source. The emitter of the transistor Q15 is connected through a resistor R15 to the reference potential source. The emitter of the transistor Q14 is connected to the filter 26.

A series circuit including a resistor R16, a diode D2 and a resistor R1, sets the base bias for the constant current source transistors Q9, Q1. and Q15. The diode D2 serves the roles of bias setting and termperature compensation. The current through the collector-emitter path of the transistor Q, is set equal to the current through the diode D2. In other words, the current path formed by the transistor Qg and resistor R12 and that by the resistor Rut6, diode D2 and resistor R,7 form a current mirror circuit.

The operation of the phase detector 23, buffer 24 and gate circuit 25, having the above construction, will now be described. It is now assumed that the reference pulse signal e1 and compared pulse signal e2 are related to each other as shown in (a) and (b) in Fig. 3. When the reference pulse signal e1 goes to a high level, the collector on the transistor Q2 is reduced. In consequence, the signal to the base of the transistors Q, and Q12 goes to a low level as shown in (c) in Fig. 3. When the compared pulse signal e2 goes to a high level, the collector potential on the transistor O3 is reduced. In consequence, the signal to the base of the transistor Q8 goes to a low level as shown in (d) in Fig. 3. The transistors Q6 and Oa are both on state during a period t shown in (e) in Fig. 3.During this period t, a pulse as shown in (e) in Fig.3 prevails at the base of the transistor Q10 The current through the transistor Q10 is controlled by the pulse shown in (e) in Fig. 3.

When the reference pulse e1 goes to a high level, the transistor Q12 is cut off, while the transistor Q13 is triggered. (While the reference pulse a1 is at the low level, the transistor Q12 is "on" and the transistor Q13 is "off".) Thus, the base potential on the transistor Q14 is increased when the transistor Q12 is cut off and is reduced when the current through the transistor Q10 is subsequently controlled. The signal to the base of the 14 thus has a waveform as shown in (f) in Fig. 3, and a signal as shown in (g) in Fig. 3 appears from the emitter of the transistor Q14.In other words, in the gate circuit 25, the current path between the phase detection pulse input terminal and output terminal is conductive while the reference pulse e1 is at the high level, and during this period the pulse duty of the output pulse is set. When the reference pulse and compared pulse go to high level at the same time a phase detection pulse can be obtained, a pulse width of said phase detection pulse proportion between the reference pulse and compared pulse, to the collector of transistor Q8. Thus, the output (as shown in (h) in Fig. 3) of the filter 26 can be utilized as a voltage which corresponds to the phase difference between the reference pulse and compared pulse.

The current I through the emitter of the transistor Qg in the automatic frequency control phase detector 26 is given as E, -- VF R17 I = . .. (1) R16 + R17 R12 VF: the forward voltage across the diode D2, R12: the resistance of the resistor R,2, the the resistance of the resistor R18, the the resistance of the resistor R17.

This means that the current path constituted by the resistor R,6, diode D2 and resistor R17 and that constituted by the transistor Q9 and resistor R,2 form a current mirror circuit.

The sensitivity y of the phase detector 26 is given as R17 R11 E1 - VF IL = . . (V/sec) ... (2) R16 + R17 R12 T1 under the assumption that X 2 T2 where s1 is the pulse width of the reference pulse e1 and T2 is the pulse width of the compared pulse e2.

As is seen from the above equation, the sensitivity of the phase detector is determined by the resistance ratio R1, R11 R1@ R1@ R1@ Since the resistors R", R,2, R,6, R,7, etc. can be realized as distributed resistance within a semiconductor integrated circuit, the error of the aforementioned resistance ratio R17 R" R.6 + R17 R12 can be held within 3%.

Thus, sufficiently high precision of the sensitivity can be obtained. Also, satisfactory linearity of the sensitivity can be obtained as is seen from equation (2).

In equation (2), only VF is dependent upon the temperature. If the circuit constants are selected such that E, > > VF and R,6 > > R17, IL can be approximated as R17 R11 E1 y ~ ~~~ (3) R.6 R12 T1 In this case, the temperature changes have practically no influence upon the sensitivity.

Claims (4)

1. A phase detector circuit comprising: a phase detector including a first differential amplifier and a second differential amplifier, a reference pulse signal and a comparison pulse signal being applied to first input terminals of said respective first and second differential amplifiers, preset bias voltages of first and second DC bias voltage sources being applied to second input terminals of said respective first and second differential amplifiers, said second differential amplifier providing from an output terminal thereof a phase detection pulse of a pulse width proportional to the phase difference between the reference pulse and comparison pulse, a buffer circuit connected to the output terminal of said second differential amplifier, for extracting said phase detection pulse output, a gate circuit connected to an output terminal of said buffer circuit, a current path of said buffer circuit between a phase detection pulse input terminal and an output terminal being controlled to on or off by said reference pulse signal, said buffer circuit providing an output pulse while said current path is in the "on" state, the pulse duty of said output pulse varying according to the pulse width of said phase detection pulse, and a filter for receiving the output of said gate circuit.

2. A phase detector circuit according to claim 1, which comprises: a first transistor having the base connected through a first resistor to said first DC bias voltage source and also connected through a diode and a second resistor to a reference potential terminal and the emitter connected through a third resistor to said reference potential terminal; a second transistor having the emitter connected to the collector of said first transistor, the base connected to a signal line to which said reference pulse signal is applied and the collector connected to said first DC bias voltage source; a third transistor having the emitter connected to the emitter of said second transistor and the base connected to a first biasing means, said second and third transistor constituting said first differential amplifier;; a fourth transistor having the emitter connected to the collector of said third transistor, the base connected to a signal line to which said comparison pulse signal is applied and the collector connected to said first DC bias voltage source; and a fifth transistor having the emitter connected to the emitter of said fourth transistor, the base connected to a second biasing means, and the collector connected through a fourth resistor to said first DC bias voltage source, said forth and fifth transistors constituting said second differential amplifier.

3. A phase detector circuit comprising: a multiplying circuit supplied with a first signal with reference phase and frequency and a second signal being phase-detected to deliver a multiplied result at an output terminal; a signal transmission path for transmitting to a hold circuit a signal obtained at the output terminal of said multiplying circuit; and means for controlling the interruption of said signal transmission path in synchronism with said first signal with the reference phase, thereby obtaining at said hold circuit a signal in accordance with phase difference between said first and second signals.

4. A phase detector circuit, substantially as hereinbefore described with reference to the accompanying drawings.