GB2091337A

GB2091337A - Electrical combination lock

Info

Publication number: GB2091337A
Application number: GB8138112A
Authority: GB
Original assignee: Individual
Current assignee: Individual
Priority date: 1980-12-19
Filing date: 1981-12-17
Publication date: 1982-07-28
Also published as: GB2091337B

Abstract

An electrical combination lock comprising a keyboard means for entering a sequence of signals; comparison circuitry for comparing an entered sequence of signals with a preset sequence, so that a lock releasing signal is produced in response to the correspondence of the entered and preset sequences of signals and an alarm-operating signal in response to the non- correspondence of the entered and preset sequence of signals. The alarm-operating signal, when produced, is fed to operate an alarm; and the subsequent entry of a sequence of signals in correspondence with the preset sequence cancels the alarm. The lock may for example be used as an ignition/door lock for a vehicle.

Description

SPECIFICATION Electrical combination lock This invention relates to electrical combination locks, and in particular to such locks which cause an alarm to be actuated if an incorrect combination is entered.

According to the present invention there is provided an electrical combination lock comprising signailing means for entering a sequence of signals; electrical signal comparison means for comparing an entered sequence of signals with a preset sequence, and operative to produce a lock releasing signal in response to the correspondence of the entered and preset sequences of signals and an alarm-operating signal in response to the noncorrespondence of the entered and preset sequences of signals; wherein said alarm-operating signal, when produced, is fed to operate an alarm; and wherein the subsequent entry of a sequence of signals in correspondence with the preset sequence cancels the alarm.

The electrical signal comparison means may include a first detection means which assumes a 'failure' output state in response to the noncorrespondence of any one of an entered sequence of signals and the appropriate one of the preset sequence of signals, and remains in this state until the end of the entered sequence, a second detection means which is arranged to respond to the output state of the first detection means at the end of a complete entered sequence and assumes a 'failure' output state when said 'failure' output state of the first detection means is present at the end of an entered sequence, and to assume a 'lock release' output state when the first detection means is not in a 'failure' output state at the end of an entered complete sequence of signals.

The lock may include synchronisation means operative to synchronise the comparison of signals at the corresponding positions of the entered sequence and the preset sequence and to enable the second detection means at the end of a complete entered sequence of signals.

An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawing, which is a diagram of the circuitry employed in a lock according to the present invention.

This embodiment of the invention is an electronic combination lock which may be used on a motor vehicle as a door and/or ignition lock, or on a variety of other equipment such as computer terminals, where the lock has to be successfully released to gain access to the stored data. The lock is released by the successful entry of a nine digit combination. The person attempting to release the lock enters the combination on a keyboard and this is compared by the electronic circuitry with the combination code previously entered by means of eight concealed thumb wheel switches. The ninth digit of the correct entered combination is any one of the fifteen alphanumeric digits on the keyboard.

Referring now to the circuit diagram, each thumb wheel is connected to a hexadecimal switching arrangement comprising four switch panels 1A--l D. Each switch panel has eight switches and is connected to the thumb wheels such that, for example, if the thumb wheel number 7 is set to the numeral 9 then the 7th place on each of the panels lA-i D are in succession ON, OFF, OFF, ON. Thus each 7th switch on the panels 1 A to 1 D controls a corresponding binary digit of a four-bit hexadecimal word representing the 7th numeral in the combination.Each thumb wheel can be used to set one on fifteen symbols; numerals 1-9 and letters A-E. Each switch on each of the panels 1 A-1 D is connected to one terminal of a respective two-input AND gate 2 and each of the output terminals of the AND gate 2 associated with each panel is connected to a separate input terminal of an eight-input NOR gate 3A-3D. Each switch on the panels 1A--l controls the connection of its associated AND gate 2 to the positive DC supply rail and thus any switch which is on causes a logic HIGH to be applied to one input of its associated AND gate 2.

Another input to each of the individual AND gates forming the set of AND gates 2 is an output from a shift register 4 arranged to operate as a ring counter. In particular, seven parallel outputs from the shift register 4 numbered 2 to 8 on the drawing are connected such that parallel output no. 8 is connected to each of the four AND gates 2 associated with switch no. 8 of the panels 1 A to 1 D, the parallel output no. 7 is connected to each of the four AND gates 2 associated with the switch no. 7 of the panels 1A--l D and so on. The input to the four AND gates 2 associated with the switch no. 1 of each of the panels 1 A-1 D is connected to the output terminal of a NOR gate 6 whose inputs are connected to each of the seven parallel outputs of the shift register 4.Thus the NOR gat 6 provides a HIGH output signal when each of the seven parallel outputs of the shift register are LOW and is LOW when any one of the seven parallel outputs is high. The output from the NOR gate is also connected to the input to the shift register 4. The shift register operates by causing each of the seven parallel outputs and the output from the NOR gate 6 to go HIGH in succession controlled by a KEY signal, the origin of which is described below.

A person attempting to operate the combination lock to unlock it operates a keyboard 7 having sixteen operable keys thereon representing the numsrals 0 to 9 and 1 6 letters A to E and a RESET key. The output terminal from each key is connected to a decoder 8 which responds to a selection of any key by producing an appropriate four-bit word (i.e. a single hexadecimal digit), each bit being transmitted on one of four parallel output channels from the decoder 8.

Operation of the reset key produces a hexadecimal F i.e. a HIGH output signal on each of the parallel outputs from the decoder 8.

Each of the four parallel outputs from the decoder 8 is connected to one input of a respective exclusive-OR gate 9, 10, 11 and 12.

The other input to the XOR gate 9 is provided by the output of the NOR gate 3D, the other input to the XOR gate 10 is provided by the NOR gate 3C and similarly with the gates 11 and 12 and the NOR gates 3A and 3B. The XOR gates 9-12 are the primary part of the means for comparing the combination set by the thumb wheel switches and the number entered at the keyboard 7. A further output terminal of the decoder 8, identified as terminal K on the diagram, produces a HIGH output upon the release of each operated key and this output is communicated to the key input of the shift register 4. Thus following each occasion a key is pressed on the keyboard 7 the shift register puts a HIGH output on one of its parallel outputs and enables one of the AND gates 2 of each of the switch panels 1 A-1 D.

Thus initially the AND gate 2 associated with the switch No. 1 of each of the panels 1 A-1 D is enabled, and assuming for example that No. 1 switches represent the number 9 then the AND gate 2 associated with switch 1 of panel 1 A has a HIGH output, the corresponding AND gate on panel 18 has a LOW output, the corresponding AND gate of panel 1 C has a LOW output and the corresponding AND gate on panel 1 D has a HIGH output. Upon passage through the respective NOR gates 3A to 3D the signals from the AND gates 2 are inverted and thus the hexadecimal digit represented by the outputs of the NOR gates 3A to 3D is the complement of the number entered by the first thumb wheel. Each bit of the hexadecimal digit is applied to one of the exclusive OR gates 9 to 12 along with the corresponding bit of the hexadecimal digit from the decoder 8.Since the number entered in the keyboard should correspond to the number entered on the first thumb wheel and since the output of the NOR gates 3 is a complement of the number entered on the thumb wheel, then if a number is entered correctly on the key board each of the exclusive OR gates 9 to 12 will have a HIGH signal at one input terminal and a LOW signal on the other input terminal and therefore will produce a HIGH output.

The outputs from the four exclusive OR gates 9-12 each form the respective input to a fourinput NAND gate 13, the output of which is LOW if the correct numeral is entered at the key board.

The output from the NAND gate 13 is connected to one input terminal of an AND gate 14. The other input terminal of the AND gate 14 is connected via a pulse shaping circuit comprising a capacitor 15, a diode 1 6 and an inverting gate 1 7 to the terminal K of the decoder 8. The terminal K gives a HIGH output upon the release of each operated key and therefore enables the AND gate 14 just following each entry; the AND gate 14 then produces a HIGH output when it sees that the output from the NAND gate 13 is HIGH. If a correct number has been entered into the key board the output from the AND gate 14 is LOW.

The output terminal from the AND gate 14 is connected to the DATA input terminal of a D-type bistable circuit 1 8 which is triggered by the positive edge of a clock signal derived from the output of the AND gate 14 via two inverters 19 and 20. The Q output of the bistable 1 8 is connected to one input of an AND gate 21 whose other input is provided by a connection to a further output terminal E of the shift register 4 which provides a HIGH output following the next shift pulse after eight numbers have been entered. This shift pulse occurs upon the further operation of any one of the fifteen keys on the keyboard.

Thus effectively the AND gate 21 looks at the output of the bistable 1 8 at the end of a sequence of key board entries. The output from the AND gate 21 is connected to the DATA input of a further D-type bistable 22. An AND gate 23 receives the signal from the E terminal of the shift register 4 at both its inputs and its output is connected via pulse delay gates 24 and 25 and a pulse-shaping capacitor 26 to the clock input of the bistable 22. The clock input is triggered by the positive edge of the clocking signal. The RESET and SET inputs to the bistable 22 are held permanently LOW.

Each of the four parallel outputs from the decoder 8 are also connected as respective inputs to a four-input NAND gate 28. The output terminal of the NAND gate 28 is connected via an inverter 29 to the RESET inputs of the first D-type bistable 1 8 and the shift register 4.

The Q output from the bistable 22 is connected to an alarm operating circuit (not shown) and to a LED 30 which indicates that the alarm has been operated. TheB output from the bistable 22 is connected to an AND gate 31 whose output controls the energisation of a further LED 32. The LED 32 operates to indicate that the mechanism of the lock has been released. The release is accomplished by means of the same signal which operates a pair of transistors to actuate a 50 v 2 amp release circuit. The other input to the AND gate 31 comes from the terminal E of the shift register 4, and thereby ensures that the lock is only released at the end of a complete entered sequence.

The person attempting to release the lock enters nine numbers by pressing a sequence of keys on the key board 7. Upon the release of each key the signal from the key output of the decoder 8 causes the shift register 4 to shift its HIGH output to the next parallel output. Thus each entered number is converted to hexadecimal and compared with the complement of the appropriate one of the preset sequence of signals and if they correspond the output state of the NAND gate 1 3 remains LOW. Upon the operation of each key the KEY signal from the decoder 8 enables the AND gate 14 and its output controls the output of bistable 1 8. Thus the bistable produces a HIGH output when any entered number is incorrect, and remains latched until reset at the end of the entered sequence. The reset signal is produced by the operation of the RESET key on the key board which causes a hexadecimal F output from the decoder which is fed to the NAND gate 28.

The RESET signal is also fed to the shift register 4 to reset it. The AND gate 21 is however enabled only when the shift register has cycled through all its outputs and produces a HIGH at its E output.

The gate 21 detects whether a HIGH, i.e. 'fail', output is present at the bistable 1 8. If it is then the alarm is operated as described above by means of a HIGH at the Q output of bistable 22. The E output from the shift register 4 also enables the AND gate 31 at the end of an entered sequence. If a fail signal is not present at the bistable 18 then the Q output from the bistable 22 is high and the AND gate 31 produces a HIGH output and causes the lock to be released.

The alarm, once operated, can only be turned off by the subsequent entry of a complete correct sequence, since the AND gate 21 is only enabled by the shift register 4 and hence enable the bistable 22 to change state, when the shift register has shifted through all its parallel outputs and finally produces a HIGH at its E output.

Claims

1. An electrical combination lock comprising signalling means for entering a sequence of signals; electrical signal comparison means for comparing an entered sequence of signals with a preset sequence, and operative to produce a lock releasing signal in response to the correspondence of the entered and preset sequences of signals and an alarm-operating signal in response to the noncorrespondence of the entered and preset sequences of signals; wherein said alarm-operating signal, when produced, is fed to operate an alarm; and wherein the subsequent entry of a sequence of signals in correspondence with the preset sequence cancels the alarm.

2. An electrical combination lock as claimed in claim 1 including means operable to select the preset sequence of signals.

3. An electrical combination lock as claimed in claim 1 or claim 2 including signal conversion means operative to convert each signal entered into an n-bit binary word and said signal comparison means compares an entered sequence of n-bit binary words with n-bit binary words derived from the preset sequence of signals.

4. An electrical combination lock as claimed in any one of the preceding claims wherein the electrical signal comparison means includes a first detection means which assumes a 'faiiure' output state in response to the non-correspondence of any one of an entered sequence of signals and the appropriate one of the preset sequence of signals, and remains in this state until the end of the entered sequence; a second detection means which is arranged to respond to the output state of the first detection means at the end of a complete entered sequence and assume a 'failure' output state when said 'failure' output state of the first detection means is present at the end of an entered sequence, and to assume a lock release output state when the first detection means is not in a 'failure' output state at the end of an entered complete sequence of signals.

5. An electrical combination lock as claimed in claim 4 wherein the first and second detection means are D-type bistable circuits.

6. An electrical combination lock as claimed in claim 4 or claim 5 including synchronisation means operative to synchronise the comparison of signals at the corresponding positions of the entered sequence and the preset sequence and to enable the second detection means at the end of a complete entered sequence of signals.

7. An electrical combination lock as claimed in claim 6 wherein the synchronisation means comprises a shift register having parallel outputs, arranged to be enabled in succession.

8. An electrical combination lock as claimed in any one of the preceding claims adapted as a lock for the ignition circuit of a motor vehicle.

9. An electrical combination lock as claimed in any one of the preceding claims adapted as a lock for a door of a motor vehicle.

10. An electrical combination lock substantially as hereinbefore described with reference to and as illustrated in the accompanying drawing.